CN101290794B - 一种到达接口总线的集成电路及其构成的存储器 - Google Patents
一种到达接口总线的集成电路及其构成的存储器 Download PDFInfo
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- CN101290794B CN101290794B CN200710123316XA CN200710123316A CN101290794B CN 101290794 B CN101290794 B CN 101290794B CN 200710123316X A CN200710123316X A CN 200710123316XA CN 200710123316 A CN200710123316 A CN 200710123316A CN 101290794 B CN101290794 B CN 101290794B
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- 230000001105 regulatory effect Effects 0.000 claims abstract description 11
- 239000012536 storage buffer Substances 0.000 claims abstract description 11
- 239000000872 buffer Substances 0.000 claims description 41
- 238000005070 sampling Methods 0.000 claims description 14
- 230000005540 biological transmission Effects 0.000 claims description 13
- 230000008878 coupling Effects 0.000 claims description 13
- 238000010168 coupling process Methods 0.000 claims description 13
- 238000005859 coupling reaction Methods 0.000 claims description 13
- 238000012546 transfer Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 11
- 238000012549 training Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Information Transfer Systems (AREA)
- Static Random-Access Memory (AREA)
- Memory System (AREA)
Abstract
Description
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/735,915 US7865660B2 (en) | 2007-04-16 | 2007-04-16 | Calibration of read/write memory access via advanced memory buffer |
US11/735,915 | 2007-04-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101290794A CN101290794A (zh) | 2008-10-22 |
CN101290794B true CN101290794B (zh) | 2012-01-11 |
Family
ID=39854791
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200710123316XA Active CN101290794B (zh) | 2007-04-16 | 2007-06-20 | 一种到达接口总线的集成电路及其构成的存储器 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7865660B2 (zh) |
CN (1) | CN101290794B (zh) |
TW (1) | TW200842589A (zh) |
WO (1) | WO2008130418A2 (zh) |
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US8438328B2 (en) * | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
JP4878215B2 (ja) * | 2006-05-26 | 2012-02-15 | ルネサスエレクトロニクス株式会社 | インタフェース回路及びメモリ制御装置 |
WO2009042329A2 (en) | 2007-09-27 | 2009-04-02 | Rambus Inc. | Reconfigurable memory system data strobes |
US8131915B1 (en) | 2008-04-11 | 2012-03-06 | Marvell Intentional Ltd. | Modifying or overwriting data stored in flash memory |
US8683085B1 (en) | 2008-05-06 | 2014-03-25 | Marvell International Ltd. | USB interface configurable for host or device mode |
EP2288993A4 (en) * | 2008-05-29 | 2012-05-09 | Advanced Micro Devices Inc | PROGRAMMABLE COMPONENT INCORPORATED FOR MEMORY DEVICE LEARNING |
US8611151B1 (en) | 2008-11-06 | 2013-12-17 | Marvell International Ltd. | Flash memory read performance |
US8947929B1 (en) | 2008-11-06 | 2015-02-03 | Marvell International Ltd. | Flash-based soft information generation |
DE102009004565B4 (de) * | 2009-01-14 | 2015-04-02 | Texas Instruments Deutschland Gmbh | Vorrichtung und Verfahren zum Zwischenspeichern von Daten zwischen Speichercontroller und DRAM |
US8423710B1 (en) | 2009-03-23 | 2013-04-16 | Marvell International Ltd. | Sequential writes to flash memory |
US8213236B1 (en) | 2009-04-21 | 2012-07-03 | Marvell International Ltd. | Flash memory |
JP5649293B2 (ja) * | 2009-08-27 | 2015-01-07 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | メモリモジュール |
TWI404339B (zh) * | 2009-11-25 | 2013-08-01 | Mstar Semiconductor Inc | 記憶體信號相位調整方法 |
US8756394B1 (en) * | 2010-07-07 | 2014-06-17 | Marvell International Ltd. | Multi-dimension memory timing tuner |
JP2012059184A (ja) * | 2010-09-13 | 2012-03-22 | Nec Computertechno Ltd | メモリコントローラ、これを備えたメモリシステム及びメモリデバイスの制御方法 |
WO2012064638A2 (en) | 2010-11-09 | 2012-05-18 | Rambus Inc. | Memory access during memory calibration |
BR102014024441A2 (pt) * | 2014-03-26 | 2016-08-02 | Mediatek Inc | método para otimização de parâmetro em inicialização de sistema e aparelho utilizando o mesmo |
US10275386B2 (en) * | 2014-06-27 | 2019-04-30 | Advanced Micro Devices, Inc. | Memory physical layer interface logic for generating dynamic random access memory (DRAM) commands with programmable delays |
US9846606B2 (en) * | 2014-11-07 | 2017-12-19 | Mediatek Inc. | Storage device calibration methods and controlling device using the same |
US10261697B2 (en) | 2015-06-08 | 2019-04-16 | Samsung Electronics Co., Ltd. | Storage device and operating method of storage device |
US10068634B2 (en) | 2016-03-16 | 2018-09-04 | International Business Machines Corporation | Simultaneous write and read calibration of an interface within a circuit |
KR102649888B1 (ko) * | 2016-11-29 | 2024-03-22 | 에스케이하이닉스 주식회사 | 트레이닝 장치 및 이를 포함하는 반도체 시스템 |
US10090065B1 (en) | 2017-03-14 | 2018-10-02 | International Business Machines Corporation | Simultaneous write, read, and command-address-control calibration of an interface within a circuit |
US10592121B2 (en) * | 2017-09-14 | 2020-03-17 | Samsung Electronics Co., Ltd. | Quasi-synchronous protocol for large bandwidth memory systems |
US10410698B2 (en) * | 2017-12-07 | 2019-09-10 | Micron Technology, Inc. | Skew reduction of a wave pipeline in a memory device |
US10579280B2 (en) * | 2018-06-28 | 2020-03-03 | Montage Technology Co., Ltd. | On-die termination control for memory systems |
US10318464B1 (en) * | 2018-06-28 | 2019-06-11 | Montage Technology Co., Ltd. | Memory system and method for accessing memory system |
KR102639707B1 (ko) * | 2018-07-31 | 2024-02-26 | 에스케이하이닉스 주식회사 | 메모리 장치 |
CN111124978B (zh) * | 2019-10-30 | 2021-07-06 | 苏州浪潮智能科技有限公司 | 一种并行总线相位校正的方法及装置 |
CN112052043B (zh) * | 2020-08-10 | 2022-07-01 | 烽火通信科技股份有限公司 | 嵌入式系统内存条参数适配方法、装置、设备及存储介质 |
US11775004B2 (en) * | 2021-09-10 | 2023-10-03 | International Business Machines Corporation | Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module |
CN116206648B (zh) * | 2022-01-27 | 2024-02-20 | 北京超弦存储器研究院 | 动态存储器及其读写方法、存储装置 |
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US20030041224A1 (en) * | 1998-05-07 | 2003-02-27 | Kabushiki Kaisha Toshiba | High speed data transfer synchronizing system and method |
CN1577627A (zh) * | 2003-07-08 | 2005-02-09 | 因芬尼昂技术股份公司 | 半导体记忆模块 |
US20060259666A1 (en) * | 2005-05-10 | 2006-11-16 | Jung-Bae Lee | Memory systems, modules, controllers and methods using dedicated data and/or control busses |
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JPH0862308A (ja) * | 1994-08-22 | 1996-03-08 | Advantest Corp | 半導体試験装置の測定信号のタイミング校正方法及びその回路 |
US6390579B1 (en) * | 1999-04-15 | 2002-05-21 | Hewlett-Packard Company | Pulse width modulator using delay-line technology with automatic calibration of delays to desired operating frequency |
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US7437491B2 (en) * | 2005-11-02 | 2008-10-14 | Sun Microsystems, Inc. | Clock and data recovery wherein an FB-DIMM is connected to signal path and null and sync frames control the FB-DIMM |
JP4823009B2 (ja) * | 2006-09-29 | 2011-11-24 | 株式会社東芝 | メモリカード及びホスト機器 |
-
2007
- 2007-04-16 US US11/735,915 patent/US7865660B2/en active Active
- 2007-06-15 WO PCT/US2007/071392 patent/WO2008130418A2/en active Application Filing
- 2007-06-20 CN CN200710123316XA patent/CN101290794B/zh active Active
- 2007-07-19 TW TW096126325A patent/TW200842589A/zh unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20030041224A1 (en) * | 1998-05-07 | 2003-02-27 | Kabushiki Kaisha Toshiba | High speed data transfer synchronizing system and method |
CN1577627A (zh) * | 2003-07-08 | 2005-02-09 | 因芬尼昂技术股份公司 | 半导体记忆模块 |
US20060259666A1 (en) * | 2005-05-10 | 2006-11-16 | Jung-Bae Lee | Memory systems, modules, controllers and methods using dedicated data and/or control busses |
Also Published As
Publication number | Publication date |
---|---|
WO2008130418A3 (en) | 2009-04-09 |
WO2008130418A2 (en) | 2008-10-30 |
TW200842589A (en) | 2008-11-01 |
US7865660B2 (en) | 2011-01-04 |
US20080256282A1 (en) | 2008-10-16 |
CN101290794A (zh) | 2008-10-22 |
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