CN101288178A - Insulated gate field effect transistors - Google Patents

Insulated gate field effect transistors Download PDF

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Publication number
CN101288178A
CN101288178A CNA2005800412443A CN200580041244A CN101288178A CN 101288178 A CN101288178 A CN 101288178A CN A2005800412443 A CNA2005800412443 A CN A2005800412443A CN 200580041244 A CN200580041244 A CN 200580041244A CN 101288178 A CN101288178 A CN 101288178A
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unit
groove
now
effect transistor
field
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亚当·布朗
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A vertical power MOSFET includes active cells 8 and inactive cells 10. The active cells 8 are surrounded by inactive cells 10 on the surface of the substrate, and are fewer in number. The MOSFET may have a lower zero temperature coefficient current than cells in which all cells are active.

Description

Insulated gate FET
Technical field
The method that the present invention relates to a kind of insulated gate FET and use described insulated gate FET.
Background technology
Power metal oxide semiconductor field-effect transistor (MOSFET) usually as or fully conducting or the switch that ends fully.Yet, also MOSFET can be used for the linear work district, typically using the dynamic current circuit, by conducting and absorb power, come the described MOSFET of self-protection in order to avoid the overvoltage spike as the part in linear work district; Or the sufficiently long short time period of restriction electric current is to make the decision of current switching to safe condition.
Other circuit also need to work in linear model.For example, control many simple motor in this manner, for example fan motor.
When modern power MOSFET, especially groove MOSFET and vertical double-diffused MOS FET (VDMOS) go wrong when working in linear zone.Typically, modern device has smaller units spacing (＜10 microns), and these devices are subject to the influence of thermal runaway (thermal runaways).
The reason of thermal runaway is critical current density J in gadget cExistence: more than described critical current density, current density reduces along with the increase of temperature; And below described critical current density, current density increases along with the increase of temperature.If make FET work in critical current density J cBelow, the less increase of temperature has just increased current density, and the increase that this causes temperature causes higher current density, i.e. thermal runaway.
Critical current density J cValue determine by two competition effects.At first, the resistance of raceway groove increases when temperature increases.This is along with the temperature increase has reduced current density.Secondly, when temperature increased, the threshold voltage of MOSFET reduced.When the hard conducting of MOSFET, this variation in the threshold voltage is unimportant.Yet under linear model, the threshold voltage that reduces has changed effective grid voltage, thereby along with the temperature increase has increased current density.When gain increased, second kind of effect became more important relatively.The per unit area grid width that modern MOSFET has higher value, and, make second kind of effect preponderate according to current work, promptly MOSFET works in J cBelow.
This means that power MOSFET is for the thermal runaway sensitivity that may cause device fault.
As it should be understood by one skilled in the art that this problem is not limited to the device that uses oxide on the silicon, and may occur in the power fet arbitrarily.
Therefore, need a kind of FET that alleviates this problem of design.
Exist some to relate to the prior art of this problem.US 5,095, and a solution that presents in 043 has been described the complex arrangement that has plurality of source regions in each this tagma.This device manufactures comparatively complicated.
At US 6,664, another device that presents in 594 has been instructed many kinds of measures.In a kind of measure, the unit is divided into two parts, these two parts have different threshold voltages.Yet this device manufactures still comparatively complicated.
As setting forth among the US 2003/0230766, other measure is used has the different height and the unit of low threshold voltage.Yet, use a plurality of different threshold voltages to make such device be difficult to make once more.
Summary of the invention
According to the present invention, a kind of insulated gate FET according to claim 1 has been proposed.
By a plurality of unit are provided, some unit are that used (active) and some unit are usefulness (inactive) not fully, have strengthened the device operation under the linear model.The present invention has realized need not to provide a plurality of different threshold voltages or having asymmetric channels or the unit of complex form.Needed is to use some of described unit and does not use other of described unit.
Because existing not crowded together with the unit, electric current can distribute on device equably, to avoid focus.Preferably, existing being evenly distributed in the unit do not used in the unit.
Practical benefits of the present invention is to have obtained improved linear properties with the configuration that is highly susceptible to making.
Preferably, the present invention is embodied as vertical transistor, wherein, grid is to extend to insulated gate electrode the substrate from first first type surface.
With this configuration, be easy to provide the power MOSFET of realizing benefit of the present invention.
Described unit can comprise this tagma of FET, has insulated gate electrode in the groove between described unit.Can only in now with the unit, source area be set.
Described unit can be arranged according to hexagonal array, and now with the unit be not 1: 2 with the ratio of unit.Be easy to like this arrange according to hexagonal array, and provide enough existing with the unit to flow through electric current when the break-over of device.
Unit interval can be less than 11 microns.Particularly, the present invention can be applicable to have the device of this junior unit spacing, can be high especially at the device zero-temperature coefficient electrical current, and therefore at described device, thermal instability is special problem.
Now with the unit be not 1: 2 with the ratio of unit.This is the ratio easily that provides better result at moderate unit interval.
Yet,, be that 1: 2 unit ratio may cause unsettled device along with unit interval reduces.In this case, can not use more a spot of unit of now using at each with the unit.Therefore, the present invention includes such device: wherein, unit interval is 8 microns or littler, and now with the number of unit divided by not having 1/3 or littler value with the mark of the number of unit.
In yet another aspect, provide a kind of method according to claim 10.
Limiting transistorized step can comprise:
Etching groove between the unit, groove extends to the substrate from first first type surface;
On the sidewall of groove and bottom, deposit gate insulator; And
Use the grid conductor filling groove.
Limiting transistorized step can also comprise:
Inject p type main body to form the unit; And
After limiting groove, at now with the adjacent source area of the groove in the unit not at do not inject with the adjacent source area of the groove in the unit.
Description of drawings
Now will be only as example, embodiments of the invention are described with reference to the accompanying drawings, wherein:
Fig. 1 shows use existing with the unit with do not use the end view of unit in first embodiment of the invention;
Fig. 2 shows the top view according to the semiconductor device of first embodiment of the invention;
Fig. 3 shows at first embodiment and only uses the curve of the current-voltage comparative example now use the unit, under the different temperatures;
Fig. 4 show at device according to the present invention and comparative example, electric current and voltage is by (pass) value and fault (fail) value; And
Fig. 5 shows the top view of the semiconductor device of the optional embodiment of the present invention.
Embodiment
With reference to figure 1, doped n+Semiconductor substrate 2 is as the drain electrode at the semiconductor device that is made of a plurality of unit 6 at first top main surfaces, 4 places of substrate.The unit is divided into existing with unit 8 with do not use unit 10.For example, substrate can be to have 10 15Cm -3To 10 18Cm -3The commercial silicon substrate of the doping content of scope.Can use alternative material and doping if desired.
With p doped body district 12 be arranged on each active area 8 and with the district 10 in.
Unit 6 is separated by insulated gate electrode groove 14, and described insulated gate electrode groove 14 has at the sidewall of groove and gate insulator on the bottom 16 and the conductor within groove 18, with as grid.
As can be as seen from Figure 2, described unit 6 be distributed on first first type surface 4 of substrate according to hexagonal array, thereby wherein insulated gate electrode groove 14 upwards connects link grid conductor 18.
Now be with unit 8 and difference not with unit 10: now also comprise severe doped n+source area 20 with first first type surface, 4 places of unit in body region 12, and these omissions in usefulness unit 10.
Be arranged on insulator 22 on the groove 14 and partly be arranged on the source area 20 with insulated trench.For example, source area can be a ring-type, stays the part of the center of described ring as body region 12.
Then, metal layer 24 extends on the surface of insulator 22 and first first type surface 4, carries out source electrode with source area 20 with body region 12 and contacts.Groove have 1 micron to 3 microns of scope, with the similar width of the degree of depth.As can be appreciated, gash depth and width can depend on the required device performance and change.
Back side contact 28 is arranged on the back of substrate 2, and grid contact 30 links to each other with grid conductor 18.
The material of standard can be used for these contacts and metallize 24,28,30, for example comprise aluminium and alloy thereof, for example be used for metallized AlSi or polysilicon and, therefore will can further not define for the known various contact materials of those of ordinary skills.Gate insulator 16 can by arbitrarily easily material constitute, for example comprise silica, silicon nitride and silicon oxynitride.Also can use stacked gate if desired.
As shown in Figure 2, now be distributed on the surface of substrate, wherein, will now add shade so that it is not distinguished mutually with using unit 10 with unit 8 with unit 8.Will be seen that in this embodiment pattern be two not with unit 10 and a repeat patterns of now using unit 8, shown in triangle 26, and therefore not with the unit and be 2: 1 now with the ratio of unit.
Unit interval among this embodiment, promptly the distance between the center of adjacent cells is 9 microns.
Can make described device according to traditional relatively technology, so this will describe no longer further.
Yet, need a kind of modification, make and in not with the unit, do not carry out source diffusion.This is not realize with the mask pattern of the whole unit of unit by carrying out implantation step with inject severe doped n+source area 20 in body region 12 before, creating to cover now with the unit center of unit and covering.In this manner, only use establishment source area 20 in the unit now.
At according to the device of this embodiment with only use and now carried out experiment with the comparative example of unit.Figure 3 illustrates two current-voltage features under the temperature.Two curves of high order end relate to comparative example, and two curves of low order end relate to this embodiment.Two temperature at each situation are 25 ℃ and 175 ℃.Zero temperature coefficient point is to need identical voltage to produce the electric current of electric current under different temperatures, that is, and and the electric current of curve intersection.
As can be seen, the about 80A of zero temperature coefficient point from comparative example drops to the about 35A among this embodiment.
Obtained device than good yield.
In linear model, use this embodiment than using comparative example and obtained better stability.Fig. 4 shows some fault points, promptly ought use predetermined amount of time and causes the value of the electric current and the voltage of fault.In some cases, use the time period of 100ms, and in other cases, use the dc signal.At higher than the fault point 34 of example frequently current value place, the fault point of the 100ms of this embodiment is labeled as 32.
Under dc, what be labeled as this embodiment of 36 passes through that point (pass point) appears at and very similar value place, the fault point 38 of comparative example.
As can be seen, this embodiment has produced better result.
Typical R dson (on-state resistance) is 9m Ω and be 5.4m Ω for comparative example for this embodiment.Because it is used that 1/3 unit is only arranged in this embodiment, this is a good result.
The present invention is not limited to above embodiment, and for example, this embodiment has the unit as the transistor bodies that is centered on by groove.Can also be set to transistorized groove in described unit, and p type main body is as groove.In this case, can be by only with the unit grid contact being set at existing, and do not stayed floating grid with the unit, be provided with and now use the unit.
It is hexagonal that the unit needs not be, and can be square, triangle or other suitable shapes arbitrarily.In fact, be not that all unit need all identical.At US 6,320, lectured this shape and configuration in 223, the various cell variations that will wherein lecture especially are included in this as a reference.
As shown in Figure 5, in optional embodiment, first first type surface can be divided into bar 50, now are short zones of bar 50 with unit 8, the remainder composition unit 10 of bar.As can finding out in Fig. 5, some bars are only formed and are not used unit 10.Alternatively, all bars can have existing with the unit with do not use the unit, for example by in adjacent bar, being offset with the unit to showing.
Note, in these embodiments, not with the cell size of unit 10 greater than the cell size of now using unit 8.
But unit that the arrangement (not shown) that uses bar has the form of the bar that be arranged in parallel, the whole length of bar or used or usefulness not.Now using cell stripes (as transistor) to be dispersed in does not use between the cell stripes.
In addition, unit interval needs not to be 9 microns of this embodiment.Particularly, the present invention is suitable for having the device less than 11 micron pitch, because more than the unit interval, also can be stable even do not use this device of the present invention at this.
The present invention can be used for than 9 microns much smaller sizes.If 1: 2 of this embodiment existing with unit and the increase of Linear Stability not being provided for the discrete cell size with the ratio of unit so, can be used now with the unit and do not use the different proportion of unit, may be 1: 4 or 1: 6.The ratio of 1: 4 or 1: 6 is easy to obtain from the rectangular grid of unit.
In addition, can exchange n type and p type doped layer mutually to obtain p type device.
FET can be concrete arbitrarily use required enhancement mode or depletion type.

Claims (14)

1. field-effect transistor comprises:
Semiconductor substrate (2) has first first type surface (4);
A plurality of unit are arranged on the described substrate, and described unit is divided into existing with unit (8) with do not use unit (10),
Each now use unit (8) to define to have insulated gate electrode (16,18), source electrode (22) and drain electrode (2) but at least one operate transistor;
Each does not use unit (10) not operate as transistor;
Wherein, show with transistor than not using unit (10) to lack.
2. field-effect transistor according to claim 1, wherein, on described substrate (6), the described unit (10) of not using is around the described unit (8) of now using.
3. field-effect transistor according to claim 1 and 2 has the form of vertical transistor, and wherein, the grid of described unit (16,18) is the insulated gate electrode that extends in the groove (14) that first first type surface extends in the described substrate.
4. field-effect transistor according to claim 3, wherein, described unit (8) comprises the body region (12) of FET, described insulated gate electrode (18) is arranged in the groove (14) between the described unit, and the source area (20) adjacent with described groove (18) only is arranged on existing with in unit (8).
5. according to the described field-effect transistor of arbitrary aforementioned claim, wherein, described unit is arranged according to the mode of hexagonal array.
6. according to each described field-effect transistor in the claim 1 to 4, comprise: a plurality of (50) of on described substrate, extending, the described length of now using unit (8) to be defined as at least some described (50), all the other described (50) limit does not use unit (10).
7. according to the described field-effect transistor of arbitrary aforementioned claim, wherein, unit interval is less than 11 microns.
8. according to the described field-effect transistor of arbitrary aforementioned claim, wherein, now using unit (8) is 1: 2 with not using the ratio of unit (10).
9. according to each described field-effect transistor in the claim 1 to 5, wherein, unit interval is 8 microns or littler, and the number of now using unit (8) has 1/3 or littler value divided by the mark of the number of not using unit (10).
10. method that is used to make field-effect transistor comprises:
Semiconductor substrate with first first type surface (4) (2) is provided; And
Qualification is arranged on a plurality of unit (6) on the described substrate, described unit is divided into existing with unit (8) with do not use unit (10), each now use unit (8) to define to have insulated gate electrode (16,18), source electrode (22) and drain electrode (2) but at least one operate transistor, each does not use unit (10) not operate as transistor;
Wherein, show with transistor than not using unit (10) to lack.
11. method according to claim 10, wherein, on described substrate (6), the described unit (10) of not using is around the described unit (8) of now using.
12., wherein, limit described transistorized step and comprise according to claim 10 or 11 described methods:
Etching groove (14), described groove extend to the described substrate from first first type surface between described unit;
On the sidewall of described groove (14) and bottom, deposit gate insulator (16); And
Fill described groove (14) with grid conductor (18).
13. field-effect transistor according to claim 12 wherein, limits described transistorized step and also comprises:
Inject p type main body to form described unit (8); And
After limiting described groove, at the source area (20) adjacent and do not inject at the source area (20) adjacent with not using groove (14) in the unit (10) with now using groove (14) in the unit (8).
14., wherein, described unit (6) are arranged according to the mode of hexagonal array according to each described method in the claim 11,12 or 13.
CNA2005800412443A 2004-12-02 2005-12-01 Insulated gate field effect transistors Pending CN101288178A (en)

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GB0426412.3 2004-12-02
GBGB0426412.3A GB0426412D0 (en) 2004-12-02 2004-12-02 Insulated gate field effect transistors

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JP2019161103A (en) 2018-03-15 2019-09-19 株式会社東芝 Semiconductor device
US11728422B2 (en) 2019-11-14 2023-08-15 Stmicroelectronics S.R.L. Power MOSFET device having improved safe-operating area and on resistance, manufacturing process thereof and operating method thereof
IT202000015076A1 (en) 2020-06-23 2021-12-23 St Microelectronics Srl ELECTRONIC DEVICE IN 4H-SIC WITH IMPROVED SHORT-CIRCUIT PERFORMANCE, AND RELATED MANUFACTURING METHOD

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CN105895684B (en) * 2015-10-16 2018-12-28 苏州能讯高能半导体有限公司 A kind of semiconductor devices and its manufacturing method

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