CN105895684B - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
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- CN105895684B CN105895684B CN201510672757.XA CN201510672757A CN105895684B CN 105895684 B CN105895684 B CN 105895684B CN 201510672757 A CN201510672757 A CN 201510672757A CN 105895684 B CN105895684 B CN 105895684B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 129
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
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- 238000009826 distribution Methods 0.000 claims abstract description 23
- 239000011159 matrix material Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 4
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- 239000004744 fabric Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 11
- 230000017525 heat dissipation Effects 0.000 abstract description 11
- 230000007423 decrease Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 210000004027 cell Anatomy 0.000 description 60
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- 239000004020 conductor Substances 0.000 description 3
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
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- 230000005533 two-dimensional electron gas Effects 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention discloses a kind of semiconductor devices and its manufacturing method, the device includes substrate；Semiconductor layer on the substrate；Multiple device cells of dispersed distribution on the semiconductor layer, the multiple device cell are distributed on the semiconductor layer with the matrix form that M row N is arranged, and wherein M and N is all larger than equal to 1 and M and N are not equal to 1 simultaneously；Wherein, individual devices unit includes at least one basic device, and single basic device includes that source electrode, drain electrode and the grid between source electrode and drain electrode, at least one described basic device are located on active area.The present invention is able to solve the problem of being difficult to decrease semiconductor devices central temperature, improves channel heat dissipation effect, reduces channel temperature, improves breakdown voltage.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
GaN high electron mobility transistor (High Electron Mobility Transistor, HEMT) is very
It is suitable for making high temperature, high frequency, high pressure and powerful device, can be widely applied to frequency microwave field and power electronics neck
Domain is one of the research hotspot of current field of semiconductor devices.In order to improve the output power of device, people are generally by device ruler
Very little increase refers to the quantity of grid by increase grid width and multi-fork to improve output power, but device heating amount increases with it, and
And be unevenly distributed in device inside, general device center temperature highest, cause device performance and reliability to reduce.
In the prior art, there are mainly three types of the methods for solving device channel region heat dissipation problem.First, optimize domain knot
Structure increases the spacing of grizzly bar in multi-fork finger grid structure.But the disadvantages of this method is that its improvement is limited, can not be by device
The heat of central area distributes in time, and device center region is still the highest region of temperature；Second, more using thermal conductivity
High substrate material, for example silicon carbide substrates are ground off, using chemical vapor deposition (Chemical Vapor Deposition,
CVD), the methods of sputtering or bonding form diamond film or quasi cobalt carbon diaphragm at the epitaxial layer back side, but the disadvantages of this method is
Increase process complexity and cost；Third optimizes packaging technology, using better shell structure of heat dissipation effect etc., but should
Method disadvantage is to distribute the temperature of device inside by shell effectively, uniformly, in time, warm at device center
Still highest is spent, and the temperature of device inside is still unevenly distributed, therefore there is no solve root problem.
Summary of the invention
In view of this, the invention proposes a kind of semiconductor devices and its manufacturing method, to solve to be difficult to decrease semiconductor
The problem of device center temperature, improves channel heat dissipation effect, reduces channel temperature, improves breakdown voltage.
To achieve the above object, the present invention adopts the following technical scheme:
On the one hand, the embodiment of the invention provides a kind of semiconductor devices, comprising:
Substrate；
Semiconductor layer on the substrate；
Multiple device cells of dispersed distribution on the semiconductor layer, the square that the multiple device cell is arranged with M row N
Formation formula is distributed on the semiconductor layer, and wherein M and N is all larger than equal to 1 and M and N are not equal to 1 simultaneously；
Wherein, individual devices unit includes at least one basic device, and single basic device includes source electrode, drain electrode and position
Grid between source electrode and drain electrode, at least one described basic device are located on active area.
Further, metal electrical connection is interconnected by grid between the grid on the multiple device cell, it is the multiple
By drain electrode interconnection metal electrical connection between drain electrode on device cell, the grid interconnection metal and the drain electrode interconnect metal
On passive region.
Further, the grid interconnection metal and drain electrode interconnection metal intersection are without electrical connection.
Further, the bottom of the semiconductor devices is equipped with grounding electrode, and the source electrode in the multiple device cell is logical
The through-hole through the substrate and the semiconductor layer is crossed, is electrically connected with the grounding electrode.
Further, the grid is strip grate.
Further, the direction of the grid of the multiple device cell is different.
Further, the semiconductor devices further includes being located at grid body on passive region, the grid body be electrically connected to it is described extremely
The grid of a few basic device, and the grid body is located at the center or edge of individual devices unit.
On the other hand, the embodiment of the invention provides a kind of manufacturing methods of semiconductor devices, comprising:
Semiconductor layer is formed on the substrate；
It is formed on the semiconductor layer with multiple device cells of the M row N matrix form dispersed distribution arranged, wherein M and N
It is all larger than and is equal to 1 and M and N not simultaneously equal to 1, individual devices unit includes at least one basic device, single basic device packet
Source electrode, drain electrode and the grid between source electrode and drain electrode, at least one described basic device is included to be located on active area.
Further, further includes:
While forming grid, the grid of the grid for being electrically connected on the multiple device cell is formed on passive region
Interconnect metal；
While forming drain electrode, the drain electrode of the drain electrode for being electrically connected on the multiple device cell is formed on passive region
Interconnect metal.
Further, further includes:
Grounding electrode is formed in the bottom of the semiconductor devices；
It is opened up between the source electrode and the grounding electrode in the multiple device cell through the substrate and described half
The through-hole of conductor layer；
The source electrode is electrically connected with the grounding electrode by the through-hole.
The beneficial effects of the present invention are: semiconductor devices and its manufacturing method of the invention, are arranged more on the semiconductor layer
A device cell, and the matrix form dispersed distribution that multiple device cells are arranged with M row N, it is active can to disperse each device cell
Junction temperature at area avoids heat at active area from excessively concentrating caused device output power decline, effectively improves heat dissipation effect
Fruit；Meanwhile the average junction temperature of active area reduces, and reduces the resistance of semiconductor, improves equivalent current density, to improve
Output power.
Detailed description of the invention
Exemplary embodiments of the present invention will be described in detail referring to the drawings by general below, makes those skilled in the art
Become apparent from above-mentioned and other feature and advantage of the invention, in attached drawing:
Fig. 1 is the diagrammatic cross-section for the individual devices unit that the embodiment of the present invention one provides；
Fig. 2 is the top view for the individual devices unit that the embodiment of the present invention one provides；
Fig. 3 is the top view for the semiconductor devices that the embodiment of the present invention one provides；
Fig. 4 is the top view of semiconductor devices provided by Embodiment 2 of the present invention；
Fig. 5 is the diagrammatic cross-section of individual devices unit provided by Embodiment 2 of the present invention；
Fig. 6 is the top view for the individual devices unit that the embodiment of the present invention three provides；
Fig. 7 is the top view for the semiconductor devices that the embodiment of the present invention three provides；
Fig. 8 is the top view for the individual devices unit that the embodiment of the present invention four provides；
Fig. 9 is the top view for the semiconductor devices that the embodiment of the present invention four provides；
Figure 10 is the top view for the individual devices unit that the embodiment of the present invention five provides；
Figure 11 is the top view for the semiconductor devices that the embodiment of the present invention five provides；
Figure 12 is the top view for the individual devices unit that the embodiment of the present invention six provides；
Figure 13 is the top view for the semiconductor devices that the embodiment of the present invention six provides；
Figure 14 is the top view for the individual devices unit that the embodiment of the present invention seven provides；
Figure 15 is the top view for the semiconductor devices that the embodiment of the present invention seven provides；
Figure 16 is the top view for the individual devices unit that the embodiment of the present invention eight provides；
Figure 17 is the top view for the semiconductor devices that the embodiment of the present invention eight provides.
Specific embodiment
To further illustrate the technical scheme of the present invention below with reference to the accompanying drawings and specific embodiments.It is understood that
It is that specific embodiment described herein is used only for explaining the present invention rather than limiting the invention.It further needs exist for illustrating
, only the parts related to the present invention are shown for ease of description, in attached drawing rather than entire infrastructure.
Embodiment one
Fig. 3 is the top view for the semiconductor devices that the embodiment of the present invention one provides, it is found that should be partly in conjunction with Fig. 1, Fig. 2 and Fig. 3
Conductor device includes substrate 100；Semiconductor layer 101 on substrate 100；Dispersed distribution is more on semiconductor layer 101
A device cell, multiple device cells are distributed on semiconductor layer 101 with the matrix form that M row N is arranged, and wherein M and N are all larger than
It is not equal to 1 simultaneously in 1 and M and N；Wherein, individual devices unit includes at least one basic device, and single basic device includes source
Pole 102, drain electrode 104 and the grid 103 between source electrode 102 and drain electrode 104, at least one above-mentioned basic device, which is located at, to be had
In source region (region in dotted line frame in Fig. 3 at least one basic device).
In the present embodiment, semiconductor devices may include 9 device cells, and individual devices unit may include one basic
Device, 9 device cells can any dispersed distribution on semiconductor layer 101, excessively concentrating to avoid heat at active area causes
Device output power decline, improve heat dissipation effect.
Further, multiple device cells are distributed on the semiconductor layer with the matrix form that M row N is arranged, it illustratively, will
Multiple device cells are distributed on the semiconductor layer with the matrix form that 3 rows 3 arrange, so that the even heat of semiconductor device inside point
Cloth further solves the high problem of semiconductor devices central temperature, improves performance of semiconductor device and reliability.
In the present embodiment, substrate 100 can be gallium nitride, aluminum gallium nitride, indium gallium nitrogen, aluminium indium gallium nitrogen, indium phosphide, GaAs,
One of silicon carbide, diamond, sapphire, germanium, silicon or a variety of combinations or any other can grow group III-nitride
Material.
The material of semiconductor layer 101 may include the semiconductor material based on III-V compound, specifically, semiconductor
Layer 101 can include:
Nucleating layer on substrate 100, the nucleating layer influence the crystal quality of heterojunction material disposed thereon, surface
The parameters such as pattern and electrical properties play a part of to match semiconductor material layer in substrate material and heterojunction structure.
Buffer layer on nucleating layer, buffer layer can protect substrate 100 not invaded by some metal ions, and can
Bonding needs to grow the effect of other semiconductor material layers thereon, the material of buffer layer can be AlGaN, GaN or
The III-nitride materials such as AlGaInN.
Channel layer on buffer layer, the barrier layer on channel layer, the material of barrier layer can be AlGaN, ditch
Channel layer and barrier layer form heterojunction structure, be formed at heterogeneous interface 2DEG (Two-Dimensional Electron Gas,
Two-dimensional electron gas) channel, wherein channel layer provides the channel of 2DEG movement, and barrier layer plays barrier effect.
In addition, the source electrode 102 and drain electrode 104 that are located on barrier layer are contacted with 2DEG respectively, it is located at source electrode 102 and drain electrode
Grid 103 between 104 and on barrier layer can control and modulate electronics when applying bias appropriate on grid 103
The flowing of 2DEG channel between channel layer and potential barrier bed boundary.
The semiconductor devices that the embodiment of the present invention one provides, is arranged multiple device cells, and will be multiple on the semiconductor layer
Device cell dispersed distribution can disperse the junction temperature at each device cell active area, avoid at active area heat from excessively concentrating and lead
The device output power of cause declines, and effectively improves heat dissipation effect；Meanwhile the average junction temperature of active area reduces, and makes semiconductor
Resistance reduce, equivalent current density is improved, to improve output power；The matrix that multiple device cells are arranged with M row N
Formal distribution on the semiconductor layer, so that the even heat of semiconductor device inside is distributed, further solves semiconductor devices
The high problem of central temperature, improves performance of semiconductor device and reliability.
In the following, realizing that the manufacturing method of above-mentioned semiconductor device elaborates to the present invention.
The manufacturing method of the semiconductor devices is used to prepare above-mentioned semiconductor device, which includes:
Step 1: forming semiconductor layer 101 on substrate 100.
Specifically, nucleating layer, buffer layer, channel layer and barrier layer can be sequentially formed on substrate 100, wherein channel layer
Heterojunction structure is formed with barrier layer, is formed with 2DEG at heterojunction boundary.
Step 2: being formed on semiconductor layer 101 with multiple device cells of the M row N matrix form dispersed distribution arranged.
Wherein, M and N is all larger than equal to 1 and M and N are not equal to 1 simultaneously, and individual devices unit includes at least one basic device
Part, single basic device includes source electrode 102, drain 104 and the grid 103 between source electrode 102 and drain electrode 104, at least
One basic device is located on active area.
Illustratively, the reticle being pre-designed can be used in above-mentioned multiple device cells, the primary shape on semiconductor layer 101
At.For individual devices unit, gate dielectric layer is formed on the channel layer of active area, forms grid 103 on gate dielectric layer,
For silicon device, ion implanted formation source region and drain region at channel layer both ends pass through gallium nitride device at channel layer both ends
Annealing forms source region and drain region, finally, precipitating metal in source region and drain region, forms source electrode 102 and drain electrode 104.
The manufacturing method for the semiconductor devices that the embodiment of the present invention one provides, forms multiple device lists on the semiconductor layer
Member, and by multiple device cell dispersed distributions, the junction temperature at each device cell active area can be dispersed, avoid heat at active area
The decline of device output power caused by excessively concentrating, effectively improves heat dissipation effect；Meanwhile the average junction temperature drop of active area
It is low, reduce the resistance of semiconductor, improve equivalent current density, to improve output power.
Embodiment two
Fig. 4 is the top view of semiconductor devices provided by Embodiment 2 of the present invention, and the present embodiment is using above-described embodiment as base
Plinth optimizes, and the grid on multiple device cells is interconnected metal electrical connection by grid, by the leakage on multiple device cells
Pole passes through drain electrode interconnection metal electrical connection.As shown in Figure 4 and Figure 5, which may include: substrate 100；Positioned at substrate
Semiconductor layer 101 on 100；Multiple device cells of dispersed distribution on semiconductor layer 101, plurality of device cell with
The matrix form of M row N column is distributed on semiconductor layer 101, and wherein M and N is all larger than equal to 1 and M and N are not equal to 1 simultaneously；It is above-mentioned
Individual devices unit includes at least one basic device, and single basic device includes source electrode 102, drain electrode 104 and is located at source electrode
Grid 103 between 102 and drain electrode 104, at least one basic device are located at active area (in Fig. 4 at least one basic device
Dotted line frame in region) on.Metal 105 is interconnected by grid between grid 103 on above-mentioned multiple device cells to be electrically connected,
It is electrically connected between drain electrode 104 on multiple device cells by drain electrode interconnection metal 106, wherein grid interconnects metal 105 and leakage
Pole interconnection metal 106 is located on passive region.The program can increasing heat radiation area, further improve heat dissipation effect, improve output work
Rate；In addition, the grid 103 on multiple device cells is electrically connected with drain electrode 104 by interconnecting metal, it only need to be to any one
A grid 103 and any one 104 power supply of drain electrode, so that it may so that semiconductor devices works, it is easy to operate.
Further, referring to Fig. 5, in the present embodiment, the bottom of semiconductor devices is equipped with grounding electrode 107, multiple devices
Source electrode 102 in unit is electrically connected by the through-hole 108 through substrate 100 and semiconductor layer 101 with grounding electrode 107.The party
Case opens hole 108 between source electrode 102 and grounding electrode 107, is grounded source electrode 102, can reduce parasitic inductance when ground connection
Value, increases the gain of semiconductor devices.
In addition, the grid 103 in the present embodiment can be strip grate.
Further, the direction of the grid of above-mentioned multiple device cells is different.Specifically, the grid of different components unit
Direction can be inconsistent, for example, the grid of two device cells can be arranged in a mutually vertical manner.
In the following, realizing that the manufacturing method of above-mentioned semiconductor device elaborates to the present invention.
The manufacturing method of the semiconductor devices is used to prepare above-mentioned semiconductor device, which includes:
Step 1: forming semiconductor layer 101 on substrate 100.
Step 2: being formed on semiconductor layer 101 with multiple device cells of the M row N matrix form dispersed distribution arranged.
Wherein, individual devices unit includes at least one basic device, and single basic device includes source electrode 102, drain electrode 104
And the grid 103 between source electrode 102 and drain electrode 104, at least one basic device are located on active area.
Preferably, the multiple device cells being distributed with the matrix form that M row N is arranged are formed on semiconductor layer 101, wherein M
It is all larger than with N equal to 1 and M and N is not equal to 1 simultaneously.
Further, while forming grid 103, the grid for being electrically connected on multiple device cells are formed on passive region
The grid of pole 103 interconnects metal 105；While forming drain electrode 104, formed on passive region for being electrically connected multiple device cells
On drain electrode 104 drain electrode interconnect metal 106.Wherein, the cabling distribution of grid interconnection metal 105 and drain electrode interconnection metal 106
With no restriction, illustratively, as shown in figure 4, grid interconnection metal 105 and drain electrode interconnection metal 106 can be in an orthogonal manner
Intersection, and grid interconnection metal 105 and drain electrode interconnect the intersection of metal 106 without electrical connection, for this purpose, grid interconnects metal 105
It can be separated with insulating layer (not marked in figure) between drain electrode interconnection metal 106.
Step 3: forming grounding electrode 107 in the bottom of semiconductor devices.
Step 4: being opened up between the source electrode 102 in multiple device cells and grounding electrode 107 through substrate 100 and half
The through-hole 108 of conductor layer 101.
Step 5: source electrode 102 is electrically connected with grounding electrode 107 by through-hole 108.
In the present embodiment, it no longer repeats the part being the same as example 1.
Semiconductor devices provided by Embodiment 2 of the present invention and its manufacturing method form grid on passive region and interconnect metal
Metal, the grid being electrically connected on multiple device cells and drain electrode are interconnected with drain electrode, increases heat dissipation area, is further improved
Heat dissipation effect, improves output power；Source electrode is electrically connected with grounding electrode by through-hole, reduces parasitism electricity when ground connection
Inductance value increases the gain of semiconductor devices.
Embodiment three
Fig. 6 is the top view for the individual devices unit that the embodiment of the present invention three provides, and Fig. 7 is that the embodiment of the present invention three provides
Semiconductor devices top view, what is different from the first embodiment is that the structure of individual devices unit refers in the present embodiment for multi-fork
Gate structure, the semiconductor devices further include being located at grid body on passive region, which is electrically connected to two adjacent basic devices
Grid, and grid body is located at the edge of individual devices unit.As shown in fig. 7, the semiconductor devices includes that substrate (is not marked in figure
Out)；Semiconductor layer 201 on substrate；Multiple device cells of dispersed distribution on semiconductor layer 201；Wherein, individually
Device cell includes at least one basic device, and single basic device includes symmetrical a pair of of the drain electrode 204, one of ecto-entad
To a source electrode 202 of grid 203 and centre, at least one above-mentioned basic device is located at active area (at least one base in Fig. 7
The region in dotted line frame on this device) on；On passive region, the grid of the grid 203 for being electrically connected multiple device cells
Pole interconnects metal 205, and the first drain electrode interconnection metal 206 of the drain electrode 204 for being electrically connected multiple device cells；Positioned at passive
A pair of of grid body 207 and a pair of of leakage body 208 in area；Positioned at individual devices unit center, for being electrically connected individual devices unit
Second drain electrode interconnection metal 209 of the drain electrode 204 of at least one basic device.
Wherein, a pair of of grid 203 is connected by grid body 207, and a pair of drain electrode 204 is connected by leakage body 208, individual devices list
Grid body 207, leakage body 208, grid 203, source electrode 202 and drain electrode 204 in member, centered on the central point of individual devices unit,
Form central symmetry pattern.
In the present embodiment, 4 device cells are distributed on the semiconductor layer with the matrix form that 2 rows 2 arrange, individual devices unit
Including 4 basic devices, the quantity of device is increased on same chip area, substantially increases the output power of device；It is single
Active area quantity on a device cell increases, and active area is distributed in symmetricaerofoil dispersion, makes the internal heat of individual devices unit
Be evenly distributed, and then the internal heat of entire semiconductor devices made to be evenly distributed, further increase semiconductor devices performance and
Reliability.
Example IV
Fig. 8 is the top view for the individual devices unit that the embodiment of the present invention four provides, and Fig. 9 is that the embodiment of the present invention four provides
Semiconductor devices top view, it is unlike the embodiments above, in the present embodiment the grid of individual devices unit be star
Divergent shape structure, the semiconductor devices further include being located at grid body on passive region, which is electrically connected at least one basic device
Grid, and grid body is located at the center of individual devices unit.As shown in figure 9, the semiconductor devices includes that substrate (is not marked in figure
Out)；Semiconductor layer 301 on substrate；Multiple device cells of dispersed distribution on semiconductor layer 301；Wherein, individually
Device cell includes at least one basic device, and single basic device includes source electrode 302, drain electrode 304 and is located at 302 and of source electrode
Grid 303 between drain electrode 304, at least one above-mentioned basic device are located at active area (in Fig. 9 at least one basic device
Region in dotted line frame) on；On passive region, metal is interconnected for being electrically connected the grid of grid 303 of multiple device cells
305, and the drain electrode interconnection metal 306 of the drain electrode 304 for being electrically connected multiple device cells；A pair of of source body on passive region
309 and a pair of of leakage body 208, and be located at individual devices unit center, it is basic for being electrically connected on individual devices unit at least one
The round grid body 307 of the grid 303 of device.
Wherein, each source body 309 connects 2 source electrodes 302, each 2 304,4 grids 303 of drain electrode of connection of leakage body 308 from
The diverging growth outward of grid body 307, is respectively formed between the source electrode 302 of each basic device and drain electrode 304.In individual devices unit
Grid body 307, leakage body 308, grid 303, source electrode 302 and drain electrode 304, centered on the central point of individual devices unit, formed
Central symmetry pattern.
In the present embodiment, 4 device cells are distributed on the semiconductor layer with the matrix form that 2 rows 2 arrange, individual devices unit
Including 4 basic devices, the quantity of device is increased on same chip area, substantially increases the output power of device；Electricity
The metallic area for being connected to the source body of source electrode significantly increases, and helps to increase clear size of opening, posting when further reduced ground connection
Raw inductance value, increases the gain of semiconductor devices.
Embodiment five
Figure 10 is the top view for the individual devices unit that the embodiment of the present invention five provides, and Figure 11 is that the embodiment of the present invention five mentions
The top view of the semiconductor devices of confession.As shown in figure 11, the present embodiment eliminates multiple devices in Fig. 9 based on example IV
Source body 309 in part unit, saves metal material, reduces the gross area of semiconductor devices.
Embodiment six
Figure 12 is the top view for the individual devices unit that the embodiment of the present invention six provides, and Figure 13 is that the embodiment of the present invention six mentions
The top view of the semiconductor devices of confession, unlike embodiment three, the structure of individual devices unit is bending in the present embodiment
Multi-fork finger grid structure, which further includes being located at grid body on passive region, which is electrically connected at least one base
The grid of this device, and grid body is located at the center of individual devices unit.As shown in figure 13, which includes substrate (figure
In do not mark)；Semiconductor layer 401 on substrate；Multiple device cells of dispersed distribution on semiconductor layer 401；Its
In, individual devices unit includes at least one basic device, and single basic device includes symmetrical a pair of of the leakage of ecto-entad
One source electrode 402 of pole 404, a pair of of first grid 403 and centre, at least one above-mentioned basic device are located at active area (figure
The region in dotted line frame in 13 at least one basic device) on；On passive region, for being electrically connected multiple device cells
The grid of grid 403 interconnect metal 405, and the drain electrode of drain electrode 404 for being electrically connected multiple device cells interconnects metal
406；A pair of of source body 409 and a pair of of leakage body 408 on passive region, and it is located at individual devices unit center, for being electrically connected
The grid body 407 of the grid 403 of at least one basic device on individual devices unit.
Wherein, a pair of of first grid 403 passes through on passive region, and the second grid 410 vertical with first grid 403 is connect,
A pair of drain electrode 404 is connected by leakage body 408, grid body 407, leakage body 408, grid 403,402 and of source electrode in individual devices unit
Drain electrode 404 forms central symmetry pattern centered on the central point of individual devices unit.
In the present embodiment, 4 device cells are distributed on the semiconductor layer with the matrix form that 2 rows 2 arrange, individual devices unit
Including 4 basic devices, the quantity of device is increased on same chip area, substantially increases the output power of device；Electricity
The metallic area for being connected to the source body of source electrode significantly increases, and helps to increase clear size of opening, posting when further reduced ground connection
Raw inductance value, increases the gain of semiconductor devices；The grid width of single basic device is equal to a pair of of first grid and second grid
The sum of length, device grid width is increased in limited areal, improves device output power.
Embodiment seven
Figure 14 is the top view for the individual devices unit that the embodiment of the present invention seven provides, and Figure 15 is that the embodiment of the present invention seven mentions
The top view of the semiconductor devices of confession.As shown in figure 15, the present embodiment eliminates multiple devices in Figure 13 based on embodiment six
Source body 409 in part unit, saves metal material, reduces the gross area of semiconductor devices.
Embodiment eight
Figure 16 is the top view for the individual devices unit that the embodiment of the present invention eight provides, and Figure 17 is that the embodiment of the present invention eight mentions
The top view of the semiconductor devices of confession, unlike the embodiments above, the source electrode of individual devices unit is common in the present embodiment
Form T-type distribution.As shown in figure 17, which includes substrate (not marking in figure)；Semiconductor layer on substrate
501；Multiple device cells of dispersed distribution on semiconductor layer 501；Wherein, individual devices unit includes that at least one is basic
Device, single basic device includes source electrode 502, drain 504 and the grid 503 between source electrode 502 and drain electrode 504, on
At least one basic device is stated to be located on active area (region in dotted line frame in Figure 17 at least one basic device)；It is located at
On passive region, metal 505 is interconnected for being electrically connected the first grid of grid 503 of multiple device cells, and more for being electrically connected
First drain electrode interconnection metal 506 of the drain electrode 504 of a device cell.
Wherein, T-type distribution is collectively formed in the source electrode 502 of individual devices unit, and concentrates and be distributed in individual devices unit
Middle part, and the direction of source electrode is consistent；Grid 503 in individual devices unit interconnects metal by the second grid on passive region
507 are electrically connected, and the drain electrode 504 in individual devices unit passes through the second drain electrode interconnection metal 508 on passive region and is electrically connected.
In the present embodiment, 4 device cells are distributed on the semiconductor layer with the matrix form that 2 rows 2 arrange, individual devices unit
Including 4 basic devices, the quantity of device is increased on same chip area, substantially increases the output power of device.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of semiconductor devices characterized by comprising
Substrate；
Semiconductor layer on the substrate；
Multiple device cells of dispersed distribution on the semiconductor layer, the rectangular that the multiple device cell is arranged with M row N
Formula is distributed on the semiconductor layer, and wherein M and N is all larger than equal to 1 and M and N are not equal to 1 simultaneously；
Wherein, individual devices unit includes at least one basic device, and the single basic device includes that ecto-entad symmetrically divides
A pair of cloth drains, a pair of of grid and an intermediate source electrode, at least one described basic device are located on active area；
Alternatively, the single basic device includes that source electrode, drain electrode and the grid between source electrode and drain electrode, the grid are
Star divergent shape structure, at least one described basic device are located on active area；
Alternatively, the single basic device includes symmetrical a pair of of the drain electrode of ecto-entad, a pair of of first grid and centre
A source electrode, at least one described basic device is located on active area；The single basic device further includes being located at passive region
On, and second grid that is vertical with the first grid and connecting the first grid；
Alternatively, single basic device includes source electrode, drain electrode and the grid between the source electrode and the drain electrode, it is described extremely
A few basic device is located on active area；And T-type distribution is collectively formed in the source electrode of the individual devices unit, and concentrates
It is distributed in the middle part of the individual devices unit, and the direction of the source electrode is consistent.
2. semiconductor devices according to claim 1, which is characterized in that lead between the grid on the multiple device cell
Grid interconnection metal electrical connection is crossed, passes through drain electrode interconnection metal electrical connection between the drain electrode on the multiple device cell, it is described
Grid interconnection metal and drain electrode interconnection metal are located on passive region.
3. semiconductor devices according to claim 2, which is characterized in that the grid interconnection metal and drain electrode interconnection
Metal intersection is without electrical connection.
4. semiconductor devices according to claim 2, which is characterized in that the bottom of the semiconductor devices is equipped with ground connection electricity
Pole, source electrode in the multiple device cell are electric with the ground connection by running through the through-hole of the substrate and the semiconductor layer
Pole electrical connection.
5. semiconductor devices according to claim 2, which is characterized in that the grid is strip grate.
6. semiconductor devices according to claim 2, which is characterized in that the direction of the grid of the multiple device cell is not
Together.
7. semiconductor devices according to claim 2, which is characterized in that the semiconductor devices further includes being located at passive region
Upper grid body, the grid body is electrically connected to the grid of at least one basic device, and the grid body is located at individual devices unit
Center or edge.
8. a kind of manufacturing method of semiconductor devices characterized by comprising
Semiconductor layer is formed on the substrate；
It is formed on the semiconductor layer with multiple device cells of the M row N matrix form dispersed distribution arranged, wherein M and N are big
It is not equal to 1 simultaneously in being equal to 1 and M and N, individual devices unit includes at least one basic device, the single basic device packet
Include a source electrode of symmetrical a pair of of the drain electrode of ecto-entad, a pair of of grid and centre, at least one described basic device
On active area；
Alternatively, the single basic device includes that source electrode, drain electrode and the grid between source electrode and drain electrode, the grid are
Star divergent shape structure, at least one described basic device are located on active area；
Alternatively, the single basic device includes symmetrical a pair of of the drain electrode of ecto-entad, a pair of of first grid and centre
A source electrode, at least one described basic device is located on active area；The single basic device further includes being located at passive region
On, and second grid that is vertical with the first grid and connecting the first grid；
Alternatively, single basic device includes source electrode, drain electrode and the grid between the source electrode and the drain electrode, it is described extremely
A few basic device is located on active area；And T-type distribution is collectively formed in the source electrode of the individual devices unit, and concentrates
It is distributed in the middle part of the individual devices unit, and the direction of the source electrode is consistent.
9. according to the method described in claim 8, it is characterized by further comprising:
While forming grid, the grid interconnection of the grid for being electrically connected on the multiple device cell is formed on passive region
Metal；
While forming drain electrode, the drain electrode interconnection of the drain electrode for being electrically connected on the multiple device cell is formed on passive region
Metal.
10. according to the method described in claim 9, it is characterized by further comprising:
Grounding electrode is formed in the bottom of the semiconductor devices；
It opens up between the source electrode and the grounding electrode in the multiple device cell through the substrate and the semiconductor
The through-hole of layer；
The source electrode is electrically connected with the grounding electrode by the through-hole.
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|---|---|---|---|---|
| US6271562B1 (en) * | 1998-02-27 | 2001-08-07 | Infineon Technologies Ag | Semiconductor component which can be controlled by a field effect |
| CN101288178A (en) * | 2004-12-02 | 2008-10-15 | Nxp股份有限公司 | Insulated gate field effect transistors |
| CN104617092A (en) * | 2014-11-06 | 2015-05-13 | 苏州捷芯威半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN104637989A (en) * | 2013-11-06 | 2015-05-20 | 恩智浦有限公司 | Semiconductor device |
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2015
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271562B1 (en) * | 1998-02-27 | 2001-08-07 | Infineon Technologies Ag | Semiconductor component which can be controlled by a field effect |
| CN101288178A (en) * | 2004-12-02 | 2008-10-15 | Nxp股份有限公司 | Insulated gate field effect transistors |
| CN104637989A (en) * | 2013-11-06 | 2015-05-20 | 恩智浦有限公司 | Semiconductor device |
| CN104617092A (en) * | 2014-11-06 | 2015-05-13 | 苏州捷芯威半导体有限公司 | Semiconductor device and manufacturing method thereof |
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