CN105895684A - Semiconductor device and manufacture method therefor - Google Patents

Semiconductor device and manufacture method therefor Download PDF

Info

Publication number
CN105895684A
CN105895684A CN201510672757.XA CN201510672757A CN105895684A CN 105895684 A CN105895684 A CN 105895684A CN 201510672757 A CN201510672757 A CN 201510672757A CN 105895684 A CN105895684 A CN 105895684A
Authority
CN
China
Prior art keywords
grid
drain electrode
semiconductor device
semiconductor layer
source electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510672757.XA
Other languages
Chinese (zh)
Other versions
CN105895684B (en
Inventor
裴风丽
亢国纯
裴轶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dynax Semiconductor Inc
Original Assignee
Dynax Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dynax Semiconductor Inc filed Critical Dynax Semiconductor Inc
Priority to CN201510672757.XA priority Critical patent/CN105895684B/en
Publication of CN105895684A publication Critical patent/CN105895684A/en
Application granted granted Critical
Publication of CN105895684B publication Critical patent/CN105895684B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66431Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention discloses semiconductor device and a manufacture method therefor. The device comprises a substrate, a semiconductor layer arranged on the substrate and a plurality of device units arranged on the semiconductor layer in a scattered manner, wherein the device units are arranged on the semiconductor layer in such a way that an M row and N line matrix is formed; each of M and N is greater than and equal to one, and M and N are not equal to one at the same time; each device unit comprises at least a basic device which comprises a source electrode, a drain electrode and a grid electrode positioned between the source electrode and the drain electrode, and the at least a basic device is positioned on an active region. Via use of the semiconductor device and the manufacture method therefor, a problem that center temperature of the semiconductor device is difficult to lower can be solved; channel heat radiation effects can be improved, channel temperature is lowered, and breakdown voltage is improved.

Description

A kind of semiconductor device and manufacture method thereof
Technical field
The present invention relates to technical field of semiconductors, be specifically related to a kind of semiconductor device and manufacture method thereof.
Background technology
GaN high electron mobility transistor (High Electron Mobility Transistor, HEMT) It is very suitable for making high temperature, high frequency, high pressure and powerful device, can be widely applied to frequency microwave neck Territory and field of power electronics, be one of the study hotspot of current field of semiconductor devices.In order to improve device Output, device size is generally increased by people, i.e. the quantity by increasing grid width and how interdigital grid carries High-output power, but device heating amount increases therewith, and at device inside skewness, general device Part central temperature is the highest, causes device performance and reliability to reduce.
In prior art, the method solving device channel region heat dissipation problem mainly has three kinds.First, optimize Domain structure, increases the spacing of grizzly bar in multi-fork finger grid structure.But the shortcoming of the method is that it improves effect The most limited, it is impossible to be distributed in time by the heat in device center region, device center region is still that temperature The highest region;Second, use the higher backing material of thermal conductivity, such as silicon carbide substrates is ground off, adopt With chemical gaseous phase deposition (Chemical Vapor Deposition, CVD), sputter or the method such as bonding outside Prolong layer back side and form diamond film or quasi cobalt carbon diaphragm, but the shortcoming of the method is to add process complexity And cost;3rd, optimize packaging technology, the use more preferable shell structure of radiating effect etc., but the method Shortcoming be can not by the temperature of device inside effectively, uniformly, in time by shell distribute, device Center temperature is the highest, and the temperature of device inside still skewness, and it is basic therefore not solve Problem.
Summary of the invention
In view of this, the present invention proposes a kind of semiconductor device and manufacture method thereof, to solve to be difficult to reduce The problem of semiconductor device central temperature, improves raceway groove radiating effect, reduces channel temperature, improves breakdown potential Pressure.
For achieving the above object, the present invention adopts the following technical scheme that
On the one hand, embodiments provide a kind of semiconductor device, including:
Substrate;
It is positioned at the semiconductor layer on described substrate;
Being positioned at multiple device cells of dispersed and distributed on described semiconductor layer, the plurality of device cell is with M row N The matrix form of row is distributed on described semiconductor layer, and wherein M with N is all higher than equal to 1 and M with N is different Time equal to 1;
Wherein, individual devices unit includes that at least one basic device, single basic device include source electrode, leakage Pole and the grid between source electrode and drain electrode, at least one basic device described is positioned on active area.
Further, electrically connected by grid interconnection metal between the grid on the plurality of device cell, institute Stating between the drain electrode on multiple device cell by drain electrode interconnection metal electrically connect, described grid interconnection metal and Described drain electrode interconnection metal is positioned on passive region.
Further, described grid interconnection metal and described drain electrode interconnection metal intersection are without electrical connection.
Further, the bottom of described semiconductor device is provided with ground electrode, in the plurality of device cell Source electrode, by running through described substrate and the through hole of described semiconductor layer, electrically connects with described ground electrode.
Further, described grid is strip grate.
Further, the direction of the grid of the plurality of device cell is different.
Further, described semiconductor device also includes being positioned at grid body on passive region, and described grid body is electrically connected to The grid of at least one basic device described, and described grid body is positioned at center or the edge of individual devices unit.
On the other hand, embodiments provide the manufacture method of a kind of semiconductor device, including:
Substrate is formed semiconductor layer;
Described semiconductor layer is formed multiple device cells of the matrix form dispersed and distributed arranged with M row N, Wherein M and N is all higher than equal to 1 and M and N is not simultaneously equal to 1, and individual devices unit includes at least one base This device, single basic device includes source electrode, drain electrode and the grid between source electrode and drain electrode, described At least one basic device is positioned on active area.
Further, also include:
While forming grid, passive region is formed for electrically connecting the grid on the plurality of device cell Grid interconnection metal;
While forming drain electrode, passive region is formed for electrically connecting the drain electrode on the plurality of device cell Drain electrode interconnection metal.
Further, also include:
Ground electrode is formed in the bottom of described semiconductor device;
Offer between source electrode and described ground electrode in the plurality of device cell and run through described substrate and institute State the through hole of semiconductor layer;
Described source electrode is electrically connected by described through hole with described ground electrode.
The invention has the beneficial effects as follows: the semiconductor device of the present invention and manufacture method thereof, on the semiconductor layer Multiple device cell, and the matrix form dispersed and distributed arranged with M row N by multiple device cells are set, permissible Disperse the junction temperature at each device cell active area, it is to avoid at active area, heat excessively concentrates the device output caused Power drop, effectively improves radiating effect;Meanwhile, the average junction temperature of active area reduces, and makes quasiconductor Resistance reduce, improve equivalent current density, thus improve output.
Accompanying drawing explanation
The exemplary embodiment of the present invention will be described in detail by referring to accompanying drawing below, make the common skill of this area Art personnel become apparent from the above-mentioned and other feature and advantage of the present invention, in accompanying drawing:
Fig. 1 is the generalized section of the individual devices unit that the embodiment of the present invention one provides;
Fig. 2 is the top view of the individual devices unit that the embodiment of the present invention one provides;
Fig. 3 is the top view of the semiconductor device that the embodiment of the present invention one provides;
Fig. 4 is the top view of the semiconductor device that the embodiment of the present invention two provides;
Fig. 5 is the generalized section of the individual devices unit that the embodiment of the present invention two provides;
Fig. 6 is the top view of the individual devices unit that the embodiment of the present invention three provides;
Fig. 7 is the top view of the semiconductor device that the embodiment of the present invention three provides;
Fig. 8 is the top view of the individual devices unit that the embodiment of the present invention four provides;
Fig. 9 is the top view of the semiconductor device that the embodiment of the present invention four provides;
Figure 10 is the top view of the individual devices unit that the embodiment of the present invention five provides;
Figure 11 is the top view of the semiconductor device that the embodiment of the present invention five provides;
Figure 12 is the top view of the individual devices unit that the embodiment of the present invention six provides;
Figure 13 is the top view of the semiconductor device that the embodiment of the present invention six provides;
Figure 14 is the top view of the individual devices unit that the embodiment of the present invention seven provides;
Figure 15 is the top view of the semiconductor device that the embodiment of the present invention seven provides;
Figure 16 is the top view of the individual devices unit that the embodiment of the present invention eight provides;
Figure 17 is the top view of the semiconductor device that the embodiment of the present invention eight provides.
Detailed description of the invention
Further illustrate technical scheme below in conjunction with the accompanying drawings and by detailed description of the invention.Permissible Being understood by, specific embodiment described herein is used only for explaining the present invention, rather than the limit to the present invention Fixed.It also should be noted that, for the ease of describing, accompanying drawing illustrate only portion related to the present invention Divide rather than entire infrastructure.
Embodiment one
Fig. 3 is the top view of the semiconductor device that the embodiment of the present invention one provides, in conjunction with Fig. 1, Fig. 2 and Fig. 3 Understanding, this semiconductor device includes substrate 100;The semiconductor layer 101 being positioned on substrate 100;It is positioned at and partly leads Multiple device cells of dispersed and distributed on body layer 101, the matrix form that multiple device cells arrange with M row N divides Cloth is on semiconductor layer 101, and wherein M and N is all higher than equal to 1 and M and N is not simultaneously equal to 1;Wherein, Individual devices unit include at least one basic device, single basic device include source electrode 102, drain electrode 104 with And the grid 103 between source electrode 102 and drain electrode 104, at least one basic device above-mentioned is positioned at active area On (region in the dotted line frame at least one basic device in Fig. 3).
In the present embodiment, semiconductor device can include 9 device cells, and individual devices unit can include One basic device, 9 device cells can arbitrarily dispersed and distributed on semiconductor layer 101, to avoid active area Place's heat excessively concentrates the device output power caused to decline, and improves radiating effect.
Further, the matrix form that multiple device cells arrange with M row N is distributed on the semiconductor layer, shows Example, the matrix form that multiple device cells arrange with 3 row 3 is distributed on the semiconductor layer so that partly lead The even heat distribution of body device inside, solves the problem that semiconductor device central temperature is high further, carries High performance of semiconductor device and reliability.
In the present embodiment, substrate 100 can be gallium nitride, aluminum gallium nitride, indium gallium nitrogen, aluminum indium gallium nitrogen, phosphatization The combination of one or more in indium, GaAs, carborundum, diamond, sapphire, germanium, silicon, or appoint What he can grow the material of group III-nitride.
The material of semiconductor layer 101 can include semi-conducting material based on III-V, concrete, Semiconductor layer 101 comprises the steps that
Being positioned at the nucleating layer on substrate 100, the impact of this nucleating layer is positioned at the crystal matter of heterojunction material thereon The parameters such as amount, surface topography and electrical properties, play quasiconductor material in coupling backing material and heterojunction structure The effect of the bed of material.
The cushion being positioned on nucleating layer, cushion can protect substrate 100 not invaded by some metal ions, Can bond again the effect needing to be grown on other semiconductor material layers thereon, the material of cushion can be The III-nitride material such as AlGaN, GaN or AlGaInN.
The channel layer being positioned on cushion, the barrier layer being positioned on channel layer, the material of barrier layer can be AlGaN, channel layer and barrier layer form heterojunction structure, are formed with 2DEG at heterogeneous interface (Two-Dimensional Electron Gas, two-dimensional electron gas) raceway groove, wherein, channel layer provides The raceway groove of 2DEG motion, barrier layer plays potential barrier effect.
It addition, the source electrode 102 being positioned on barrier layer contacts with 2DEG respectively with drain electrode 104, it is positioned at source electrode 102 And the grid 103 draining between 104 and being positioned on barrier layer, when applying suitable bias on grid 103, Can control and modulate the flowing of electronics 2DEG raceway groove between channel layer and barrier layer interface.
The semiconductor device that the embodiment of the present invention one provides, arranges multiple device cell on the semiconductor layer, and By multiple device cell dispersed and distributed, the junction temperature at each device cell active area can be disperseed, it is to avoid active area Place's heat excessively concentrates the device output power caused to decline, and effectively improves radiating effect;Meanwhile, have The average junction temperature of source region reduces, and makes the resistance of quasiconductor reduce, improves equivalent current density, thus improve Output;The matrix form that multiple device cells arrange with M row N is distributed on the semiconductor layer so that The even heat distribution of semiconductor device inside, solves the problem that semiconductor device central temperature is high further, Improve performance of semiconductor device and reliability.
Below, the manufacture method that the present invention realizes above-mentioned semiconductor device elaborates.
The manufacture method of this semiconductor device is used for preparing above-mentioned semiconductor device, and this manufacture method includes:
Step one, on the substrate 100 formation semiconductor layer 101.
Concrete, nucleating layer, cushion, channel layer and barrier layer can be sequentially formed on the substrate 100, its In, channel layer and barrier layer form heterojunction structure, are formed with 2DEG at heterojunction boundary.
Step 2, formed on semiconductor layer 101 with multiple devices of matrix form dispersed and distributed of M row N row Part unit.
Wherein, M and N is all higher than equal to 1 and M and N is not simultaneously equal to 1, and individual devices unit includes at least One basic device, single basic device includes source electrode 102, drain electrode 104 and is positioned at source electrode 102 and drain electrode Grid 103 between 104, at least one basic device is positioned on active area.
Exemplary, above-mentioned multiple device cells can use the reticle being pre-designed, at semiconductor layer 101 Last formation.For individual devices unit, on the channel layer of active area, form gate dielectric layer, at grid Grid 103 is formed on dielectric layer, for silicon device, in channel layer two ends ion implanted formation source region and drain region, For gallium nitride device, in channel layer two ends annealed formation source region and drain region, finally, in source region and drain region Upper precipitation metal, forms source electrode 102 and drain electrode 104.
The manufacture method of the semiconductor device that the embodiment of the present invention one provides, forms multiple device on the semiconductor layer Part unit, and by multiple device cell dispersed and distributed, the junction temperature at each device cell active area can be disperseed, Avoid heat at active area excessively to concentrate the device output power caused to decline, effectively improve radiating effect; Meanwhile, the average junction temperature of active area reduces, and makes the resistance of quasiconductor reduce, improves equivalent current density, Thus improve output.
Embodiment two
Fig. 4 is the top view of the semiconductor device that the embodiment of the present invention two provides, and the present embodiment is with above-mentioned enforcement It is optimized based on example, the grid on multiple device cells is electrically connected by grid interconnection metal, will be many Drain electrode on individual device cell is electrically connected by drain electrode interconnection metal.As shown in Figure 4 and Figure 5, this quasiconductor Device may include that substrate 100;The semiconductor layer 101 being positioned on substrate 100;It is positioned at semiconductor layer 101 Multiple device cells of upper dispersed and distributed, the matrix form that plurality of device cell arranges with M row N is distributed in On semiconductor layer 101, wherein M and N is all higher than equal to 1 and M and N is not simultaneously equal to 1;Above-mentioned single device Part unit includes that at least one basic device, single basic device include source electrode 102, drain electrode 104 and be positioned at Grid 103 between source electrode 102 and drain electrode 104, at least one basic device is positioned at active area (in Fig. 4 extremely The region in dotted line frame on a few basic device) on.Grid 103 on above-mentioned multiple device cell it Between electrically connected, between the drain electrode 104 on multiple device cells by drain electrode mutually by grid interconnection metal 105 Connection metal 106 electrically connects, and wherein, grid interconnection metal 105 and drain electrode interconnection metal 106 are positioned at passive region On.The program can increasing heat radiation area, improve radiating effect further, improve output;It addition, will Grid 103 and drain electrode 104 on multiple device cells are electrically connected by interconnection metal, only need to be to arbitrarily One grid 103 and any one drain electrode 104 power supply, so that it may so that semiconductor device work, simple to operate.
Further, seeing Fig. 5, in the present embodiment, the bottom of semiconductor device is provided with ground electrode 107, Source electrode 102 in multiple device cells, by running through the through hole 108 of substrate 100 and semiconductor layer 101, and connects Ground electrode 107 electrically connects.The program opens hole 108 between source electrode 102 and ground electrode 107, makes source electrode 102 ground connection, can reduce stray inductance value during ground connection, increase the gain of semiconductor device.
It addition, the grid 103 in the present embodiment can be strip grate.
Further, the direction of the grid of above-mentioned multiple device cell is different.Concrete, different components unit The direction of grid can be inconsistent, such as, the grid of two device cells can be arranged in a mutually vertical manner.
Below, the manufacture method that the present invention realizes above-mentioned semiconductor device elaborates.
The manufacture method of this semiconductor device is used for preparing above-mentioned semiconductor device, and this manufacture method includes:
Step one, on the substrate 100 formation semiconductor layer 101.
Step 2, formed on semiconductor layer 101 with multiple devices of matrix form dispersed and distributed of M row N row Part unit.
Wherein, individual devices unit include at least one basic device, single basic device include source electrode 102, Drain electrode 104 and the grid 103 between source electrode 102 and drain electrode 104, at least one basic device is positioned at On active area.
Preferably, semiconductor layer 101 is formed multiple device lists of the matrix form distribution with M row N row Unit, wherein M and N is all higher than equal to 1 and M and N is not simultaneously equal to 1.
Further, while forming grid 103, passive region is formed and is used for electrically connecting multiple device list The grid interconnection metal 105 of the grid 103 in unit;While forming drain electrode 104, passive region is formed and uses Drain electrode interconnection metal 106 in the drain electrode 104 electrically connected on multiple device cells.Wherein, grid interconnection metal 105 are not restricted with the cabling distribution interconnecting metal 106 that drains, and exemplary, as shown in Figure 4, grid is mutual Connection metal 105 and drain electrode interconnection metal 106 can intersect in an orthogonal manner, and grid interconnection metal 105 With the intersection that drain electrode interconnects metal 106 without electrical connection, to this end, grid interconnection metal 105 and drain electrode interconnect Can separate with insulating barrier (figure does not marks) between metal 106.
Step 3, the bottom of semiconductor device formed ground electrode 107.
Offer between step 4, source electrode 102 and ground electrode 107 in multiple device cells and run through substrate 100 and the through hole 108 of semiconductor layer 101.
Step 5, source electrode 102 and ground electrode 107 is electrically connected by through hole 108.
In the present embodiment, identical with embodiment one part no longer repeats.
The semiconductor device of the embodiment of the present invention two offer and manufacture method thereof, form grid mutual on passive region Connection metal and drain electrode interconnection metal, be electrically connected the grid on multiple device cell and drain electrode, increase scattered Hot side amasss, and further improves radiating effect, improves output;By through hole by source electrode and ground connection electricity Pole electrically connects, and reduces stray inductance value during ground connection, increases the gain of semiconductor device.
Embodiment three
The top view of the individual devices unit that Fig. 6 provides for the embodiment of the present invention three, Fig. 7 is that the present invention implements The top view of the semiconductor device that example three provides, unlike embodiment one, individual devices in the present embodiment The structure of unit is multi-fork finger grid structure, and this semiconductor device also includes being positioned at grid body on passive region, these grid Body is electrically connected to the grid of the basic device of adjacent two, and grid body is positioned at the edge of individual devices unit.As Shown in Fig. 7, this semiconductor device includes substrate (not marking in figure);The semiconductor layer 201 being positioned on substrate; It is positioned at multiple device cells of dispersed and distributed on semiconductor layer 201;Wherein, individual devices unit includes at least One basic device, single basic device includes symmetrical a pair drain electrode 204 of ecto-entad, a pair grid 203 and a source electrode 202 of centre, at least one basic device above-mentioned is positioned at active area (in Fig. 7 at least The region in dotted line frame on one basic device) on;It is positioned on passive region, is used for electrically connecting multiple device The grid interconnection metal 205 of the grid 203 of unit, and for electrically connecting the drain electrode 204 of multiple device cell First drain electrode interconnection metal 206;The a pair grid body 207 being positioned on passive region and a pair leakage body 208;It is positioned at list Individual device cell center, for electrically connecting the drain electrode 204 of at least one basic device on individual devices unit Second drain electrode interconnection metal 209.
Wherein, a pair grid 203 is connected by grid body 207, and a pair drain electrode 204 is connected by leakage body 208, Grid body 207, leakage body 208, grid 203, source electrode 202 and drain electrode 204 in individual devices unit, with list Centered by the central point of individual device cell, form centrosymmetry pattern.
In the present embodiment, the matrix form that 4 device cells arrange with 2 row 2 is distributed on the semiconductor layer, single Device cell includes 4 basic devices, equal chip area adds the quantity of device, is greatly improved The output of device;Active area quantity on individual devices unit increases, and active area symmetrically disperses Distribution, makes the internal heat of individual devices unit be evenly distributed, and then makes the inside heat of whole semiconductor device Amount is evenly distributed, and improves performance and the reliability of semiconductor device further.
Embodiment four
The top view of the individual devices unit that Fig. 8 provides for the embodiment of the present invention four, Fig. 9 is that the present invention implements The top view of the semiconductor device that example four provides, unlike the embodiments above, single device in the present embodiment The grid of part unit is star divergent shape structure, and this semiconductor device also includes being positioned at grid body on passive region, should Grid body is electrically connected to the grid of at least one basic device, and grid body is positioned at the center of individual devices unit.As Shown in Fig. 9, this semiconductor device includes substrate (not marking in figure);The semiconductor layer 301 being positioned on substrate; It is positioned at multiple device cells of dispersed and distributed on semiconductor layer 301;Wherein, individual devices unit includes at least One basic device, single basic device includes source electrode 302, drain electrode 304 and is positioned at source electrode 302 and drain electrode Grid 303 between 304, at least one basic device above-mentioned is positioned at active area, and (in Fig. 9, at least one is basic The region in dotted line frame on device) on;It is positioned on passive region, for electrically connecting the grid of multiple device cell The grid interconnection metal 305 of pole 303, and for electrically connecting the drain electrode interconnection of the drain electrode 304 of multiple device cell Metal 306;The a pair source body 309 being positioned on passive region and a pair leakage body 208, and it is positioned at individual devices unit Center, for electrically connecting the circular grid body 307 of the grid 303 of at least one basic device on individual devices unit.
Wherein, each source body 309 connects 2 source electrodes 302, and each leakage body 308 connects 2 drain electrodes 304, 4 grids 303 outwards dissipate growth from grid body 307, are respectively formed in source electrode 302 and the leakage of each basic device Between pole 304.Grid body 307, leakage body 308, grid 303, source electrode 302 and leakage in individual devices unit Pole 304, centered by the central point of individual devices unit, forms centrosymmetry pattern.
In the present embodiment, the matrix form that 4 device cells arrange with 2 row 2 is distributed on the semiconductor layer, single Device cell includes 4 basic devices, equal chip area adds the quantity of device, is greatly improved The output of device;The metallic area of the source body being electrically connected to source electrode significantly increases, and contributes to increasing and leads to Hole dimension, reduce further stray inductance value during ground connection, increases the gain of semiconductor device.
Embodiment five
The top view of the individual devices unit that Figure 10 provides for the embodiment of the present invention five, Figure 11 is that the present invention is real Execute the top view of the semiconductor device that example five provides.As shown in figure 11, the present embodiment based on embodiment four, Eliminate the source body 309 in multiple device cells in Fig. 9, save metal material, reduce semiconductor device The gross area.
Embodiment six
The top view of the individual devices unit that Figure 12 provides for the embodiment of the present invention six, Figure 13 is that the present invention is real Execute the top view of the semiconductor device that example six provides, unlike embodiment three, single device in the present embodiment The structure of part unit is the multi-fork finger grid structure of bending, and this semiconductor device also includes being positioned at grid on passive region Body, this grid body is electrically connected to the grid of at least one basic device, and grid body is positioned in individual devices unit The heart.As shown in figure 13, this semiconductor device includes substrate (not marking in figure);Be positioned on substrate partly leads Body layer 401;It is positioned at multiple device cells of dispersed and distributed on semiconductor layer 401;Wherein, individual devices unit Including at least one basic device, single basic device include symmetrical a pair drain electrode 404 of ecto-entad, A pair first grid 403 and a source electrode 402 of centre, at least one basic device above-mentioned is positioned at active area On (region in the dotted line frame at least one basic device in Figure 13);It is positioned on passive region, for electricity Connect the grid interconnection metal 405 of the grid 403 of multiple device cell, and be used for electrically connecting multiple device cell Drain electrode 404 drain electrode interconnection metal 406;The a pair source body 409 being positioned on passive region and a pair leakage body 408, And it is positioned at individual devices unit center, for electrically connecting the grid of at least one basic device on individual devices unit The grid body 407 of pole 403.
Wherein, a pair first grid 403 passes through on passive region, the second grid vertical with first grid 403 410 connect, and a pair drain electrode 404 is connected by leakage body 408, the grid body 407 in individual devices unit, leakage body 408, grid 403, source electrode 402 and drain electrode 404, centered by the central point of individual devices unit, is formed Centrosymmetry pattern.
In the present embodiment, the matrix form that 4 device cells arrange with 2 row 2 is distributed on the semiconductor layer, single Device cell includes 4 basic devices, equal chip area adds the quantity of device, is greatly improved The output of device;The metallic area of the source body being electrically connected to source electrode significantly increases, and contributes to increasing and leads to Hole dimension, reduce further stray inductance value during ground connection, increases the gain of semiconductor device;Single The grid width of basic device, equal to a pair first grid and the length sum of second grid, increases in limited areal Device grid width, improves device output power.
Embodiment seven
The top view of the individual devices unit that Figure 14 provides for the embodiment of the present invention seven, Figure 15 is that the present invention is real Execute the top view of the semiconductor device that example seven provides.As shown in figure 15, the present embodiment based on embodiment six, Eliminate the source body 409 in multiple device cells in Figure 13, save metal material, reduce semiconductor device The gross area of part.
Embodiment eight
The top view of the individual devices unit that Figure 16 provides for the embodiment of the present invention eight, Figure 17 is that the present invention is real Execute the top view of the semiconductor device that example eight provides, unlike the embodiments above, single in the present embodiment The source electrode of device cell is collectively forming T-shaped distribution.As shown in figure 17, this semiconductor device includes substrate (figure In do not mark);The semiconductor layer 501 being positioned on substrate;It is positioned at the multiple of dispersed and distributed on semiconductor layer 501 Device cell;Wherein, individual devices unit includes that at least one basic device, single basic device include source Pole 502, drain electrode 504 and source electrode 502 and drain electrode 504 between grid 503, above-mentioned at least one Basic device is positioned on active area (region of the dotted line frame at least one basic device in Figure 17);Position On passive region, for electrically connecting the first grid interconnection metal 505 of the grid 503 of multiple device cell, and For electrically connecting the first drain electrode interconnection metal 506 of the drain electrode 504 of multiple device cell.
Wherein, the source electrode 502 of individual devices unit is collectively forming T-shaped distribution, and concentration is distributed in single device The middle part of part unit, and the direction of source electrode is consistent;Grid 503 in individual devices unit is by passive region Second grid interconnection metal 507 electrically connect, drain electrode in individual devices unit 504 is by passive region Second drain electrode interconnection metal 508 electrically connects.
In the present embodiment, the matrix form that 4 device cells arrange with 2 row 2 is distributed on the semiconductor layer, single Device cell includes 4 basic devices, equal chip area adds the quantity of device, is greatly improved The output of device.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.Those skilled in the art It will be appreciated that the invention is not restricted to specific embodiment described here, can enter for a person skilled in the art Row various obvious changes, readjust and substitute without departing from protection scope of the present invention.Therefore, though So by above example, the present invention is described in further detail, but the present invention be not limited only to Upper embodiment, without departing from the inventive concept, it is also possible to include other Equivalent embodiments more, And the scope of the present invention is determined by scope of the appended claims.

Claims (10)

1. a semiconductor device, it is characterised in that including:
Substrate;
It is positioned at the semiconductor layer on described substrate;
Being positioned at multiple device cells of dispersed and distributed on described semiconductor layer, the plurality of device cell is with M row N row matrix form be distributed on described semiconductor layer, wherein M and N be all higher than equal to 1 and M and N not It is simultaneously equal to 1;
Wherein, individual devices unit includes that at least one basic device, single basic device include source electrode, leakage Pole and the grid between source electrode and drain electrode, at least one basic device described is positioned on active area.
Semiconductor device the most according to claim 1, it is characterised in that on the plurality of device cell Grid between by grid interconnection metal electrically connect, between the drain electrode on the plurality of device cell by leakage Pole interconnection metal electrical connection, described grid interconnection metal and described drain electrode interconnection metal are positioned on passive region.
Semiconductor device the most according to claim 2, it is characterised in that described grid interconnection metal and Described drain electrode interconnection metal intersection is without electrical connection.
Semiconductor device the most according to claim 2, it is characterised in that the end of described semiconductor device Portion is provided with ground electrode, and the source electrode in the plurality of device cell is by running through described substrate and described quasiconductor The through hole of layer, electrically connects with described ground electrode.
Semiconductor device the most according to claim 2, it is characterised in that described grid is strip grate.
Semiconductor device the most according to claim 2, it is characterised in that the plurality of device cell The direction of grid is different.
Semiconductor device the most according to claim 2, it is characterised in that described semiconductor device also wraps Including and be positioned at grid body on passive region, described grid body is electrically connected to the grid of at least one basic device described, and institute State grid body and be positioned at center or the edge of individual devices unit.
8. the manufacture method of a semiconductor device, it is characterised in that including:
Substrate is formed semiconductor layer;
Described semiconductor layer is formed multiple device cells of the matrix form dispersed and distributed arranged with M row N, Wherein M and N is all higher than equal to 1 and M and N is not simultaneously equal to 1, and individual devices unit includes at least one Basic device, single basic device includes source electrode, drain electrode and the grid between source electrode and drain electrode, institute State at least one basic device to be positioned on active area.
Method the most according to claim 8, it is characterised in that also include:
While forming grid, passive region is formed for electrically connecting the grid on the plurality of device cell Grid interconnection metal;
While forming drain electrode, passive region is formed for electrically connecting the drain electrode on the plurality of device cell Drain electrode interconnection metal.
Method the most according to claim 9, it is characterised in that also include:
Ground electrode is formed in the bottom of described semiconductor device;
Offer between source electrode and described ground electrode in the plurality of device cell and run through described substrate and institute State the through hole of semiconductor layer;
Described source electrode is electrically connected by described through hole with described ground electrode.
CN201510672757.XA 2015-10-16 2015-10-16 A kind of semiconductor devices and its manufacturing method Active CN105895684B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510672757.XA CN105895684B (en) 2015-10-16 2015-10-16 A kind of semiconductor devices and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510672757.XA CN105895684B (en) 2015-10-16 2015-10-16 A kind of semiconductor devices and its manufacturing method

Publications (2)

Publication Number Publication Date
CN105895684A true CN105895684A (en) 2016-08-24
CN105895684B CN105895684B (en) 2018-12-28

Family

ID=57002012

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510672757.XA Active CN105895684B (en) 2015-10-16 2015-10-16 A kind of semiconductor devices and its manufacturing method

Country Status (1)

Country Link
CN (1) CN105895684B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108346690A (en) * 2017-01-24 2018-07-31 恩智浦有限公司 Semiconductor device including switch

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271562B1 (en) * 1998-02-27 2001-08-07 Infineon Technologies Ag Semiconductor component which can be controlled by a field effect
CN101288178A (en) * 2004-12-02 2008-10-15 Nxp股份有限公司 Insulated gate field effect transistors
CN104617092A (en) * 2014-11-06 2015-05-13 苏州捷芯威半导体有限公司 Semiconductor device and manufacturing method thereof
CN104637989A (en) * 2013-11-06 2015-05-20 恩智浦有限公司 Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271562B1 (en) * 1998-02-27 2001-08-07 Infineon Technologies Ag Semiconductor component which can be controlled by a field effect
CN101288178A (en) * 2004-12-02 2008-10-15 Nxp股份有限公司 Insulated gate field effect transistors
CN104637989A (en) * 2013-11-06 2015-05-20 恩智浦有限公司 Semiconductor device
CN104617092A (en) * 2014-11-06 2015-05-13 苏州捷芯威半导体有限公司 Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108346690A (en) * 2017-01-24 2018-07-31 恩智浦有限公司 Semiconductor device including switch
CN108346690B (en) * 2017-01-24 2023-08-01 恩智浦有限公司 Semiconductor device including switch

Also Published As

Publication number Publication date
CN105895684B (en) 2018-12-28

Similar Documents

Publication Publication Date Title
CN208336235U (en) Semiconductor devices
US10312358B2 (en) High electron mobility transistors with improved heat dissipation
TWI525753B (en) Gallium nitride power devices using island topography
EP2465141B1 (en) Gallium nitride microwave and power switching transistors with matrix layout
US8791508B2 (en) High density gallium nitride devices using island topology
WO2015085841A1 (en) Semiconductor device and manufacturing method thereof
US10361271B2 (en) Semiconductor device and method of manufacturing the same
CN103972282B (en) The method of reverse blocking semiconductor devices and manufacture reverse blocking semiconductor devices
US9520490B2 (en) Semiconductor device and method of manufacturing the same
US11862536B2 (en) High power transistors
US8907377B2 (en) High electron mobility transistor and method of manufacturing the same
JP2019096631A (en) Semiconductor device and power converter
CN107768438A (en) Semiconductor device
JP2016009866A (en) Cellular layout for semiconductor devices
JP2016009867A (en) Cellular layout for semiconductor devices
CN104538523B (en) A kind of semiconductor devices for improving current expansion
CN105895684A (en) Semiconductor device and manufacture method therefor
KR101377165B1 (en) High electron mobility transistor in serial connection and method for forming thereof
US11728419B2 (en) High electron mobility transistor

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant