CN101276643B - Write-in method and system of phase variation memory - Google Patents
Write-in method and system of phase variation memory Download PDFInfo
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- CN101276643B CN101276643B CN200710091441A CN200710091441A CN101276643B CN 101276643 B CN101276643 B CN 101276643B CN 200710091441 A CN200710091441 A CN 200710091441A CN 200710091441 A CN200710091441 A CN 200710091441A CN 101276643 B CN101276643 B CN 101276643B
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Abstract
The invention provides a writing method of a phase variation memory, comprising providing a first writing signal for the phase variation memory so that the temperature of the phase variation memory is larger than a first temperature; and providing a second writing signal for the phase variation memory so that the temperature of the phase variation memory is approximately maintained at a second temperature.
Description
Technical field
The present invention is a kind of wiring method and system of Ovonics unified memory, particularly a kind of wiring method of Ovonics unified memory of high speed operation strategy and system.
Background technology
Growth along with the portable applications product, make the demand of nonvolatile memory that the trend that day by day increases be arranged, the Ovonics unified memory technology is owing to have competitive characteristics such as speed, power, capacity, fiduciary level, processing procedure integrated level and cost, has been regarded as the non-volatile memory technologies of potentialization of next epoch.The maximum bottleneck that present Ovonics unified memory is faced is that operating current is too high, makes its density effectively to promote, thereby reduces its competitive power.
In recent years, there is certain methods to be suggested successively, comprises and adopt new framework, as edge contact formula (edge contact) or limitation formula structure (confinedstructure) etc. with solving the too high problem of operating current; Or adopt new recording layer material, as Ge-Sb-Te compound (N-dopedGST), the oxygen of doping nitrogen (O-doped) material etc. that mixes.Yet, framework that these are new or material all may cause Ovonics unified memory to have the phenomenon of imperfect crystal or amorphous when crystallization, cause crystallization (SET) resistance and noncrystallineization (RESET) resistance to be lowered effectively and to improve, and then cause less sensing margin (sensing margin) and relatively poor homogeneity to distribute.Present most solution is to elongate the running time of crystallization (SET) and noncrystallineization (RESET), yet this method will reduce characteristics such as the power of Ovonics unified memory and speed.
The operation of Ovonics unified memory mainly is to be applied on the Ovonics unified memory by two kinds of different big or small current impulses, make Ovonics unified memory because the effect of Ohmic heating, cause amorphous state (amorphous state) that regional area causes phase-transition material because of different temperature changes with crystalline state (crystalline state) but anti-phase change, and reach the purpose of storage data by the different resistance values that this two phase transformations structure is presented.The current impulse synoptic diagram of Fig. 1 for generally Ovonics unified memory being write and reads.When Ovonics unified memory carries out the RESET operation, mainly be to apply the short and higher reset current I of pulse height of pulse width
RESET, make the temperature of Ovonics unified memory regional area can be higher than the melting temperature (T of phase-transition material by applying of this pulse
m) and melt.When the zone of this thawing during in instantaneous temperature reduction, carry out crystallization again owing to have insufficient time to, therefore in the process of solidifying, can form amorphous state, this moment, phase-transition material had high value.On the other hand, when Ovonics unified memory carries out the SET operation, then be to utilize pulse width broad and the lower setting electric current I of pulse height
SET, make the temperature of Ovonics unified memory regional area between the Tc (T of phase-transition material by applying of this pulse
c) and melting temperature (T
m) between, so then can be again by crystallization through the noncrystallineization zone after the SET operation.As mentioned above, the RESET of Ovonics unified memory operation and SET operation be promptly as writing in the storer (write) and wiping (erase) action, at last by Ovonics unified memory being operated in the effect that resistance difference between crystalline state and the amorphous state reaches storage.During data in reading Ovonics unified memory, then utilize size of current less than I
SETRead electric current I
ReadJudge its resistance value, to learn the data of its storage.
Along with the development of Ovonics unified memory technology, the size of phase change storage element (PCM cell) has the trend of micro gradually.After the size micro, crystallization (SET) operation of phase change storage element (PCM cell) can become more difficult, that is crystallization (SET) operation may make active region form paracrystalline state, can be in some residual a spot of amorphous areas in zone.This makes crystallization (SET) resistance of phase change storage element (PCM cell) that the trend of increase gradually be arranged, thereby the scope that causes sensing margin (sensing margin) diminishes and instability, in addition, also very easily cause the not good problem of homogeneity because of processing procedure between the different storage elements or the change on the material.Traditionally, the main practice that desire is improved the problems referred to above is by prolonging crystallization pulse width (SET pulse width), so can make the crystallization of active region become more complete, thereby can improve sensing margin (sensing margin) and the not good problem of homogeneity.Yet shortcomings such as this practice may cause that power attenuation increases, overheated (overheating) and operating speed are slack-off.
Summary of the invention
The invention provides a kind of wiring method of Ovonics unified memory, comprising: provide first write pulse signal to Ovonics unified memory, the temperature that makes this Ovonics unified memory is greater than first temperature; And provide second write pulse signal to this Ovonics unified memory, make the temperature of this Ovonics unified memory maintain second temperature substantially.
The present invention also provides a kind of wiring method of Ovonics unified memory, comprise: Ovonics unified memory is carried out noncrystallineization (RESET) program, this program comprises: provide the first noncrystallineization pulse signal to this Ovonics unified memory, make the melting temperature of the temperature of this Ovonics unified memory more than or equal to this Ovonics unified memory, and provide the second noncrystallineization pulse signal to this Ovonics unified memory, make the temperature of this Ovonics unified memory maintain first temperature substantially.This Ovonics unified memory is carried out crystallization (SET) program, this program comprises: provide the first crystallization pulse signal to this Ovonics unified memory, make the Tc of the temperature of this Ovonics unified memory greater than this Ovonics unified memory, and provide the second crystallization pulse signal to this Ovonics unified memory, make the temperature of this Ovonics unified memory maintain second temperature substantially.
The present invention also provides a kind of writing system of Ovonics unified memory, comprises Ovonics unified memory, the first write pulse signal generator, second write pulse signal generator and the control module.This first write pulse signal generator is in order to produce first write pulse signal.This second write pulse signal generator is in order to produce second write pulse signal.This control module, temperature according to this Ovonics unified memory, control the output of this first write pulse signal and this second write pulse signal, wherein when the temperature of Ovonics unified memory during greater than first temperature, this second write pulse signal is imported this Ovonics unified memory, make the temperature of this Ovonics unified memory maintain second temperature substantially.
The present invention also provides a kind of wiring method of Ovonics unified memory, comprising: provide first write pulse signal to Ovonics unified memory, make the melting temperature of the temperature of this Ovonics unified memory more than or equal to this Ovonics unified memory; Provide second write pulse signal to this Ovonics unified memory, make the temperature of this Ovonics unified memory maintain first temperature substantially.
Description of drawings
The current impulse synoptic diagram of Fig. 1 for generally Ovonics unified memory being write and reads.
Fig. 2 is for writing the synoptic diagram of the embodiment of pulse according to crystallization of the present invention (SET).
Fig. 3 is the synoptic diagram according to the embodiment of noncrystallineization of the present invention (RESET) pulse.
Fig. 4 is the synoptic diagram according to the embodiment of write pulse signal of the present invention.
Fig. 5 is the synoptic diagram according to the embodiment of the signal generating circuit of write pulse signal of the present invention.
Fig. 6 is the synoptic diagram according to the embodiment of write pulse signal of the present invention.
Fig. 7 is the synoptic diagram according to the embodiment of the writing system of a kind of Ovonics unified memory of the present invention.
[main element label declaration]
51～the first signal generators
53～secondary signal generator
71～Ovonics unified memory
72～control module
73～the first write pulse signal generators
74～the second write pulse signal generators
75～temperature detecting unit
Embodiment
Fig. 2 is the synoptic diagram according to the embodiment of crystallization of the present invention (SET) pulse.In the crystallization pulse shown in Fig. 1 is the lower but long square wave of holding time of electric current, utilize its long duration of pulse to increase the crystallization usefulness of Ovonics unified memory, but this may cause Ovonics unified memory overheated, and forms noncrystallineization (RESET).Therefore provide a kind of new crystallization pulse among Fig. 2, not only can prolong the crystallization time of Ovonics unified memory, also can avoid Ovonics unified memory overheated and form noncrystallineization, and then can get the advantage of phase change element crystallization high speed operation.
Please refer to Fig. 2, at first import the first crystallization pulse S1, it is held time and is t1, makes the temperature of Ovonics unified memory surpass minimum crystallized temperature T
c, but be no more than melting temperature T
mProfess it, import the first crystallization pulse S1 and make the temperature of Ovonics unified memory arrive best crystallized temperature Tc
OptThe operational zone between, and this best crystallized temperature Tc
OptTemperature between the operational zone is between crystallized temperature T
cWith melting temperature T
mBetween.In the present embodiment, best crystallized temperature is meant that under this temperature the crystallization time of this Ovonics unified memory is the write operation of this Ovonics unified memory the longest allowed crystallization time.
When the operating temperature of Ovonics unified memory enters its best crystallized temperature Tc
Opt.The time, then again Ovonics unified memory is imported the second crystallization pulse S2, the temperature maintenance that makes Ovonics unified memory is at the best crystallized temperature Tc of Ovonics unified memory
OptInterval, i.e. T
c＜Tc
Opt.＜Tm.In the present embodiment, the second crystallization pulse S2 is that (pulse width modulation PWM), can adjust its each pulse by adjustment its ratio cycle (duty cycle) and be positioned at electric current I pulse width modulating signal
SetThe time hold time.In this enforcement, the t2 that holds time might not equate with t3.In the present embodiment, the second crystallization pulse S2 can detect the temperature of Ovonics unified memory by control module, and adjusts its each second crystallization pulse and be positioned at electric current I by adjusting its ratio cycle
SetThe time hold time, reach Adaptive Control.In the present embodiment, the first crystallization pulse S1 equates with the current peak of the second crystallization pulse S2, but in another embodiment, the current peak of the first crystallization pulse S1 and the second crystallization pulse S2 is also unequal.
Fig. 3 is the synoptic diagram according to the embodiment of noncrystallineization of the present invention (RESET) pulse.In the noncrystallineization pulse shown in Fig. 1 is that the higher but short square wave of holding time of electric current utilizes its higher pulse current to the Ovonics unified memory Fast Heating, and makes the temperature of Ovonics unified memory surpass its melting temperature (T
m), reach the purpose of noncrystallineization, but this may cause excessive noncrystallineization of Ovonics unified memory, make the incomplete situation of crystallization takes place when next Ovonics unified memory carries out crystallization easily, and then can get the advantage of phase change element crystallization high speed operation.
Please refer to Fig. 3, at first import the first noncrystallineization pulse S1, it is held time and is t1, makes the temperature of Ovonics unified memory surpass its melting temperature T
mWhen the temperature of Ovonics unified memory surpasses its melting temperature T
mThe time, Ovonics unified memory is imported the second noncrystallineization pulse S2, make the melting temperature T of the temperature maintenance of Ovonics unified memory at Ovonics unified memory
mOn.In the present embodiment, can stipulate the best noncrystallineization temperature T a of the temperature of this Ovonics unified memory
Opt.Scope as shown in Figure 3, to avoid Ovonics unified memory by excessive noncrystallineization.In the present embodiment, best noncrystallineization temperature is Ta
Opt.Scope.Profess it, the second noncrystallineization pulse S2 is except the temperature maintenance that the makes Ovonics unified memory melting temperature T at Ovonics unified memory
mOn outside, also must avoid the temperature of Ovonics unified memory to surpass (T
m+ Ta
Opt.).In the present embodiment, the second noncrystallineization pulse S2 is that (pulse width modulation PWM), can adjust its each pulse by adjustment its ratio cycle (duty cycle) and be positioned at electric current I pulse width modulating signal
ResetThe time hold time.In this enforcement, the t2 that holds time might not equate with t3.In the present embodiment, the second noncrystallineization pulse S2 can detect the temperature of Ovonics unified memory by control module, and adjusts its each second noncrystallineization pulse and be positioned at electric current I by adjusting its ratio cycle
ResetThe time hold time, reach Adaptive Control.In the present embodiment, the first crystallization pulse S1 equates with the current peak of the second crystallization pulse S2, but in another embodiment, the current peak of the first crystallization pulse S1 and the second crystallization pulse S2 is also unequal.
Fig. 4 is the synoptic diagram according to the embodiment of write pulse signal of the present invention.In the present embodiment, write pulse signal comprises the first write pulse signal S1 and the second write pulse signal S2.The first write pulse signal S1 has voltage peak V1, and its time that maintains voltage peak V1 is t1.The purpose of the first write pulse signal S1 is that temperature increase with Ovonics unified memory is to predetermined temperature, as the crystallized temperature T among Fig. 2
cThe melting temperature T of Ovonics unified memory among (at the SET operation) or Fig. 3
m(at the RESET operation).The second write pulse signal S2 has voltage peak V1, and its time that maintains voltage peak V1 be respectively t3 and t5, and the second write pulse signal S2 has voltage peak V2 in addition, and its time that maintains voltage peak V2 is respectively t2 and t4.The purpose of the second write pulse signal S2 is to make in the certain limit of temperature maintenance on predetermined temperature of Ovonics unified memory, and the second write pulse signal S2 shown in Fig. 4 utilizes the voltage of pulse signal in voltage peak V1 and V2 conversion, keeps the crystallization (Tc that Ovonics unified memory operates in the best and reach
Opt.At the SET operation) or best noncrystalline (Ta
Opt.At RESET operation) purpose of temperature range.
Present embodiment is to be that example explains with the square wave, yet the first write pulse signal S1 and the second write pulse signal S2 be not as limit.Speech for example, the first write pulse signal S1 or the second write pulse signal S2 be can triangular wave or the write pulse signal of other non-square wave reach the purpose of keeping the Ovonics unified memory temperature.Realize that about the write pulse signal that uses triangular wave or other non-square wave should be those skilled in the art can understand, will not continue to describe in detail at this.
Fig. 5 is the synoptic diagram of embodiment of the signal generating circuit of write pulse signal shown in Figure 4.First signal generator 51 is sent to totalizer 56 for the square wave of voltage peak V2 is provided by first amplifier 52.In the present embodiment, the enlargement ratio of first amplifier 52 for example is 1.In the present embodiment, first signal generator 51 also can be Dc bias V2 is provided merely, and determines whether exporting this Dc bias by control signal (not drawing on the figure).Secondary signal generator 53 is sent to totalizer 56 by second amplifier 54 with switch 55 for the square wave of voltage peak (V1-V2) is provided.In the present embodiment, the enlargement ratio of second amplifier 54 for example is 1.
When signal generating circuit 50 produced the first write pulse signal S1, switch 55 conductings made totalizer 56 directly with the output signal mutually adduction output of first signal generator 51 with secondary signal generator 53.When signal generating circuit 50 produced the second write pulse signal S2, switch 55 can determine whether the output signal of secondary signal generator 53 is sent to totalizer 56 according to Continuity signal.Illustrate with the second write pulse signal S2 shown in Figure 4, switch 55 can cut out the time of t2 earlier, follow the time of conducting t3 again, then close the time of t4 again, follow the time of conducting t5 again, so just can export the second write pulse signal S2 as shown in Figure 4 easily, and its required circuit is easy to realize.In the present embodiment, the Continuity signal of gauge tap 55 can be clock signal or arbitrary cyclical signal.In addition, in the present embodiment, second writes the temperature that pulse S2 can detect Ovonics unified memory by control module, and adjusts the time of the output signal of output secondary signal generator 53 by adjusting Continuity signal, reaches Adaptive Control.
Fig. 6 is the synoptic diagram according to the embodiment of write pulse signal of the present invention.In the present embodiment, write pulse signal comprises the first write pulse signal S1 and the second write pulse signal S2.The first write pulse signal S1 has voltage peak V1, and its time that maintains voltage peak V1 is t1.The purpose of the first write pulse signal S1 is that temperature increase with Ovonics unified memory is to predetermined temperature, as the crystallized temperature T among Fig. 2
cThe melting temperature T of Ovonics unified memory among (at the SET operation) or Fig. 3
m(at the RESET operation).The second write pulse signal S2 is three rank signals, has voltage peak V1, V2 and V3.The purpose of the second write pulse signal S2 is to make in the certain limit of temperature maintenance on predetermined temperature of Ovonics unified memory, and the second write pulse signal S2 shown in Fig. 6 can utilize the voltage of pulse signal to change between voltage peak V1, V2 and V3, keeps the crystallization (Tc that Ovonics unified memory operates in the best and reach
Opt.At the SET operation) or noncrystalline (Ta
Opt.At RESET operation) purpose of temperature range.And the second write pulse signal S2 shown in Fig. 6 can be more known write signal save power, and be easy to realize.Present embodiment is to be that example explains with the square wave, yet the first write pulse signal S1 and the second write pulse signal S2 be not as limit.
The second write pulse signal S2 also can utilize similar signal generating circuit shown in Figure 5 50 to produce among Fig. 6, in in order to the signal circuit that produces the second write pulse signal S2 among Fig. 6, comprised and to have distinguished output voltage V 3, (V2-V3) and signal generator (V1-V3).And the t2～t9 that holds time of the second write pulse signal S2 also can be by reaching as switch among Fig. 5 55 and Continuity signal among Fig. 6.
Fig. 7 is the synoptic diagram according to the embodiment of the writing system of a kind of Ovonics unified memory of the present invention.Temperature detecting unit 76 is in order to detecting the temperature of Ovonics unified memory 71, and testing result is sent to control module 72.Control module 72 receives the first pulse signal S1 that the first write pulse signal generator 73 produces, in order to Ovonics unified memory 71 is heated on the predetermined temperature.The temperature that detects Ovonics unified memory 71 when temperature detecting unit 76 is during greater than this predetermined temperature, and control module 72 stops first pulse signal S1 input Ovonics unified memory 71.Control module 72 receives and transmits the second pulse signal S2 that the second write pulse signal generator 74 produces to Ovonics unified memory 71, in order to the temperature of keeping Ovonics unified memory 71 in particular range.
When Ovonics unified memory 71 carried out crystallization, this predetermined temperature was the Tc T of this Ovonics unified memory 71
c, and the second pulse signal S2 keeps Ovonics unified memory 71 in this crystallized temperature T
C.Melting temperature T with this Ovonics unified memory 71
mBetween.When Ovonics unified memory 71 carried out noncrystallineization, this predetermined temperature was the melting temperature T of this Ovonics unified memory 71
m, and the temperature of keeping Ovonics unified memory 71 drops on best noncrystallineization temperature range Ta
Opt.In.The second pulse signal S2 that the first pulse signal S1 that control module 72 also can produce the first write pulse signal generator 73 and the second write pulse signal generator 74 produce produces the 3rd write pulse signal S3 by totalizer 75.In the present embodiment, this the first write pulse signal generator 73 and the second write pulse signal generator 74 can be respectively according to first control signal and second control signals, adjust electric current (or voltage or power) the peak value size of this first write pulse signal S1 and this second pulse signal S2, and be positioned at holding time of this electric current (or voltage or power) peak value.
Though the present invention discloses as above with specific embodiment; so it is only in order to be easy to illustrate technology contents of the present invention; and be not with narrow sense of the present invention be defined in this embodiment; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (31)
1. the wiring method of an Ovonics unified memory comprises:
Provide first write pulse signal to Ovonics unified memory, the temperature that makes this Ovonics unified memory is greater than first temperature; And
Provide second write pulse signal to this Ovonics unified memory, the temperature maintenance that makes this Ovonics unified memory is in second temperature,
Wherein, when this Ovonics unified memory carried out crystallization, this first temperature was a Tc, and this second temperature is between the melting temperature and this first temperature of this Ovonics unified memory; When Ovonics unified memory carried out noncrystallineization, this first temperature was the melting temperature of this Ovonics unified memory, and this second temperature is greater than this first temperature.
2. the wiring method of Ovonics unified memory according to claim 1, wherein this first write pulse signal has first current peak, and holding time of this first current peak is first to hold time.
3. the wiring method of Ovonics unified memory according to claim 1, wherein this second write pulse signal is a pulse width modulating signal.
4. the wiring method of Ovonics unified memory according to claim 1, wherein this second write pulse signal has second current peak, and holding time of this second current peak is second to hold time.
5. the wiring method of Ovonics unified memory according to claim 4, wherein this first write pulse signal has first current peak, and this second current peak equals this first current peak.
6. the wiring method of Ovonics unified memory according to claim 4, wherein this second write pulse signal also comprises the 3rd write pulse signal, has the 3rd current peak, and holding time of the 3rd current peak held the time for the third dimension.
7. the wiring method of Ovonics unified memory according to claim 6, wherein the 3rd current peak is less than this second current peak.
8. the wiring method of Ovonics unified memory according to claim 1, wherein to be positioned at holding time of first current peak be first to hold time to this first write pulse signal, it is second to hold time that this second write pulse signal is positioned at holding time of second current peak, and this second is held time and first hold time less than this.
9. the wiring method of an Ovonics unified memory comprises:
Ovonics unified memory is carried out noncrystallineization program, comprising:
Provide the first noncrystallineization pulse signal to this Ovonics unified memory, make the melting temperature of the temperature of this Ovonics unified memory more than or equal to this Ovonics unified memory; And
Provide the second noncrystallineization pulse signal to this Ovonics unified memory, the temperature maintenance that makes this Ovonics unified memory is in first temperature;
This Ovonics unified memory is carried out the crystallization program, comprising:
Provide the first crystallization pulse signal to this Ovonics unified memory, make the Tc of the temperature of this Ovonics unified memory greater than this Ovonics unified memory; And
Provide the second crystallization pulse signal to this Ovonics unified memory, the temperature maintenance that makes this Ovonics unified memory is in second temperature,
Wherein this first temperature is more than or equal to this melting temperature of this Ovonics unified memory, and this second temperature is between this melting temperature and this Tc of this Ovonics unified memory.
10. the wiring method of Ovonics unified memory according to claim 9, wherein this first noncrystallineization pulse signal has first current peak, and holding time of this first current peak was the first noncrystallineization time, and wherein this second noncrystallineization pulse signal has second current peak, and holding time of this second current peak was the second noncrystallineization time, and this second current peak equals this first current peak.
11. the wiring method of Ovonics unified memory according to claim 10, wherein this second noncrystallineization time is less than this first noncrystallineization time.
12. the wiring method of Ovonics unified memory according to claim 9, wherein this second noncrystallineization pulse signal also comprises the 3rd noncrystallineization pulse signal, have the 3rd current peak, and holding time of the 3rd current peak was the 3rd noncrystallineization time.
13. the wiring method of Ovonics unified memory according to claim 12, wherein the 3rd current peak is less than this second current peak.
14. the wiring method of Ovonics unified memory according to claim 12, wherein the 3rd noncrystallineization pulse signal is a pulse width modulating signal.
15. the wiring method of Ovonics unified memory according to claim 9, wherein this second noncrystallineization pulse signal is a pulse width modulating signal.
16. the wiring method of Ovonics unified memory according to claim 9, wherein this first crystallization pulse signal has the 4th current peak, and holding time of the 4th current peak was the first crystallization time, and wherein this second crystallization pulse signal has the 5th current peak, and holding time of the 5th current peak was the second crystallization time, and the 5th current peak is less than the 4th current peak.
17. the wiring method of Ovonics unified memory according to claim 16, wherein this second crystallization pulse signal also comprises the 3rd crystallization pulse signal, has the 6th current peak, and holding time of the 6th current peak was the 3rd crystallization time.
18. the wiring method of Ovonics unified memory according to claim 17, wherein the 6th current peak is less than the 5th current peak.
19. the wiring method of Ovonics unified memory according to claim 17, wherein the 3rd crystallization pulse signal is a pulse width modulating signal.
20. the writing system of an Ovonics unified memory comprises:
Ovonics unified memory;
The first write pulse signal generator is in order to produce first write pulse signal;
The second write pulse signal generator is in order to produce second write pulse signal; And
Control module, temperature according to this Ovonics unified memory, control the output of this first write pulse signal and this second write pulse signal, wherein when the temperature of Ovonics unified memory during greater than first temperature, this second write pulse signal is imported this Ovonics unified memory, the temperature maintenance that makes this Ovonics unified memory is in second temperature
Wherein, when this Ovonics unified memory carried out crystallization, this first temperature was a Tc, and this second temperature is between the melting temperature and this first temperature of this Ovonics unified memory; When Ovonics unified memory carried out noncrystallineization, this first temperature was the melting temperature of this Ovonics unified memory, and this second temperature is greater than this first temperature.
21. the writing system of Ovonics unified memory according to claim 20 wherein also comprises temperature measurement unit, in order to detect the temperature of this Ovonics unified memory.
22. the writing system of Ovonics unified memory according to claim 20 wherein also comprises totalizer, receives this first write pulse signal and this second write pulse signal to produce the 3rd write pulse signal.
23. the writing system of Ovonics unified memory according to claim 20, wherein this first write pulse signal generator can be adjusted the first current peak size of this first write pulse signal according to control signal, and is positioned at holding time of this first current peak.
24. the writing system of Ovonics unified memory according to claim 20, wherein this second write pulse signal generator can be adjusted the second current peak size of this second write pulse signal according to control signal, and is positioned at holding time of this second current peak.
25. the wiring method of an Ovonics unified memory comprises:
Provide first write pulse signal to Ovonics unified memory, make the melting temperature of the temperature of this Ovonics unified memory more than or equal to this Ovonics unified memory; And
Provide second write pulse signal to this Ovonics unified memory, the temperature maintenance that makes this Ovonics unified memory is in first temperature,
Wherein first temperature is more than or equal to the melting temperature of this Ovonics unified memory.
26. the wiring method of Ovonics unified memory according to claim 25, wherein this first write pulse signal has first current peak, and holding time of this first current peak is first to hold time.
27. the wiring method of Ovonics unified memory according to claim 25, wherein this second write pulse signal is a pulse width modulating signal.
28. the wiring method of Ovonics unified memory according to claim 25, wherein this second write pulse signal has second current peak, and holding time of this second current peak is second to hold time.
29. the wiring method of Ovonics unified memory according to claim 28, wherein this first write pulse signal has first current peak, and this second current peak is less than this first current peak.
30. the wiring method of Ovonics unified memory according to claim 28, wherein this second write pulse signal also comprises the 3rd write pulse signal, has the 3rd current peak, and holding time of the 3rd current peak held the time for the third dimension.
31. the wiring method of Ovonics unified memory according to claim 25, wherein to be positioned at holding time of first current peak be first to hold time to this first write pulse signal, it is second to hold time that this second write pulse signal is positioned at holding time of second current peak, and this second is held time and first hold time less than this.
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| TWI347607B (en) | 2007-11-08 | 2011-08-21 | Ind Tech Res Inst | Writing system and method for a phase change memory |
| TWI402845B (en) | 2008-12-30 | 2013-07-21 | Higgs Opl Capital Llc | Verification circuits and methods for phase change memory |
| TWI412124B (en) | 2008-12-31 | 2013-10-11 | Higgs Opl Capital Llc | Phase change memory |
| EP3005372A4 (en) * | 2013-05-29 | 2017-01-18 | Hewlett-Packard Enterprise Development LP | Writable device based on alternating current |
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| CN1764982A (en) * | 2003-03-18 | 2006-04-26 | 株式会社东芝 | Phase-change memory device |
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