CN101894587A - Self-limit writing pulse-generating circuit for phase-change memory - Google Patents
Self-limit writing pulse-generating circuit for phase-change memory Download PDFInfo
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- CN101894587A CN101894587A CN2010102355664A CN201010235566A CN101894587A CN 101894587 A CN101894587 A CN 101894587A CN 2010102355664 A CN2010102355664 A CN 2010102355664A CN 201010235566 A CN201010235566 A CN 201010235566A CN 101894587 A CN101894587 A CN 101894587A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0038—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
Abstract
The invention provides a self-limit writing pulse-generating circuit for a phase-change memory. The circuit comprises a memory unit and a writing drive circuit which provides writing pulse signals and erasing pulse signals for the memory unit, wherein the writing drive circuit further comprises a voltage source, a pair of PMOS tubes electrically connected with the voltage source, a bias circuit electrically connected with drain electrodes of the PMOS tubes, a reference circuit electrically connected with the bias circuit and a pulse width control circuit; the reference circuit comprises a target resistor, a gate tube electrically connected with the target resistor and a word line inputting effective control signals to the gate tube. The self-limit writing pulse generating circuit can detect the state of the memory unit by setting the reference circuit and the pulse width control circuit when the memory unit completes writing operation or erasing operation, and regulates the duration of writing pulse so as to improve the memory speed of the phase-change memory.
Description
Technical field
The present invention relates to phase transition storage, relate in particular to the self-limit writing pulse-generating circuit of phase transition storage.
Background technology
Phase transition storage (phase change memory), it is a kind of novel resistor type non-volatile semiconductor memory, it is a storage medium with the chalcogenide compound material, utilize the phase-change material be worked into nano-scale crystalline state during with amorphous state different resistance states realize data storage.
See also Fig. 4, and the write/erase operating process of phase transition storage 2 be described in detail in detail:
Write operation (set process): apply that a long and write pulse signal 21 medium tenacity makes that phase-change material temperature is raised under the temperature of fusion, on the Tc after, and keep a period of time to impel nucleus growth, thereby realize the conversion of amorphous state to the polycrystalline attitude, promptly one state is to the conversion of " 0 " attitude.
Erase operation (reset process): apply a weak point and strong erasure pulse signal 22, because the effect of heating electrode, electric energy converts heat energy to, and the long-range order of polycrystalline is destroyed, to amorphous conversion, promptly " 0 " attitude is to the conversion of one state by polycrystal in the phase-change material realization.
Read operation (read process): after applying a very weak pulse signal that can not exert an influence to the state of phase-change material, read its state by the resistance value of measuring element unit.
See also Fig. 5, Fig. 5 is phase transition storage 2 design frame charts.Described phase transition storage 2 comprises the write pulse generation circuit 23 of accepting write pulse signal 21 and erasure pulse signal 22, bit line decoding scheme 24 and the column decode circuitry 25 that is electrically connected with write pulse generation circuit 23, and the storage array 26 of accepting bit line decoding scheme 24 and column decode circuitry 25 output signals.Wherein, storage array 26 is made of several phase-change memory cells 27.Bit line decoding scheme 24 is corresponding with the storage array of being made up of phase-change memory cell 27 25 with column decode circuitry 25, and by choosing specific phase-change memory cell 26, it is carried out the reading and writing operation, realizes random-access function.
But, write pulse signal 21 and erasure pulse signal 22 adopt fixing pulse width usually, and some phase-change memory cells 27 that storage array 26 comprises respond different write pulse signal 21 or erasure pulse signal 22 respectively, then the difference of pulse signal selection will influence the writing speed of phase transition storage 2, and storage speed is slack-off at random to make phase transition storage 2.
At the problem that prior art exists, this case designer relies on the industry experience for many years of being engaged in, and the active research improvement is so there has been the self-limit writing pulse-generating circuit of phase transition storage of the present invention.
Summary of the invention
The objective of the invention is in the prior art, the write pulse signal of traditional phase transition storage and erasure pulse signal have fixing pulse width, and the difference that pulse signal is selected makes the phase transition storage slack-off defective of storage speed at random, any state that can the detection of stored unit is provided, and adjust the duration that writes pulse, thereby improve the self-limit writing pulse-generating circuit of phase transition storage storage speed.
For achieving the above object, the present invention adopts following technical scheme: a kind of self-limit writing pulse-generating circuit of phase transition storage, comprise: storage unit, the bit line that described storage unit comprises phase change resistor, the gate tube that is electrically connected with phase change resistor, phase change resistor is programmed, and the word line of control gate tube on off state; Write driving circuit, with thinking that storage unit provides write pulse signal and erasure pulse signal.Wherein, the described driving circuit of writing further comprises voltage source, a pair of PMOS pipe that is electrically connected with voltage source, manages the biasing circuit that drain electrode is electrically connected with PMOS, and reference circuit that is electrically connected with biasing circuit and pulse width control circuit.Described reference circuit comprises target resistance, the gate tube that is electrically connected with target resistance, and word line from effective control signal to gate tube that import.Described target resistance is the polycrystalline attitude low-resistance of the amorphous state high resistant or the phase change resistor of phase change resistor.The grid of the gate tube of storage unit is electrically connected identical word line with the grid of reference circuit.Described pulse width control circuit comprises comparer and the transistor that is electrically connected with comparer.The input end of described comparer is electrically connected with the output terminal of biasing circuit and reference circuit.When the resistance of phase change resistor reached the resistance size of target resistance, the transistor of pulse width control circuit was in off state.
Compared with prior art, the present invention has the following advantages: self-limit writing pulse-generating circuit of the present invention is by being provided with reference circuit and pulse width control circuit, when storage unit is finished write operation or erase operation, state that can the detection of stored unit, and adjust and to write the duration of pulse, thereby improved the storage speed of phase transition storage.
Description of drawings
Fig. 1 is the frame diagram of the self-limit writing pulse-generating circuit of phase transition storage of the present invention.
Fig. 2 is the circuit design drawing of the self-limit writing pulse-generating circuit of phase transition storage of the present invention.
Fig. 3 is the self-limit writing pulse-generating circuit write operation process flow diagram of phase transition storage of the present invention.
Fig. 4 is the circuit frame figure of traditional phase transition storage.
Fig. 5 is the sequential chart of the programming of the write pulse signal of traditional phase transition storage and erasure pulse signal.
Embodiment
By the technology contents, the structural attitude that describe the invention in detail, reached purpose and effect, described in detail below in conjunction with embodiment and conjunction with figs..
See also Fig. 1, Fig. 1 is the frame diagram of self-limit writing pulse-generating circuit 1.Described self-limit writing pulse-generating circuit 1 comprises the storage unit 10 of storing at random, and writes driving circuit 11 to storage unit 10 input write pulse signals and erasure pulse signal.
See also Fig. 1, and in conjunction with consulting Fig. 2.Described storage unit 10 comprises phase change resistor 12, first gate tube 13 that is electrically connected with phase change resistor 12, be used for bit line 14 that the phase change resistor 12 of storage unit 10 is programmed, and useful signal is provided and controls the word line 15 of gate tube 14 on off states to described gate tube 14.
Write driver circuit 11 comprises a pair of voltage source 111, and described voltage source 111 comprises write current is offered bit line 14 is programmed for write state with the storage unit 10 that will connect write current source and will wipe current source and offer bit line 14 is programmed for erase status with the storage unit 10 that will be connected the current source of wiping.
Write driver circuit 11 also comprises a pair of PMOS pipe 112 that is electrically connected with voltage source 111, first biasing circuit 113 that is electrically connected with the drain electrode of PMOS pipe 1121 in the PMOS pipe 112, manage the 2nd PMOS in 112 with PMOS manages second biasing circuit 114 that 1122 drain electrode is electrically connected, and reference circuit 115 that is electrically connected with first biasing circuit 113 and the pulse width control circuit 116 that is electrically connected with second biasing circuit 114.Wherein, the grid of PMOS pipe 1121 is communicated with missing.The one PMOS pipe 1121 is communicated with the grid of the 2nd PMOS pipe 1122.First biasing circuit 113 is duplicate circuits of second biasing circuit 114.Described first biasing circuit 113 and described second biasing circuit 114 are in order to adjust write pulse signal and erasure pulse signal.
Described reference circuit 115 comprises target resistance 1151, second gate tube 1152 that is electrically connected with target resistance 1151, and word line 15 from effective control signal to second gate tube 1152 that import.The source ground of described second gate tube 1152, the drain electrode of second gate tube 1152 is electrically connected target resistance 1152.The grid of the grid of second gate tube 1152 and first gate tube 13 is electrically connected with identical word line 15.The size of target resistance 1152 is the polycrystalline attitude low-resistance of the amorphous state high resistant or the phase-change material of phase-change material.
Described pulse width control circuit 116 comprises comparer 1161, and controls the transistor 1162 that turn-offs by comparer 1161.Wherein, the input end of comparer 1161 is electrically connected with the output terminal of first biasing circuit 113 and the output terminal of second biasing circuit 114.Simultaneously, the output terminal of reference circuit 115 is electrically connected with comparer 1161.The grid of transistor 1162 is electrically connected with the output terminal of comparer 1161.The drain electrode of transistor 1162 connects the bit line 14 of phase change resistor 12.
Please continue to consult Fig. 2, and, in detail the principle of work of self-limit writing pulse-generating circuit 1 is described in detail in conjunction with consulting Fig. 1.Allow program current by storage unit 10 by the useful signal on the word line 15.Described useful signal is applied to first gate tube 13 and second gate tube 1152 that is operatively connected to bit line 14.First current signal that first biasing circuit 113 and second biasing circuit 114 and voltage source 111 thereof produce is transferred to the input end of the comparer 1161 of pulse width control circuit 116.Simultaneously, second current signal that is produced by reference circuit 115 is transferred to the input end of the comparer 1161 of on-off circuit 116.116 pairs first electric currents 117 of comparer and second electric current 118 compare, and then oxide-semiconductor control transistors 1162 is turn-offed operation.Particularly, promptly when the resistance of phase change resistor 12 is lower than the resistance of target resistance 1151, comparer 1161 is first current signal and second current signal relatively, and make transistor 1162 be in conducting state, and write pulse signal is applied to is used for bit line 14 that storage unit 10 is programmed according to comparison signal.When the resistance of phase change resistor 12 reached the resistance of target resistance 1151, comparer 1161 is first current signal and second current signal relatively, and make transistor 1162 be in off state according to comparison signal, and remove write pulse signal.
See also Fig. 3, Fig. 3 is for being programmed for storage unit 10 process flow diagram of the running program 119 of write state.In this this running program 119, step S1191 will be for will write the bit line 14 that pulse is applied to the storage unit 10 that just is being programmed.In step S1192, detect the resistance of phase change resistor 12, and in step S1193, the resistance and the target resistance 1151 of phase change resistor 12 compared.Step S1191 apply write pulse in, wait for that the resistance of phase change resistor 12 reaches the resistance of target resistance 1151.In step S1194, when the resistance of phase change resistor 12 reached the resistance of target resistance 1151, pulse width control circuit 116 turn-offed.
In sum, self-limit writing pulse-generating circuit 1 of the present invention is by being provided with reference circuit 115 and pulse width control circuit 116, when storage unit 10 is finished write operation or erase operation, state that can detection of stored unit 10, and adjust and to write the duration of pulse, thereby improved the storage speed of phase transition storage.
Those skilled in the art all should be appreciated that, under the situation that does not break away from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any modification or modification fall in the protection domain of appended claims and equivalent, think that the present invention contains these modifications and modification.
Claims (8)
1. the self-limit writing pulse-generating circuit of a phase transition storage comprises:
The bit line that storage unit, described storage unit comprise phase change resistor, the gate tube that is electrically connected with phase change resistor, phase change resistor is programmed, and the word line of control gate tube on off state;
Write driving circuit, with thinking that storage unit provides write pulse signal and erasure pulse signal;
It is characterized in that: the described driving circuit of writing further comprises voltage source, a pair of PMOS pipe that is electrically connected with voltage source, manages the biasing circuit that drain electrode is electrically connected with PMOS, and reference circuit that is electrically connected with biasing circuit and pulse width control circuit.
2. the self-limit writing pulse-generating circuit of phase transition storage according to claim 1, it is characterized in that: described reference circuit comprises target resistance, the gate tube that is electrically connected with target resistance, and word line from effective control signal to gate tube that import.
3. the self-limit writing pulse-generating circuit of phase transition storage according to claim 2, it is characterized in that: described target resistance is the amorphous state high resistant of phase change resistor.
4. the self-limit writing pulse-generating circuit of phase transition storage according to claim 2, it is characterized in that: described target resistance is the polycrystalline attitude low-resistance of phase change resistor.
5. the self-limit writing pulse-generating circuit of phase transition storage according to claim 2 is characterized in that: the grid of the gate tube of storage unit and the identical word line of the grid of reference circuit electrical connection.
6. the self-limit writing pulse-generating circuit of phase transition storage according to claim 1 is characterized in that: described pulse width control circuit comprises comparer and the transistor that is electrically connected with comparer.
7. the self-limit writing pulse-generating circuit of phase transition storage according to claim 6, it is characterized in that: the input end of described comparer is electrically connected with the output terminal of biasing circuit and reference circuit.
8. the self-limit writing pulse-generating circuit of phase transition storage according to claim 6, it is characterized in that: when the resistance of phase change resistor reached the resistance of target resistance, the transistor of pulse width control circuit was in off state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102355664A CN101894587A (en) | 2010-07-23 | 2010-07-23 | Self-limit writing pulse-generating circuit for phase-change memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102355664A CN101894587A (en) | 2010-07-23 | 2010-07-23 | Self-limit writing pulse-generating circuit for phase-change memory |
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| CN101894587A true CN101894587A (en) | 2010-11-24 |
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| CN2010102355664A Pending CN101894587A (en) | 2010-07-23 | 2010-07-23 | Self-limit writing pulse-generating circuit for phase-change memory |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102592671A (en) * | 2012-02-17 | 2012-07-18 | 北京时代全芯科技有限公司 | Write circuit for phase change memories and write method thereof |
| CN108022617A (en) * | 2016-11-04 | 2018-05-11 | 财团法人工业技术研究院 | Variable resistance memory circuit and writing method of variable resistance memory circuit |
| CN110993001A (en) * | 2019-11-06 | 2020-04-10 | 华中科技大学 | Double-end self-checking writing circuit and data writing method of STT-MRAM |
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| US6157571A (en) * | 1998-08-26 | 2000-12-05 | Oki Electric Industry Co., Ltd. | Semiconductor memory device and method of controlling a threshold voltage of the same |
| CN1499526A (en) * | 2002-11-07 | 2004-05-26 | ������������ʽ���� | Semiconductor memory and its mfg. method |
| CN1505052A (en) * | 2002-12-04 | 2004-06-16 | ������������ʽ���� | Semiconductor memory device and method for programming and erasing a memory cell |
| CN1574093A (en) * | 2003-06-03 | 2005-02-02 | 三星电子株式会社 | Device and method for pulse width control in a phase change memory device |
| US20070153563A1 (en) * | 2006-01-03 | 2007-07-05 | Thomas Nirschl | Write circuit for resistive memory |
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2010
- 2010-07-23 CN CN2010102355664A patent/CN101894587A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6157571A (en) * | 1998-08-26 | 2000-12-05 | Oki Electric Industry Co., Ltd. | Semiconductor memory device and method of controlling a threshold voltage of the same |
| CN1499526A (en) * | 2002-11-07 | 2004-05-26 | ������������ʽ���� | Semiconductor memory and its mfg. method |
| CN1505052A (en) * | 2002-12-04 | 2004-06-16 | ������������ʽ���� | Semiconductor memory device and method for programming and erasing a memory cell |
| CN1574093A (en) * | 2003-06-03 | 2005-02-02 | 三星电子株式会社 | Device and method for pulse width control in a phase change memory device |
| US20070153563A1 (en) * | 2006-01-03 | 2007-07-05 | Thomas Nirschl | Write circuit for resistive memory |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102592671A (en) * | 2012-02-17 | 2012-07-18 | 北京时代全芯科技有限公司 | Write circuit for phase change memories and write method thereof |
| CN102592671B (en) * | 2012-02-17 | 2015-06-17 | 北京时代全芯科技有限公司 | Write circuit for phase change memories and write method thereof |
| CN108022617A (en) * | 2016-11-04 | 2018-05-11 | 财团法人工业技术研究院 | Variable resistance memory circuit and writing method of variable resistance memory circuit |
| CN110993001A (en) * | 2019-11-06 | 2020-04-10 | 华中科技大学 | Double-end self-checking writing circuit and data writing method of STT-MRAM |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Application publication date: 20101124 |