KR100650098B1 - Programming a phase-change material memory - Google Patents

Abstract

The memory device has a constituent cell 604 that includes a structural phase change material for storing data of the cell. Such a material may be, for example, a chalcogenide alloy. A first pulse 204 is applied to the cell 604 to place the material in a first state, such as a reset state in which the material is relatively amorphous and has a relatively high resistivity. A second pulse 208 is then applied to the cell 604 to change the material from the first state to a second, different state, such as a set state in which the material is relatively crystalline and has a relatively low resistivity. The second pulse 208 generally has a triangular shape rather than a rectangular shape.

Phase change memory, chalcogenide, program, first pulse, second pulse, intermediate state

Description

PROGRAMMING A PHASE-CHANGE MATERIAL MEMORY

The present invention relates to a technique for programming a structural phase change material solid state memory device, such as using a chalcogenide material that can be programmed to different resistivity states to store data.

Solid-state memory devices using structural phase change materials as data storage mechanisms (herein simply referred to as "phase-change memories") have significant advantages for both cost and performance over conventional charge storage based memories. Has Phase change memory consists of an array of constituent cells, each cell having a predetermined structural phase change material for storing the data of the cell. This material can be, for example, a chalcogenide alloy exhibiting a reversible structural phase change from amorphous to crystalline. A small volume of chalcogenide alloy is integrated in the circuit that serves as a programmable high speed switching resistor. Such a programmable resistor may have a dynamic range of resistivity greater than 40 times between the crystalline state (low resistivity) and the amorphous state (high resistivity), and may represent a number of intermediate states allowing multiple bit storage in each cell. Data stored in a cell is read by measuring the resistance of the cell. Chalcogenide alloy cells are also nonvolatile.

Prior art for programming a phase change memory cell applies a square pulse current (of constant magnitude) to the cell at a voltage greater than the switching threshold for the phase change material, which puts the material in a reset state (amorphous and high resistivity). It is. Subsequently, a subsequent square pulse is applied at a voltage above the switching threshold, which changes the material to the set state (crystalline and low resistivity). Since the reset pulse has a larger magnitude of current than the set pulse, the temperature of the phase change material rises to the amorphous temperature T _m , and becomes amorphous before the material is rapidly cooled. In order to change to the crystalline state, the material is heated again to an optimum temperature T _opt , which is lower than T _m . The temperature T _opt allows the material in the cell to crystallize in a relatively short time interval and to produce a relatively low resistance. Ideally, this is accomplished by having a set pulse size that is less than the size of the reset pulse to prevent the phase change material from reaching the amorphous temperature, but large enough to allow the material to reach T _opt .

Due to the manufacturing process and material variations in the phase change memories, the actual temperature of the phase change material in the cells of the manufactured device varies significantly from cell to cell, for a given programming current / voltage level obtained by the set pulse. . This variation causes the material in one or more cells in the device to accidentally reach T _m during conventional square set pulse application, such that such cells remain incorrectly in the reset state rather than being changed to the set state. To avoid this problem, conventional programming techniques use a square set pulse (applied to all cells in the device) with reduced magnitude, as shown in FIG. Since the magnitude of the set current is sufficiently low, in terms of expected fluctuations in the cell temperature at that magnitude, it is ensured that no cell in the device reaches T _m while the set pulse is applied. However, this solution requires a longer rectangular set pulse because it is lower than the optimum temperature produced by the lower magnitude of the set pulse, which can slow the programming of the memory device. In addition, many cells in the memory are placed at significantly lower than the optimal crystallization temperature, which reduces the dynamic range of the resistivity between the set and reset states in those cells.

The invention is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like reference numerals indicate like elements. It should be noted that reference to an "an" embodiment herein does not necessarily mean the same embodiment, but rather at least one.

1 shows a conventional pulse sequence for programming a phase change memory.

2 illustrates a sequence of phase change memory programming pulses including a set sweep, in accordance with an embodiment of the present invention.

3 shows the crystallization time in the phase change material memory cell as a function of the temperature of the phase change material.

4 shows another sequence of phase change memory programming pulses, including a set sweep.

5 shows the change in time versus temperature of the phase change material in a memory cell while a set sweep is applied to the cell according to one embodiment of the invention.

6 is a diagram illustrating memory cell resistance versus programming current levels for a particular phase change memory device.

FIG. 7 is a diagram illustrating memory cell resistance versus programming current for a large population of memory cells, illustrating an example of a relatively wide variation in population.

8 is a block diagram of a phase change material memory device, including waveshaping and driving circuitry, designed to provide the voltage and current levels needed to program the component cells of the device.

9 is a block diagram of one embodiment of a portable application of a phase change memory that includes a programming process.

According to one embodiment of the invention, the set pulses for programming the phase change memory are generally triangular rather than rectangular. Such pulses are also referred to herein as "set sweeps." Using set sweep, the magnitude of the set pulse current can be increased so that the phase change material in all the cells in the device changes the set pulse to the set state still due to the downward slope at the trailing portion of the pulse. At least the temperature of T _opt can be reached during the process. Despite manufacturing process and material variations, better crystallization occurs in memory. As better crystallization occurs, the resistivity differences between the set and reset states become even more pronounced. This means that tolerances to variations in memory are increased, resulting in higher yields from manufacturing and test flows, thereby lowering manufacturing costs.

Even if the memory device reaches a temperature as high as T _m when the magnitude of the triangle set pulse is greater than the conventional set current magnitude, the cells reaching T _m are also decayed or have a trailing edge with a downward slope. T _opt, or it will have the possibility of being cooled to a temperature near the crystallization. Decay during the trailing edge is slow enough to ensure that such cells have the minimum required time interval at approximately T _opt so that better crystallization can be achieved within such cells. For devices that are expected to have large fluctuations across the cell population, the current transition time from maximum to minimum for the slope of the trailing edge needs to be longer than those expected to exhibit relatively little fluctuation.

2 illustrates a sequence of phase change memory programming pulses, in accordance with an embodiment of the invention. The first pulse 204 is applied to the constituent cells of the phase change memory. Such pulses can be of any conventional type. A typical shape is a rectangle with a constant current magnitude, as shown. Square pulses are easy to generate using only a single switching transistor (not shown). As described above in the background, the first pulse 204 may be a _reset or amorphous pulse having a magnitude I _reset high enough that the phase change material in the cell reaches the amorphous temperature T _m of the material. . Alternatively, the current magnitudes may be different as long as the first pulse 204 leaves the cell in a predefined state. The pulse width of the first pulse 204 may be selected long enough to be sufficient to obtain a predefined state.

After the application of the first pulse 204, a second pulse 208 is generally triangular in shape as shown. The second pulse 208 has a leading portion with a peak at magnitude or at a maximum I _{2 (max} ) and a trailing portion that attenuates to a minimum value I _{2 (min)} . The tip may have a much larger slope than the tail. The shape of the second pulse 208 can be selected in terms of fabrication processes and material variation for phase change materials and circuitry within the constituent cells of the memory device, so that when the second pulse 208 is applied to each of the cells, All cells of the memory device are changed from the first state to the second different state. The first and second states may be the reset and set states described above in the background. The shaping of the second pulse 208 is the setting of a number of parameters, including the maximum and minimum values, the decay rate / pulse width, in terms of the structure and type of phase change material used as well as the operating thermal environment of the memory device. It includes.

I _{2 (max)} and I _{2 (min)} levels can take a wide range of values. For example, I _{2 (max)} may be substantially larger than I _reset or may be substantially smaller if the pulse width is long enough to ensure that the phase change materials in the cells to which the pulse is applied are crystallized. Crystallization is a function of both temperature and the amount of time the material spends at that temperature. This can be explained by FIG. 3, which shows an exemplary diagram in which the crystallization time (in a phase change material memory cell) is a function of the temperature of the phase change material. The figure shows that at temperatures below T _opt , the material requires a longer time period to crystallize. As a result, at lower current magnitudes (which roughly translate to lower temperatures created in the phase change material), longer pulse widths are needed to set the phase change memory cell. Ideally, the set pulse has a shortest set programming interval T _min and a current magnitude that generates T _opt for as many cells as possible in the memory device to provide the lowest set state resistance for those cells.

The I _{2 (min)} level may change to a wide range of values, including as low as zero. Ideally, the upper limit of I _{2 (min)} for a set pulse is such that the temperature of the phase change material in all cells to which the pulse is applied is below T _m at the end of the pulse (if I _{2 (min)} is reached ₎ . It is a guaranteed value.

4 shows another sequence of phase change memory programming pulses. It should be noted how, in this example, the second pulse (set sweep) 308 has a relatively short middle part between the leading end and the trailing end, even though it is generally represented by a triangle. The middle part has an essentially zero slope relative to the leading and trailing parts. In addition, in contrast to the linear decay rate of FIG. 2, the trailing portion of FIG. 4 has a nonlinear slope. In general, the rate of attenuation at the trailing edge may be in a wide range, including polynomials, logarithms, and exponents, as long as the trailing edges allow all relevant cells in the device to sweep through the rapid crystallization temperature interval.

The effect of the triangle set pulse on the cell temperatures in the phase change memory is shown in the example diagram of FIG. 5. Even if there is a large fluctuation in temperature (shown in shaded bands) for a given magnitude and attenuation rate of the triangle set pulse, the entire memory device is swept through the rapid crystallization temperature interval, thus optimizing the lowest set It can be seen that the resistance is obtained for every cell in the device. This is also shown in FIG. 6, which is a plot of memory cell resistance versus set current for a particular phase change memory device. The resistance is shown as the memory cell responds to various levels of programming current, starting in the reset state. The sequence for applying the various levels of programming current is indicated by arrows starting from the left and then moving to the right and then back to the left. As can be seen, the lowest set resistance is obtained at the set current value just before the rapid rise to the reset level. Due to the triangular nature of the set pulse, this lowest set resistance has the advantage of being "locked in" as the set sweep pulse is swept back down from its peak value. Guaranteed lowest set resistance for each cell in the memory device provides good margins for memory read operations, higher manufacturing yields, as well as better product reliability.

The advantage of set sweep will also be appreciated in view of FIG. 7, which shows a diagram of memory cell resistance versus programming current, for a large population of memory cells in a memory device. This device suffers from a relatively wide variation in its population of constituent memory cells. To take all the cells from the set state to the reset state, a conventional square pulse with an I _reset magnitude will be applied to each cell. However, conventional programming techniques that apply the same square set pulse (with constant magnitude) may not return all cells in the device to the set state. This means that the current magnitude must be at least I _conv. Because it should be as high as. However, at that size, certain cells, i.e., cells corresponding to region 704, will remain in reset when the pulse abruptly terminates. In contrast, this is because all cells including the cells in region 708 as well as the cells in region 704 will be swept through their crystallization temperature interval by the time the pulse is slowly attenuated to I _{2 (min)} . (The result is guaranteed to return to the set state). If I _{2 (min)} is selected as shown, it does not occur upon set sweep. The set sweep is represented by a loop 712 whose tail is shown by dashed lines.

Returning to FIG. 8, a block diagram of a phase change material memory device is shown, including waveform shaping and driving circuitry designed to provide the voltage and current levels needed to program the component cells of the device. The apparatus includes an array of memory cells 604 in which each cell 604 can be accessed by a unique pair of vertical conductors 614 and horizontal conductors 610. In this embodiment, horizontal conductor 610 allows control signals from timing logic 620 to be provided to each cell 604 to open and close the solid state switch. This solid state switch is in series with the phase change material, the other terminal of which is connected to a power source or a power return node. Thus, when the switch is closed, current is sourced or sinked through the phase change material. This programming current is provided through the vertical conductor 614. The sourcing or sinking of the programming current is performed by read circuit 618 or waveform shaping and drive circuit 608 depending on whether a write or read operation is performed. Read circuit 618 may be entirely conventional in the art.

The waveform shaping and driving circuit 608 is designed to provide the voltage and current levels needed to program the cells 604 in accordance with the first and second pulses described above, the second pulse having an overall triangular shape. The waveform shaping circuit can be implemented using conventional analog waveform shaping circuits such as integrator / lamp circuits, exponential and log circuits, as well as others. The waveform shaped pulses are then driven by conventional fanout circuitry to ensure that each cell 604 connected to the vertical conductor 614 has the desired level of current and voltage to achieve a set sweep. Receive.

Timing associated with the generation of the pulses may be determined by timing logic 620. Timing logic 620 provides digital control signals to waveform shaping and driving circuit 608 and readout circuit 618 so that the latter circuit measures the resistance of memory cell 604 (read operation) or selected memory cell. Provides reset and set pulses to 604 at the correct timing. Access to cells 604 may be organized in a row-by-row, random manner in which each cell can be accessed individually, or according to the higher level requirements of the memory system.

The memory device shown in FIG. 8 can be fabricated using a wide range of different fabrication processes, including a somewhat modified version of a conventional complementary metal oxide semiconductor (CMOS) logic fabrication process. The array of cells 604 and the waveform shaping and driving circuit 608 may be formed on the same integrated circuit (IC) die, thereby utilizing low cost system integration on a single chip.

9 is a block diagram of a portable application 904 of the phase change memory programming process described above. Phase change memory 908 operates in accordance with one embodiment of the programming process described above. The phase change memory 908 may include one or more integrated circuit dies each die having a memory array programmed in accordance with various embodiments of the above-described programming techniques of FIGS. 1-8. Such IC dies may be separate stand-alone memory devices arranged in modules such as conventional DRAM modules or may be integrated with other on-chip functions. In the latter embodiment, phase change memory 908 may be part of an I / O processor or microcontroller.

Application 904 may be, for example, a portable notebook computer, a digital still and / or video camera, a personal digital assitant (PDA), or a mobile (cellular) handheld telephone unit. In all such applications, the electronic system includes a processor 910 that uses the phase change memory 908 as a program memory for storing code and data for its execution. Alternatively, phase change memory 908 may be used as a mass storage device for nonvolatile storage of code and data. The portable application 904 communicates with other devices such as a personal computer or a network of computers via the I / O interface 914. This I / O interface 914 provides access to a computer peripheral bus, a high speed digital communication transmission line, or an antenna for unguided transmission. Communication between the processor and the phase change memory 908 and communication between the processor and the I / O interface 914 may be accomplished using conventional computer bus architectures.

The above-described components of the portable application 904 are powered by the battery 918 via the power supply bus 916. Because application 904 is typically battery powered, functional components including phase change memory 908 should be designed to provide the desired performance at low power consumption levels. In addition, due to the limited size of portable applications, the various components shown in FIG. 9, including the phase change memory 908, must provide relatively high density functionality. Of course, there are other non-portable applications for the phase change memory 908 that are not shown. This includes, for example, other computing devices that may benefit from nonvolatile memory devices such as large network servers or phase change memory.

By way of example, the phase change material may be Ge ₂ Sb ₂ Te ₅ . An exemplary pulse may have a peak current of the _reset I, I _reset is high enough in the array cells to be programmed to the reset state. The example pulse may have a falling edge that decreases from I _reset to zero current within about 200 nsec. However, this particular is only illustrative and the programming technique can work with a wide range of different phase change materials and pulse shapes with relatively slow falling edges.

In summary, various embodiments of phase change material memory programming techniques, called set sweeps, have been described. In the foregoing specification, the invention has been described with reference to specific exemplary embodiments. However, as will be provided in the appended claims, it will be apparent that various modifications and changes may be made without departing from the spirit and scope of the invention. For example, the phase change material may be a chalcogenide alloy or other suitable structural phase change material that functions as a programmable resistor. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims (22)

As a method of programming a memory device, Applying a first pulse to a component cell of said memory device, said cell having a structural phase change material for storing data of said cell, thereby leaving said material in a first state; And Thereafter, applying a second pulse to change the material from the first state to a different second state, the second pulse having an overall triangular shape How to include. The method of claim 1, The second pulse comprises a leading portion and a trailing portion, wherein the tip has a steeper slope than the trailing portion. The method of claim 2, Wherein the second pulse further comprises an intermediate portion between the tip portion and the trailing portion, wherein the intermediate portion has an essentially zero slope with respect to the tip portion and trailing portion. The method of claim 1, The first pulse is shaped to leave the material in a high resistance state, and the second pulse is shaped to leave the material in a low resistance state. The method of claim 4, wherein The magnitude and decay rate of the second pulse is such that, when the first and second pulses are applied, all constituent cells of the memory device are in the first state, regardless of material variation in the manufacturing process and device. Set to change from the second state to the second state. The method of claim 5, And said magnitude is high enough to cause said phase change material in at least some of said constituent cells of said device to reach an amorphous temperature if said second pulse is applied to said cells. The method of claim 6, The decay rate is slow enough so that the corresponding component cells that have reached the amorphous temperature are cooled at a sufficiently slow rate such that the phase change material in the cells changes from the first state to the second state. In a memory device, An array having a plurality of constituent cells, each cell having a structural phase change material for storing data of said cells; And Waveform shaping and driving circuitry coupled to provide voltage and current levels needed to program the plurality of configuration cells, the circuitry generating a first pulse to be applied to one of the plurality of configuration cells of the memory device; Leaving the material in a first state, and then generating a second pulse to be applied to the constituent cell to change the material from the first state to a second, different state, the second pulse being generally triangular Memory device having a shape. The method of claim 8, And the waveform shaping and driving circuit shapes the second pulse to have a leading end and a trailing end, the leading end having a steeper slope than the trailing end. The method of claim 8, The material may change from a high resistance state to a low resistance state in response, and the circuit may shape the first pulse to leave the material in the component cell in the high resistance state when applied and, when applied, the configuration. And shape the second pulse to leave the material in a cell in the low resistance state. The method of claim 10, The circuitry has a magnitude and attenuation rate at which all component cells of the memory device change from the first state to the second state, regardless of material variations in the manufacturing process and the device when the first and second pulses are applied. And a memory device configured to have the second pulse. The method of claim 11, The circuit shapes the second pulse to a size high enough that the phase change material in at least some of the constituent cells of the device can reach an amorphous temperature when the second pulse is applied to the corresponding cells. Memory device. The method of claim 12, The circuit may be configured such that the component cells that have reached the amorphous temperature are cooled at a sufficiently slow rate so that the phase change material in the cells is changed at a sufficiently low decay rate such that the phase change material in the cells changes from the first state to the second state. Memory device for shaping two pulses. The method of claim 8, And the array, the waveform shaping and the driving circuit are formed on the same integrated circuit (IC) die. As a method of programming a memory device, Applying a first pulse to a constituent cell of said memory device, said cell having a structural phase change material for storing data of said cell, thereby leaving said material in a first state; And Thereafter, applying a second pulse to the cell to change the material from the first state to a different second state, the second pulse wherein the signal level of the second pulse changes continuously over time. Having an active period, the cell is changed from the first state to the second state during the active period How to include. The method of claim 15, The signal level decreases continuously with time during the active period. The method of claim 15, The first pulse is shaped to leave the material in a high resistance state, and the second pulse is shaped to leave the material in a low resistance state. The method of claim 17, The magnitude and attenuation rate of the second pulse such that when the first and second pulses are applied, all constituent cells of the memory device change from the first state to the second state, regardless of material variation in the manufacturing process and device. How to set up. In a memory device, An array having a plurality of constituent cells, each cell having a structural phase change material for storing data of said cells; And Waveform shaping and driving circuitry coupled to provide the voltage and current levels needed to program the plurality of component cells. Including, The circuit generates a first pulse to be applied to one of the plurality of configuration cells of the memory device, leaving the material of the configuration cell in a first state, and then generating a second pulse to be applied to the configuration cell. Change the material from the first state to a different second state, wherein the second pulse has an active period in which the signal level of the second pulse continuously changes over time, and the constituent cell has the active period Memory device for changing from said first state to said second state. The method of claim 19, And the circuit shapes the second pulse such that its signal level decreases continuously with time during the active period. The method of claim 19, And the first pulse is shaped to leave the material in a high resistance state, and the second pulse is shaped to leave the material in a low resistance state. The method of claim 21, The magnitude and attenuation rate of the second pulse such that when the first and second pulses are applied, all constituent cells of the memory device change from the first state to the second state, regardless of material variation in the manufacturing process and device. Memory device to set up.

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