CN101271435A

CN101271435A - Method for access to external memory

Info

Publication number: CN101271435A
Application number: CNA2008101119811A
Authority: CN
Inventors: 林川
Original assignee: Vimicro Corp
Current assignee: JIANGSU DAHAI INTELLIGENT SYSTEM CO Ltd
Priority date: 2008-05-20
Filing date: 2008-05-20
Publication date: 2008-09-24
Anticipated expiration: 2028-05-20
Also published as: CN101271435B

Abstract

The present invention discloses a method for visiting an external storage device. The present invention displays the bandwidth priority attribute of the physical features of the external storage device by setting up and determines whether the visit authority of the current visit request is entitled or not according to the judgment of the bandwidth priority attribute of the physical features of the external storage device, thus increasing the efficiency of the device to visit the external storage device. The continuous data visit tries to be operated on the same line of the same block to the largest extent, thus greatly increasing the efficiency of continuous visit of the external storage device. When implementing the data transmission by the former request, the command and the address of the current visit request are parallelly sent out, thus reducing the time consumption of the transmission command delay; the time consumption of the bus switch is reduced by ensuring that the continuous data visit is writing or reading.

Description

Method for accessing external memory

Technical Field

The present invention relates to memory processing technologies, and more particularly, to a method for accessing an external memory.

Background

In a system on chip (SoC), a plurality of parallel processing functional modules such as a processor, a DMA, a hardware accelerator, and a peripheral device are included, and the functional modules access an off-chip memory such as an SDRAM and a DDR memory as required.

Because functional modules such as a processor, a DMA (direct memory access), a hardware accelerator and the like run independently, in practical application, the SDRAM (synchronous dynamic random access memory) can be accessed by a plurality of functional modules simultaneously, but only one read-write access is allowed to exist in the SDRAM at the same time according to the physical characteristics of the SDRAM. In order to solve the problem, the access to the external memory needs to grant the access authority of the external memory to the access request of a certain functional module through the bus arbitration unit according to a certain selection strategy, and temporarily suspend the access requests of other functional modules until all the access requests are processed. Obviously, the operation mode of the SDRAM with small system bandwidth affects the storage efficiency of the memory.

In a complex SoC chip, more and more parallel processing functional modules are provided, the operation processing capability of the functional modules is stronger and stronger, and the storage efficiency of the SDRAM memory and the system bandwidth gradually become the bottleneck of the SoC chip performance.

The SDRAM memory bus is divided into a data bus and an address bus, wherein the data bus is used for transmitting accessed data; the address bus is used to transmit the addresses of accesses and commands issued to the SDRAM memory. The access characteristics to the SDRAM memory are as follows: the SDRAM memory divides an accessed address into a block (Bank) address, a row (row) address and a column (column) address. When accessing the SDRAM memory, the block where the access address is located needs to be precharged (precharge) first, and then the row where the access address is located needs to be activated (active), and then the memory cell where the access address is located can be accessed according to the column address. That is, each time the SDRAM memory is accessed, if the bank is not precharged and the row is activated, the command process must be issued through the address bus, then the column address is issued through the address bus, and after a certain time, the data is transmitted through the data bus.

If the Bank where the access address is located is charged and not turned off, the block pre charge step may be omitted, thereby saving time for the block pre charge. Active time can be saved if the Bank where the access address is located is charged and the row where the address is located is activated.

Furthermore, the inputs and outputs of SDRAM memories typically multiplex the same data bus, i.e. the data bus is bidirectional. The SDRAM requires additional overhead in time to switch buses when performing the read and write operations at intervals.

In summary, due to the device physical characteristics of the SDRAM memory, the access delay to the SDRAM memory includes a block precharge, a line active and a bus bidirectional switching delay in addition to the SDRAM internal data transfer delay.

At present, a bus arbitration unit in a general SoC arbitrates a certain request from requests of a plurality of masters according to a sequence of the requests or a module priority of the masters and directly sends the certain request to an SDRAM memory, and a specific delay characteristic of the SDRAM memory is not considered. Under the conditions that more and more parallel functional modules are arranged in external equipment such as a complex SoC chip, and the operation processing capability of the functional modules is stronger and stronger, the low storage efficiency of the SDRAM memory directly and seriously reduces the access efficiency of the external equipment.

Disclosure of Invention

In view of the above, the main objective of the present invention is to provide a method for accessing an external memory, which can improve the efficiency of accessing the external memory by a device by improving the storage efficiency of the external memory itself.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a method of accessing an external memory, comprising:

A. setting a bandwidth priority attribute and a module priority attribute which reflect the self physical characteristics of an external memory; b, judging whether an access request meeting the bandwidth priority attribute exists in the current access request, and if so, entering the step B; otherwise, entering the step C;

B. setting access priority according to the bandwidth priority attribute, granting access request access authority with the highest access priority, and ending the process;

C. and setting access priority according to the module priority attribute, and granting the request access authority with the highest access priority.

The bandwidth priority attribute comprises:

activating an address attribute for indicating a block address at which the external memory has completed precharging and a row address at which it has been activated;

and/or a block address attribute for indicating a block address accessed by the last access request;

and/or a read-write state attribute used for representing the read-write state accessed by the last access request.

When the bandwidth priority attribute includes an activated address attribute, the method for determining in step a includes:

and judging whether a request which is the same as the block address pre-charged by the current external memory and the activated row address exists in the current access request, and if so, judging that the access request is the access request meeting the bandwidth priority attribute.

When the bandwidth priority attribute comprises a block address attribute, the judging method in the step A is as follows:

and judging whether a request different from the block address accessed last time exists in the current access request or not, and if so, judging that the access request is the access request meeting the bandwidth priority attribute.

When the bandwidth priority attribute includes a read-write state attribute, the method for determining in step a is as follows:

and judging whether a request with the same read-write state as the previous access exists in the current access request, and if so, judging that the access request is the access request meeting the bandwidth priority attribute.

The bandwidth priority attribute comprises an activated address attribute, a block address attribute and a read-write state attribute, and the judging method in the step A comprises the following steps:

A1. judging whether a request which is the same as the pre-charged block address and the activated row address of the current external memory exists in the current access request, if so, entering the step B; otherwise, go to step A2;

A2. judging whether a request different from the block address of the previous access exists in the current access request, and if so, entering the step B; otherwise go to step A3;

A3. b, judging whether a request with the same read-write state as the previous access exists in the current access request, and if so, entering the step B; otherwise, entering the step C.

The step B specifically comprises the following steps: and setting the access request meeting the bandwidth priority attribute as the highest access priority to obtain the access authority.

The step C specifically comprises the following steps: and setting the access request with the highest module priority as the highest access priority to obtain the access authority.

The method further comprises the following steps: and storing the access request which cannot obtain the access right currently.

The storage method comprises the following steps: adjusting and storing the storage priority for each access request which cannot obtain the access authority;

and when the external memory is idle, selecting the access request with the highest storage priority to obtain the access authority according to the adjusted storage priority of each access request.

The storage priority is set in a storage priority register;

the storage priority register comprises a same block and a same row domain, different fast domains, a same read-write state domain and a module priority domain; wherein,

a same block and same row field for indicating whether the access request is the same as the currently precharged block address of the external memory and the activated row address;

different block fields for indicating whether the block address of the access request is different from the block address of the previous access;

and the same read-write state field is used for indicating whether the read-write state of the access request is the same as the read-write state of the previous access.

And when a plurality of storage priorities are equal and are all in the current highest priority, selecting one access request from the storage priorities through the hardware connection position to obtain the access right.

According to the technical scheme, the bandwidth priority attribute which embodies the physical characteristics of the external memory is set, and whether the access authority of the current access request is given or not is judged and determined according to the bandwidth priority attribute which embodies the physical characteristics of the external memory, so that the efficiency of the device for accessing the external memory is improved: continuous data access is made to fall on the same row of the same block as much as possible, and the efficiency of continuously accessing the external memory is greatly improved; when the last request executes data transmission, the command and the address of the current access request are sent out in parallel, and the command delay time overhead of transmission is reduced; by ensuring that consecutive data accesses are both read or write, the time overhead of bus switching is reduced.

Drawings

FIG. 1 is a flow chart of the present invention for accessing external memory;

FIG. 2 is a flow diagram of an embodiment of the present invention for accessing external memory.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and preferred embodiments.

The bus arbitration unit stores the bandwidth priority attributes of the precharged block, the activated row, the block address of the previous access, the read-write state of the previous access and the like of the current external memory at any time. These bandwidth priority attributes embody the physical characteristics of the external memory itself. For convenience of description, the following description will be made taking the external memory as an SDRAM as an example.

The block precharged by the current SDRAM means that the current SDRAM block is in a state of being precharged. If the current access request is to access the block, the pre-charge time overhead can be saved;

the activated row of the current SDRAM represents that the row of the current SDRAM is in an activated state, and the block in which the row is located is also in a state of being completely precharged. If the current access request is to access the row, the pre-charge time and row activation time overhead can be saved;

the block address of the previous access indicates the block address of the last access request. If the block address accessed by the current access request is different from the block address accessed by the previous request, the command and the address of the current access request can be issued in parallel when the data transmission is executed by the previous request, so that the time overhead of precharging time, row activation and address issuing can be saved;

the read-write state of the previous access indicates that the previous access request is a read operation or a write operation. If the read-write requirement of the current access request is the same as the last access request, i.e. the last access request is a read operation, then the current access request is also required to be a read operation. The time overhead of the bidirectional bus switch can be saved.

In addition, the bus arbitration unit also sets a module priority attribute which is used for representing the priority of the module, for example, when executing the operation task, the module priority attribute of the processor can be set as the highest priority; when data storage is performed, the module priority attribute of the peripheral may be set to the highest priority or the like, and the module priority attribute may be configurable by software.

It should be noted that the bandwidth priority attribute may be recorded in only one record, or any combination of records, or all records.

FIG. 1 is a flow chart of accessing external memory according to the present invention, as shown in FIG. 1, including the following steps:

step 100: setting a bandwidth priority attribute and a module priority attribute.

In the bus arbitration unit, each function module corresponding to each access external memory has a respective configuration register, and the module priority attribute of each function module can be configured through software;

in addition, a set of Active Address (Active Address) register, a block Address (Last Bank) register and a read-Write state (Last Write) register are preset in the bus arbitration unit, and are respectively used for storing bandwidth priority attributes representing the physical characteristics of the external memory.

The number of registers in a group of activated address registers is the same as the number of blocks of an external memory, each activated address register is used for storing a block address of a certain external memory such as SDRAM, which is subjected to pre-charging, and an activated row address of the external memory, and a bandwidth priority attribute stored in the activated address register is referred to as an activated address attribute;

the block address register is used for storing the block address accessed by the last access request; the bandwidth priority attribute stored in the block address register is referred to herein as the block address attribute;

a read-write state register for storing the read-write state accessed by the last access request, wherein the bandwidth priority attribute stored in the read-write state register is referred to as the read-write state attribute;

step 101: judging whether the current access request has an access request meeting the bandwidth priority attribute, and if so, entering step 102; otherwise step 103 is entered.

The method for judging whether the bandwidth priority attribute is met comprises the following steps:

(1) firstly, judging whether a request which is the same as a pre-charged block address and an activated row address of a current external memory such as SDRAM exists in a current access request, if so, judging that the request is an access request meeting the bandwidth priority attribute;

(2) if the condition (1) is not met, judging whether a request different from the block address accessed last time exists in the current access request, if so, judging that the request is the access request meeting the bandwidth priority attribute;

(3) and if the condition (1) and the condition (2) are not met, judging whether a request with the same read-write state as the previous access exists in the current access request, and if so, judging that the request is the access request meeting the bandwidth priority attribute.

It is easy to see from the implementation of point (1) in step 101 that the method of the present invention makes the continuous data access fall on the same row of the same block as much as possible, and greatly improves the efficiency of continuously accessing the external memory such as SDRAM.

As is readily apparent from the implementation of point (2), when the block address accessed by the current access request is different from the previous request, by activating the block and row of the next access request in advance, i.e., issuing the command and address of the current access request in parallel, when the data transmission is performed by the previous request, the time overhead of precharging time, row activation and address issuing, i.e., the command delay time overhead of transmission, is reduced.

As is readily apparent from the implementation of point (3), the consecutive data accesses are all read or write, and the time overhead of bus switching is reduced.

Step 102: and setting access priority according to the bandwidth priority attribute, granting the request access authority with the highest access priority, and ending the process.

And setting the access request meeting the bandwidth priority attribute in the step 101 as the highest access priority, and obtaining the access authority, namely applying the request for accessing the SDRAM by using the standing horse.

Step 103: and setting an access priority according to the module priority attribute, and granting a request access authority with the highest access priority, specifically, setting the access request with the highest module priority as the highest access priority to obtain the access authority.

And if the conditions of (1) to (3) in the step 101 are not met, selecting the access request with the highest module priority to obtain the access authority according to the module priority attribute, and applying for accessing the SDRAM.

Other access requests that do not satisfy the bandwidth priority attribute and the module priority attribute are stored in the bus arbitration unit, for implementation see below.

It should be emphasized that, in step 101, as long as any condition judgment exists, the purpose of the present invention of improving the storage efficiency of the external memory itself and increasing the efficiency of the device accessing the external memory can be achieved, and any combination of the judgment conditions in step 101 can also achieve the purpose of the present invention, and when all three judgment conditions in step 101 exist, the best effect can be achieved.

Fig. 2 is a flowchart of an embodiment of accessing an external memory according to the present invention, assuming that the external memory is an SDRAM and the bandwidth priority attribute includes a block precharged by the current SDRAM, an activated row, a block address of a previous access, and a read/write status of the previous access, as shown in fig. 2, including the following steps:

step 200: judging whether a request with the same address as the pre-charging block and the activated row exists in the current access request, if so, meeting the condition, and entering a step 203; otherwise, step 204 is entered.

Step 201: judging whether a request which is different from the block address accessed last time exists in the current access request, if so, meeting the condition, and entering a step 203; otherwise, step 204 is entered.

Step 202: judging whether a request with the same read-write state as the previous access exists in the current access request, if so, meeting the conditions, and entering step 203; otherwise, step 204 is entered.

Step 203: and setting the access request meeting the conditions as the highest access priority, granting the access request access authority, and ending the process.

Step 204: and granting the access authority according to the module priority of the module of the access request.

The invention improves the efficiency of the device accessing the external memory by setting the bandwidth priority attribute reflecting the physical characteristics of the external memory and judging whether to give the access authority of the current access request according to the bandwidth priority attribute: continuous data access is made to fall on the same row of the same block as much as possible, and the efficiency of continuously accessing the external memory is greatly improved; when the last request executes data transmission, the command and the address of the current access request are sent out in parallel, and the command delay time overhead of transmission is reduced; by ensuring that consecutive data accesses are both read or write, the time overhead of bus switching is reduced.

If the access request of the functional module can not obtain the access right at the current moment, the request which can not obtain the access right at this time is stored in the bus arbitration unit so as to issue an application at the next arbitration. The storage priority is adjusted and queued according to the following method:

the priority of each module is represented by a multi-bit storage priority register, and the larger the value of the register is, the larger the priority of the register is represented. The priority is composed of 4 fields, namely, the same block and the same row field, the different fast fields, the same read-write state field and the module priority field, as shown in table 1.

Same block and same line

Different blocks

Simultaneous reading and writing state

Module priority

TABLE 1

The same-block same-row field is used for indicating whether the access request is the same as the currently precharged block address of the external memory and the activated row address, when the block address and the row address of the access request are stored in a certain activated address register, the field is 1, otherwise, the field is 0. The field is the highest bit of the adjusted storage priority, and when the field is 1, the access request has the highest adjusted storage priority.

And different block fields for indicating whether the block address of the access request is different from the block address of the previous access, wherein the field is 1 when the block address of the access request is different from the value stored in the block address register, and is 0 otherwise. Different block domains are at the second highest position of the adjusted priority, and when the same block and the same row domain of all the access requests are the same and the different block domain of one access request is 1, the storage priority of the access request after adjustment is the highest.

And the same read-write state field is used for indicating whether the read-write state of the access request is the same as the read-write state of the previous access, when the read-write state of the access request is the same as the value stored in the read-write state register, the field is 1, and otherwise, the field is 0. And the same read-write state field is at the third highest position of the adjusted priority, and when the values of the same block, the same row field and different block fields of all the access requests are the same, and the same read-write state field of a certain access request is 1, the storage priority of the access request after adjustment is the highest.

And the module priority field is used for representing the priority of the module, and the larger the value of the module priority field is, the higher the module priority of the module is. Under the condition that the same block and the same row domain, the different block domains and the same read-write state domain are the same, the larger the module priority domain value of the module where the access request is located is, the highest priority of the access request of the module is, and the highest storage priority of the module after the access request corresponding to the module is adjusted is.

The bus arbitration unit does not process new access requests during the access period of the external memory, when the external memory is idle, arbitration is performed according to the storage priority of each adjusted access request, the access request of the module with the highest value of the storage priority register obtains access authority, if the storage priorities of a plurality of modules are equal and are all in the current highest priority, one of the modules is selected through the hardware connecting line position, and the modules can be set to have higher priority under the same storage priority according to the bandwidth use condition, the access frequency of the external memory and the like. For example, for a CPU, a decoder, and a peripheral device such as a USB in the SoC, for a video processing application, the decoder needs the largest bandwidth and will often access an external memory, and the next CPU compares the smallest bandwidth with the USB, so that the priority of the decoder acquiring the access right is the highest, the next CPU compares the smallest bandwidth with the USB, and finally the USB may be preset under the condition that the priorities of the CPU, the decoder, and the USB are the same.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements and the like that are within the spirit and principle of the present invention should be included in the present invention.

Claims

1. A method of accessing an external memory, comprising:

2. The method of claim 1, wherein the bandwidth priority attribute comprises:

an activation address attribute for indicating a block address at which the external memory has completed precharging, and a row address at which it has been activated;

3. The method according to claim 1, wherein when the bandwidth priority attribute comprises an active address attribute, the method for determining in step a is:

4. The method of claim 1, wherein when the bandwidth priority attribute comprises a block address attribute, the determining in step a is performed by:

5. The method according to claim, wherein when the bandwidth priority attribute includes a read/write status attribute, the determining in step a is performed by:

6. The method according to claim 1, wherein the bandwidth priority attributes include an active address attribute, a block address attribute, and a read/write status attribute, and the method of determining in step a is:

7. The method according to claim 1, 3, 4, 5 or 6, wherein the step B specifically comprises: and setting the access request meeting the bandwidth priority attribute as the highest access priority to obtain the access authority.

8. The method according to claim 1, 3, 4, 5 or 6, characterized in that said step C comprises in particular: and setting the access request with the highest module priority as the highest access priority to obtain the access authority.

9. The method of claim 1, further comprising: and storing the access request which cannot obtain the access right currently.

10. The method of claim 9, wherein the saving is performed by: adjusting and storing the storage priority for each access request which cannot obtain the access authority;

11. The method of claim 10, wherein the storage priority is set in a storage priority register;

the storage priority register comprises a same-block same-row domain, a different-block domain, a same read-write state domain and a module priority domain; wherein,

12. The method of claim 10, wherein when there are a plurality of said storage priority levels that are equal and all are at the current highest priority level, selecting one of the access requests via the hardwire location to obtain the access right.