CN113064550B - Control device and control method for shortening external memory access time - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention discloses a control device and a control method for shortening the access time of an external memory, according to the method, the requirement on the storage space and the caching frequency are reduced by caching the data of the discontinuous addresses, so that the control of cost and power consumption is facilitated. Meanwhile, because the data at the discontinuous address is cached, the access time of the external memory can be shortened, the bandwidth reduction problem caused by the transmission of data such as command words, read addresses and the like is eliminated, the equivalent effective bandwidth of the read-write host for reading the external memory can be increased to 100%, the reading speed is stable, the system performance is improved, and the method has obvious advantages in the scene of strict requirement on program running delay.
Description
Technical Field
The invention relates to the field of memories, in particular to a control device and a control method for shortening external memory access time.
Background
Along with the development of the internet of things and artificial intelligence technology, the MCU on the terminal product is gradually developed towards the directions of high computational power and large program storage space, and a memory with a larger space in the MCU is not a good choice from the aspects of cost and flexibility, so that an external memory is generally used. Because of the limitation of packaging, the external memory usually selects an SPI flash of a serial interface, the interface can reach higher bandwidth under the condition of continuous reading, but when the read data is discontinuous, a command word and a read address are required to be sent first, then the program data can be acquired, and the read-write host is in a state of waiting for data and is suspended during the period, so that the operation efficiency of the system is reduced.
Disclosure of Invention
In order to solve the problems, the invention provides a control device and a control method for shortening the access time of an external memory, which greatly improve the operation efficiency of a system. The specific technical scheme of the invention is as follows:
a control method for shortening an external memory access time, the method comprising the steps of: s1, an acceleration control module receives an access request of a read-write host, wherein the access request comprises an access address; s2, the acceleration control module detects whether the access address is continuous with the last access address, if so, the data is read through the external storage controller and returned to the read-write host, and if not, S3 is entered; s3, the acceleration control module detects whether the data corresponding to the access address is stored in the acceleration cache memory, if yes, the data is read through the acceleration cache memory, the data of the next continuous address is read and set, then the data is returned to the read-write host, and if not, S4 is entered; s4, the acceleration control module reads data through the external storage controller and returns the data to the read-write host, and simultaneously the access address and the corresponding data are stored in a storage unit of the acceleration cache memory, so that the data at the discontinuous address can be quickly read from the acceleration cache memory next time. The control method of the invention utilizes the acceleration cache memory to cache the data at the discontinuous address, thereby reducing the requirement on the storage space and the cache frequency, and being beneficial to controlling the cost and the power consumption; meanwhile, because the data at the discontinuous addresses are cached, the access time of the external memory can be shortened, the problem of bandwidth reduction caused by data transmission is eliminated, the equivalent effective bandwidth of the external memory read by the read-write host can be increased to 100%, the reading speed is stable, the system performance is improved, and the method has obvious advantages in the scene of strict program running delay requirements.
Further, in the method for detecting whether the access address and the last access address are consecutive in step S2, the access address and the last access address are compared, and if the value of the access address is increased by a preset step value compared with the value of the last access address, the access address and the last access address are consecutive. If the addresses are judged to be continuous, the data can be directly read from the external memory, so that the speed is high and the cache frequency is reduced.
Further, in the step S2, if it is detected that the last access address does not exist, the acceleration control module controls the external memory controller to send a command word and a read address to the external memory, reads data from the external memory and returns the data to the read-write host, where the read-write address is the access address.
Further, in the step S3, the method for detecting whether the data corresponding to the access address is stored in the acceleration cache memory is to compare the access address with the address stored in the acceleration cache memory, and if the addresses with the same value exist, it indicates that the data corresponding to the access address is stored. If the required data is stored in the cache memory, the access request can be completed quickly.
Further, in the method for performing the reading setting of the data of the next continuous address in step S3, the external storage controller sends the command word and the reading address to the external storage while accelerating the reading of the data by the cache memory, so as to save the setting time of the next access request, wherein the next access address in the next access request is continuous with the access address. The command word and the read address are sent in advance, so that the setting time of the next access request can be saved, and the data reading speed is improved.
Further, in step S4, before storing the access address and the corresponding data in a storage unit of the cache memory, it is detected whether the cache memory has an empty storage unit, if so, the access address and the corresponding data are stored in the empty storage unit and the effective identification segment is updated, if not, an algorithm is used to find a replacement storage unit, and then the access address and the corresponding data are stored and the effective identification segment is updated. The data at the discontinuous address is stored in the storage unit of the acceleration cache memory, and the data is not required to be read through an external memory next time, so that the access time of the external memory is shortened, the bandwidth reduction problem caused by the transmission of data such as command words, read addresses and the like is eliminated, and the system performance is improved.
Further, the algorithm for finding the replaced storage unit is a replacement algorithm.
The control device for shortening the access time of the external memory comprises an external memory, an external memory controller, an acceleration control module, an acceleration cache memory and a read-write host, wherein the external memory is connected with the external memory controller and used for storing program codes; the external storage controller is connected with the acceleration control module and used for controlling access to the external memory; the acceleration control module is connected with the acceleration cache memory and the read-write host and is used for receiving a data access request of the read-write host and controlling the external storage controller and the acceleration cache memory to work according to the data access request; the acceleration cache memory is used for caching data at discontinuous addresses requested by the read-write host; and the read-write host is used for initiating the access request. The control device utilizes the acceleration cache memory to cache the data at the discontinuous address, so that the requirement on the storage space and the cache frequency can be reduced, and the control of the cost and the power consumption is facilitated; meanwhile, because the data at the discontinuous addresses are cached, the access time of the external memory can be shortened, the problem of bandwidth reduction caused by data transmission is eliminated, the equivalent effective bandwidth of the external memory read by the read-write host can be increased to 100%, the reading speed is stable, the system performance is improved, and the method has obvious advantages in the scene of strict program running delay requirements.
Further, the acceleration cache memory comprises a plurality of storage units for storing data at the non-continuous addresses, wherein the data at the non-continuous addresses comprises a group of continuous data with preset length. The storage unit is only used for storing data at the discontinuous addresses, so that the requirement on the storage space and the caching frequency are reduced, and the control of the cost and the power consumption is facilitated.
Further, the storage unit is composed of an address section, a data section and an effective identification section, wherein the address section is used for storing the first address of a group of continuous data with preset length at discontinuous addresses read from an external memory; a data section for storing data at the discontinuous address read out from the external memory; and the valid identification section is used for storing an identification indicating whether the data in the acceleration cache memory is valid or not.
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Fig. 1 is a schematic diagram of a control apparatus for shortening external memory access time according to an embodiment of the invention.
FIG. 2 is a flow chart of a control method for shortening external memory access time according to an embodiment of the invention.
Detailed Description
The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention. It should be understood that the following detailed description is merely illustrative of the invention, and is not intended to limit the invention.
In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the embodiments.
Referring to fig. 1, a control apparatus for shortening an external memory access time includes an external memory, an external memory controller, an acceleration control module, an acceleration cache memory, and a read-write host. The external memory is used for storing program codes, and the read-write host machine can acquire the program codes from the external memory when in operation. Taking GD25LT256E (ultra-high speed 4 channel SPI NOR Flash product) as an example, when reading data in single line mode, the read-write host needs to send an 8bit "command word" first, then send a 24bit "read address", and then start receiving data. The external memory controller is responsible for directly performing access control on the external memory. The acceleration control module is a core component of the control device and is used for receiving a data access request of a read-write host and controlling an external storage controller and an acceleration cache memory to work according to the data access request. The acceleration cache memory is used for caching data at discontinuous addresses requested by the read-write host. Specifically, the data at the discontinuous addresses are stored in a storage unit of the acceleration cache memory, and the storage unit consists of an address section, a data section and a valid identification section. Wherein the address field is used for storing a head address of a set of continuous data of a preset length at discontinuous addresses read from the external memory. It should be noted that, in order to facilitate management of the acceleration cache memory and achieve optimal acceleration performance, the acceleration cache memory will cache a set of continuous data with a preset length into the data segment at a time. The length of the continuous data depends on the number of clock cycles taken up in the links of "command word", "read address", etc. and the bus bit width of the system when accessing the external memory. Still taking GD25LT256E as an example, when reading data, an 8-bit "command word" and a 24-bit "read address" need to be sent, which is 32 bits in total, and the bus bit width of the system is 32 bits. The data segment should buffer 4 bytes (or 32 bits, 1 byte equals 8 bits) of data at this time, so that optimal acceleration performance can be achieved. The length of the continuous data can be designed to be configured through a register so as to adapt to different external memory time sequences, and the cached data can be dynamically updated when the program runs, or can be fixedly configured according to the requirement. If a dynamic update method is used, acceleration may be performed on different schemes, but the effect of acceleration may be variable and uncertain due to storage space limitations. If the method of fixed configuration is adopted, after the firmware is determined, fixed acceleration can be realized on the places needing acceleration. Applications with stringent requirements on program run time may employ dynamic methods, but fixed configuration methods are preferred. After the data is stored in the data segment, the valid identification segment is updated, and when the data is valid, the identification is "1", and when the data is invalid, the identification is "0". The read-write host is an initiating module of the read-write request, and the control device needs to receive the request initiated by the read-write host to start working.
Referring to fig. 2, a control method for shortening an external memory access time, the method comprising the steps of:
in step S1, the acceleration control module receives an access request from the read-write host, where the access request includes an access address. For convenience of description, the access address is denoted as ADDR. In this embodiment, one address corresponds to one byte.
And S2, the acceleration control module detects whether the access address ADDR is continuous with the last access address, if so, the data is read by the external storage controller and returned to the read-write host, and if not, the step S3 is carried out. After receiving an access address ADDR of a read-write host, the acceleration control module compares the size of the access address ADDR with the size of a last access address first, and when the size of the access address ADDR is increased by a preset step value compared with the size of the last access address, the access address ADDR is considered to be continuous with the last access address. At this time, the data corresponding to the access address is directly read out from the external memory through the external memory controller and returned to the read-write host. The preset step size value is determined by the system bit width, and is, for example, GD25LT256E, and is 4, because the data length cached in the acceleration cache memory is 4 bytes. It should be noted that, when the access addresses are consecutive, it is not necessary to send "command word" and "read address" before reading data from the external memory, so reading data directly through the external memory controller does not degrade the system performance. The opposite is the case when the access addresses are discontinuous, so the control device and the control method for shortening the access time of the external memory are provided to solve the problem of system performance reduction when the access addresses are discontinuous.
And S3, the acceleration control module detects whether the data corresponding to the access address is stored in the acceleration cache memory, if so, the data is read through the acceleration cache memory and returned to the read-write host, and the data is read and set at the same time of the data reading, and if not, the step S4 is carried out. When the access address ADDR is found to be discontinuous with the last access address, the acceleration control module attempts to read the requested data from the acceleration cache memory in order to eliminate the problem of system bandwidth degradation caused by the transmission of the command word and the read address. Firstly, whether the request data is stored in the acceleration cache memory is detected, if the acceleration cache memory has a stored address with the same size as the access address, the request data can be directly read from the acceleration cache memory, so that the access time of an external memory is shortened, and the system performance is improved. After the requested data is read, the data is returned to the read-write host. It should be noted that, while reading the requested data, the acceleration control module will start the external storage controller to send the "command word" and the "read address" to the external memory, so as to save the setup time of the next access request. In this way, if the address where the data requested by the next read/write host is located is continuous with the current access address, the external storage controller can directly return the data to the read/write host.
And S4, the acceleration control module reads data through the external storage controller and returns the data to the read-write host, and simultaneously stores the access address and the corresponding data into a storage unit of the acceleration cache memory so as to quickly read the data at the discontinuous address from the acceleration cache memory next time. When the access addresses are discontinuous and the acceleration cache memory has no needed data, the acceleration control module reads the data through the external storage controller. It is then inevitably necessary to send "command words" and "read addresses" to the external memory. Although the system performance is reduced, after the data is read, the acceleration control module stores the access address and the corresponding data into the acceleration cache memory. If a data access request at the same non-contiguous address is encountered next, it can be quickly read from the acceleration cache memory and returned. Also, since only data at non-contiguous addresses is cached, rather than all data, the cache size requirements for the acceleration cache memory are low (the example code for a program jump will not be very high in the overall program). Thus, the update frequency of the cache is also reduced, which is advantageous in controlling power consumption, since it is possible to update the cache only if the cache is checked at the time of address hopping. It should be noted that, before storing the access address and the corresponding data into the cache memory, it is necessary to detect whether the cache memory has a free memory location. If there are unused memory locations, a new memory location is allocated and stored in the address field, and then when the external memory controller requests data, the external memory controller returns the data to the read-write host while storing the data in the memory location where the access address ADDR is located. As mentioned above, taking GD25LT256E as an example, the data segment should buffer 4 bytes of data to achieve optimal acceleration performance. Therefore, the total number of data stored in the memory cells is 4, and the corresponding addresses are ADDR, addr+1, addr+2, and addr+3, respectively. In this embodiment, only the first address of the set of consecutive data, i.e. 4 data, is stored in the memory location where the access address ADDR is located. And after the storage is successful, updating the effective identification of the effective identification section to be 1. If the storage unit is used up, the storage unit to be replaced is found through a replacement algorithm, the identification of the storage unit is cleared, then the access address ADDR and corresponding data are stored in the replaced storage unit, and then the effective identification section is updated.
In summary, the method for caching the data at the discontinuous address shortens the average access time of the external memory and eliminates the problem of bandwidth reduction caused by the transmission of the command word and the read address. This can increase the effective bandwidth of the read-write host to 100%, in other words, the read-write host can continuously read the desired data. The key points are as follows: 1, when the access address is discontinuous with the last access address, the data can be directly read from the acceleration cache memory (assuming that the data is stored), so that the time for sending a command word and a read address is saved; 2, the external storage controller can read the data of the next continuous address while reading the data of the discontinuous address from the acceleration cache memory, namely, send the command word and the read address in advance, so that the setting time of the next access request is saved. From the perspective of the read-write host, the read-write host can continuously read the required data without interruption, and the suspension is caused without waiting in the middle, so that the operation efficiency of the system is affected.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A control method for shortening an external memory access time, the method comprising the steps of:
S1, an acceleration control module receives an access request of a read-write host, wherein the access request comprises an access address;
S2, the acceleration control module detects whether the access address is continuous with the last access address, if so, the data is read through the external storage controller and returned to the read-write host, and if not, S3 is entered;
S3, the acceleration control module detects whether the data corresponding to the access address is stored in the acceleration cache memory, if yes, the data corresponding to the access address is read through the acceleration cache memory, the data corresponding to the access address is read, meanwhile, the data of the next continuous address is read, then the data corresponding to the access address is returned to the read-write host, and if not, S4 is entered;
S4, the acceleration control module reads data through the external storage controller and returns the data to the read-write host, and simultaneously the access address and the corresponding data are stored in a storage unit of the acceleration cache memory, so that the data at the discontinuous address can be quickly read from the acceleration cache memory next time.
2. The method of claim 1, wherein the step S2 of detecting whether the access address is consecutive with the last access address is performed by comparing the access address with the last access address, and if the value of the access address is greater than the value of the last access address by a preset step value, the access address is consecutive with the last access address.
3. The method according to claim 1, wherein in step S2, if it is detected that the last access address is not present, the acceleration control module controls the external memory controller to send a command word and a read address to the external memory, reads data from the external memory and returns the read address to the read/write host, wherein the read address is the access address.
4. The method of claim 1, wherein the step S3 of detecting whether the data corresponding to the access address is stored in the cache memory is performed by comparing the access address with the address stored in the cache memory, and if the addresses with the same value are stored, the data corresponding to the access address is stored.
5. The method of claim 1, wherein the method of performing the read setting of the data of the next sequential address in step S3 is that the external memory controller sends the command word and the read address to the external memory while accelerating the data read of the cache memory, saving the setting time of the next access request, wherein the next access address in the next access request is continuous with the access address.
6. The method according to claim 1, wherein in step S4, before storing the access address and the corresponding data in a memory unit of the cache memory, it is detected whether the cache memory has a free memory unit, if so, the access address and the corresponding data are stored in the free memory unit and the effective identification segment is updated, and if not, an algorithm is used to find a replaced memory unit, and then the access address and the corresponding data are stored and the effective identification segment is updated.
7. The method of claim 6, wherein the algorithm for finding the replaced memory cells is a replacement algorithm.
8. A control device for shortening external memory access time, characterized in that the control device performs the control method for shortening external memory access time according to any one of claims 1 to 7, the control device comprises an external memory, an external memory controller, an acceleration control module, an acceleration cache memory, and a read-write host, wherein,
An external memory connected with the external memory controller for storing program codes;
The external storage controller is connected with the acceleration control module and used for controlling access to the external memory;
The acceleration control module is connected with the acceleration cache memory and the read-write host and is used for receiving a data access request of the read-write host and controlling the external storage controller and the acceleration cache memory to work according to the data access request;
The acceleration cache memory is used for caching data at discontinuous addresses requested by the read-write host;
and the read-write host is used for initiating the access request.
9. The control device for shortening an external memory access time according to claim 8, wherein the acceleration cache memory comprises a plurality of memory cells for storing data at the non-consecutive addresses, the data at the non-consecutive addresses comprising a set of consecutive data of a predetermined length.
10. The control device for shortening an external memory access time according to claim 9, wherein the memory unit is composed of an address section, a data section and a valid identification section, wherein,
An address section for storing a head address of a set of continuous data of a preset length at discontinuous addresses read out from the external memory;
A data section for storing data at the discontinuous address read out from the external memory;
and the valid identification section is used for storing an identification indicating whether the data in the acceleration cache memory is valid or not.
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| CN101271435A (en) * | 2008-05-20 | 2008-09-24 | 北京中星微电子有限公司 | Method for access to external memory |
| CN102171649A (en) * | 2008-12-22 | 2011-08-31 | 英特尔公司 | Method and system for queuing transfers of multiple non-contiguous address ranges with a single command |
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