CN101258100B - Microelectromechanical systems (MEMS) device including a superlattice and associated methods - Google Patents
Microelectromechanical systems (MEMS) device including a superlattice and associated methods Download PDFInfo
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- CN101258100B CN101258100B CN2006800188160A CN200680018816A CN101258100B CN 101258100 B CN101258100 B CN 101258100B CN 2006800188160 A CN2006800188160 A CN 2006800188160A CN 200680018816 A CN200680018816 A CN 200680018816A CN 101258100 B CN101258100 B CN 101258100B
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Abstract
A microelectromechanical system (MEMS) device may include a substrate and at least one movable member supported by the substrate. At least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Description
Technical field
The present invention relates to semiconductor applications, more specifically, the present invention relates to comprise the semiconductor device and the correlation technique of superlattice.
Background technology
Existing many people propose some structures and the technological performance that improves semiconductor device, for example through improving the mobility of electric charge carrier.For example, people's such as Currie U.S. Patent application 2003/0057416 discloses the strained material layer of silicon, silicon-germanium and relaxed silicon, and it also comprises the free from admixture district, then will cause performance to reduce if not the free from admixture district.The biaxial strain that in upper silicon layer, obtains has changed the mobility of electric charge carrier, and obtains more speed and/or more lower powered device.A kind of CMOS inverter that is the basis with similar strained silicon technology is equally disclosed in people's such as Fitzgerald the application of U.S. Patent No. 2003/0034529.
The United States Patent (USP) 6472685B2 of Takagi discloses a kind of semiconductor device that comprises silicon layer and carbon-coating, and said carbon-coating is clipped between the silicon layer, thereby the conduction band of second silicon layer and valence band receive elongation strain.Be applied in the electronics that the electric field to gate electrode brings out and be limited in second silicon layer, therefore can obtain having the more n-channel mosfet of high mobility with littler effective mass.
People's such as Ishibashi United States Patent (USP) 4937204 discloses a kind of superlattice, wherein comprises multilayer (being less than 8 individual layers) structure of a part or binary or Binary compound semiconductor layer, with the mode epitaxial growth that replaces.The main current flow direction is vertical with each layer plane in the superlattice.
People's such as Wang United States Patent (USP) 5375119 discloses a kind of Si-Ge short period superlattice, and it disperses the mobility that reaches higher through reducing alloy in superlattice.In these class methods; The United States Patent (USP) 5683934 of Candelaria discloses the MOSFET that a kind of mobility improves; Its channel layer comprises silicon alloy and second kind of material, and this second kind of material substitutes appearance can make channel layer be in tensile stress with certain percentage in silicon crystal lattice.
The United States Patent (USP) 5216262 of Tsu discloses a kind of SQW that comprises two barrier layers district and be clipped in the epitaxially grown semiconductor lamella between the district of barrier layer (quantum well) structure.Each barrier layer district by thickness usually at two SiO that replace to six individual layers
2/ Si individual layer is formed, and also accompanies the part of one section thick a lot of silicon between the district of barrier layer.
By " Applied Physics and Materials Science and Engineering " (Applied Physics and Materials Science) in online delivering on September 6,2000 (391-402 page or leaf), Tsu writes is entitled as in " phenomenon in the silicon nanostructure device " (" Phenomena in silicon nanostructure devices ") literary composition, discloses the semiconductor-atom superlattice (SAS) of a kind of silicon and oxygen.Disclosed Si/O superlattice can be used for silicon quantum and light emitting devices.Disclosed especially and how to have constructed and tested a kind of green electroluminescent diode structure.Direction of current flow in this diode structure is vertical, promptly perpendicular to the aspect of SAS.Disclosed SAS can comprise by the semiconductor layer that impurity is separated that is absorbed like oxygen atom and CO molecule etc.The silicon that is absorbed outside the individual layer to be generated at oxygen is described as the extension with suitable fabricating low-defect-density.A SAS structure comprises the thick silicon area of 1.1nm with about 8 silicon atom layers, and the thickness of the silicon part twice of thickness for this reason in another structure.One piece of people such as Luo is published in " Acta Physica Sinica " (Physical Review Letters); The 89th volume the 7th phase (on August 12nd, 2002), the light emission SAS structure of Tsu further discussed in the article that is entitled as " Chemical Design of Direct-Gap Light-Emitting Silicon ".
The disclosed International Patent Application WO 02/103767A1 of Wang, Tsu and Lofgren discloses a kind of thin silicon and the barrier layer structure piece (barrier building block) of oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen, and it can be with reducing more than 4 one magnitude through the electric current of vertical current through lattice.Insulating barrier/barrier layer allows on insulating barrier, then to deposit the epitaxial silicon of low defective.
People's such as Mears disclosed British Patent Application 2347520 discloses aperiodicity optical band gap (APBG) structural principle and can be applicable to the electronic band gap engineering.Specifically, this application discloses material parameter, for example can regulate and obtain the new aperiodicity material with required band structure characteristic with the position of minimum value, effective mass etc.This application also discloses other parameter, and for example conductivity, thermal conductivity and dielectric constant or magnetic permeability also can be designed in the material and go.
Summary of the invention
A kind of Micro Electro Mechanical System (MEMS) device can comprise substrate and by at least one moving meter of this substrate supports.Said at least one moving meter includes the superlattice that comprise a plurality of layer group of piling up; Each of said superlattice layer group comprises a plurality of basic semiconductor monolayer of piling up and at least one monolayer; Wherein said basic semiconductor monolayer defines basic semiconductor portions, and said monolayer is limited in the lattice of adjacent basic semiconductor portions.
More specifically, superlattice can be piezoelectric superlattice.The MEMS device also comprises the driver by substrate supports that is used for moving at least one moving meter.In addition, first conductive contact piece is supported by at least one moving meter, and second conductive contact piece is aimed at by substrate supports and with first conductive contact piece.
The MEMS device can also comprise first radio frequency (RF) holding wire that is connected with first conductive contact piece, with the 2nd RF holding wire that is connected with second conductive contact piece.In addition, also comprise and be used for bias voltage is imposed on a pair of bias voltage contact that superlattice move at least one moving meter.And, the part superlattice can with substrate separately.In addition, this MEMS device can also comprise by the dielectric anchor of substrate supports (dielectric anchor), and at least one moving meter can be supported by this dielectric anchor.
For superlattice, basic semiconductor can comprise silicon, and at least one monolayer can comprise for example oxygen.More specifically, at least one monolayer comprises the non-semiconductor that is selected from mainly in the group that is made up of oxygen, nitrogen, fluorine and carbon-oxygen.In addition, at least one monolayer can be a thickness in monolayer.All base semiconductor portions can be the thickness in monolayer of equal number, and perhaps at least some base semiconductor portions can be the thickness in monolayer of varying number.In addition, the basic relatively semiconductor portions of the adjacent groups of layers of at least one superlattice can chemical bonding together.
A kind of method that is used to make the MEMS device can comprise the steps: to provide substrate and form at least one moving meter by this substrate supports.Said at least one moving meter includes the superlattice that comprise a plurality of layer group of piling up; Each of said superlattice layer group comprises a plurality of basic semiconductor monolayer of piling up and at least one monolayer; Wherein said basic semiconductor monolayer defines basic semiconductor portions, and said monolayer is limited in the lattice of adjacent basic semiconductor portions.
Description of drawings
Fig. 1 is the top view of Micro Electro Mechanical System (MEMS) device that the present invention includes superlattice.
Fig. 2 is the sectional view along the line 2-2 among Fig. 1.
Fig. 3 is the amplification sectional view of superlattice among Fig. 1.
Fig. 4 is the atomic structure perspective view of a part of superlattice shown in Figure 3.
Fig. 5 is the amplification sectional view of another embodiment of the superlattice that use in the device of Fig. 1.
Fig. 6 A is the band structure figure that calculates from γ point (G) for of the prior art block of silicon and 4/1 Si/O superlattice shown in Figure 2.
Fig. 6 B is the band structure figure that calculates from the Z point for of the prior art block of silicon and 4/1 Si/O superlattice shown in Figure 1.
Fig. 6 C is the band structure figure that calculates from γ point and Z point for of the prior art block of silicon and 5/1/3/1 Si/O superlattice shown in Figure 5.
Fig. 7 A-7F has shown that a series of sectional views represent among the present invention to make the method for the superlattice that are used for the MEMS device.
Fig. 8 A-8F has shown that a series of sectional views represent among the present invention to make the another kind of method of the superlattice that are used for the MEMS device.
Fig. 9 A-9F has shown that a series of sectional views represent among the present invention to make the another kind of method of the superlattice that are used for the MEMS device.
Figure 10 A-10G has shown that a series of sectional views represent among the present invention to make the another kind of method of the superlattice that are used for the MEMS device.
Figure 11 A-11F has shown that a series of sectional views represent among the present invention to make the another kind of method of the superlattice that are used for the MEMS device.
Figure 12 A-12G has shown that a series of sectional views represent among the present invention to make the another kind of method of the superlattice that are used for the MEMS device.
Embodiment
With reference to the accompanying drawings the present invention is described below in greater detail, has wherein shown preferred embodiments more of the present invention.The present invention can be confined to each embodiment that this paper proposes and should not be construed with multiple multi-form enforcement.These embodiment are provided, so that of the present invention open more comprehensively with complete, and to the comprehensive reception and registration of those skilled in the art scope of the present invention.Reference numeral identical in inscription on ancient bronze objects is represented components identical, " ' " symbol then is used for the element of representing that various embodiment is similar.
The present invention relates to the character of control semi-conducting material on atom or molecular level, thereby obtain to improve the semiconductor device of performance.In addition, the invention still further relates to the improved material of discriminating, creation and serviceability, so that be applied in the conductive path of semiconductor device.
Under situation about being not wishing to be bound by theory, the applicant's reasoning some superlattice as herein described have reduced the effective mass of electric charge carrier and have therefore caused higher charge carrier mobility.In document, have various definition for effective mass.Improvement as effective mass is measured; The applicant has used " the anti-effective mass tensor of conductivity ";
and
representes that respectively the corresponding of electronics and hole measure, definition as follows:
For electronics:
For the hole:
Wherein f is Fermi-Di Lake distribution function, E
FBe Fermi energy, T is temperature (Kelvin), E (k; N) be corresponding to the electron energy in wave vector k and the n level ability carrier state; Subscript i and j represent cartesian coordinate x, y, z; (B.Z.) gets integration to it in the Brillouin zone, and the energy in electronics and hole be higher than respectively and be lower than among being with of Fermi energy art with.
The applicant makes the bigger part of numerical value in the respective components of the anti-equivalent mass tensor of material electric conductivity for the definition of the anti-effective mass tensor of conductivity, and the component of tensor of conductivity of electrolyte materials is also bigger.The applicant is also once more at the numerical value of not accepting the anti-effective mass tensor of conductivity that reasoning superlattice described herein set under the situation of opinion constraint in addition, to improve the conduction property of material, for example typically for the preferred orientations of charge carrier transport.Suitably the inverse of component of tensor b referred to as the conductivity effective mass at this.In other words, for characterize semiconductor material structures, the conductivity equivalent mass of the electrons/of as above describing and on the direction that the charge carrier intention will be transmitted, calculating can be used to existing improved these materials of distinctive function.
Use said method, the material that can select to have improved band structure for specific purpose.An example is the super crystal lattice material 25 (following will describing in detail to it) that in microscopic electro-mechanical systems (MEMS) device 20, uses.Developed some and used, wherein less relatively device is adjustable condenser for example, and switch etc. are all well used.It is very favourable that these devices use the MEMS manufacturing process to make, and wherein very little moving meter can use deposition, plating or other additional process, and selective etch, and/or other emerging technology combines and is formed on the substrate.
These technology usually form a kind of structures, thereby it is finally discharged by part or remove and makes mechanical movement take place, particularly as a kind of result of electrostatic force.This electrostatic force can produce to conductor at interval through applying voltage.A kind of common MEMS structure is the switch that is provided by the conduction light beam, and this conduction light beam one end is anchored, and another opposite end is connected with adjacent contacts through the electrostatic force that applies.
Author Los Santo equals to be published in IEEE Microwave Magazine in December, 2004, is entitled as in " RF MEMS for Ubiquious Wireless Connectivity:Part 1-Fabrication " literary composition; The various application of MEMS have been discussed, have been incorporated into its full content through reference at this.This article points out that the MEMS technology can be applied to radio frequency (RF)/microwave system, because RF MEMS can provide passive device for example switch, changeable (two states) capacitor, adjustable condenser (variable capacitance diode), inductor, transmission line resonator.Like this, these devices just can be used in this locality/ground, move and space field in the wireless application operation in, for example mobile phone, base station and artificial satellite.
In Fig. 1 and Fig. 2, introduced an exemplary MEMS device 20 that comprises superlattice 25 (that is switch) for the first time.Although should be noted that the preferred embodiment of having introduced mems switch, superlattice 25 can be used for polytype MEMS device, comprise the above-mentioned type of mentioning, and are the basis and are understood with content disclosed herein as those skilled in the art.
As introducing in people's such as Los Santos the article, the physical basis that is used to start MEMS is the piezoelectric effect of counter-rotating.When voltage is applied to whole piezoelectric layer, can cause this layer mechanical deformation.This distortion can be opened a relay of closing or closed the relay opened.The conventional method of making mems switch is to use a cantilever (cantilever) structure to form a relay.Through this structure needed function is provided, their manufacturing possibly be very difficult.
In MEMS device 20, superlattice 25 are become piezoelectrics by electric polarization (polled), and for this MEMS device a moving meter are provided as stated.Particularly, this MEMS device 20 also exemplarily comprises a substrate 21, for example Semiconductor substrate (like silicon, SOI etc.).Groove 22 be formed on around and be arranged in the substrate 21 of superlattice 25 belows, thereby make part superlattice and substrate spaced apart (that is, being positioned at below it), and dielectric anchor 23 with the superlattice anchor on the substrate above the channel bottom, as shown in the figure.Certainly, also can use other arrangement mode, as well-known to those skilled in the art.
Thereby a pair of bias voltage contact 30,31 and superlattice 25 couplings apply a bias voltage and are used for moving this moving meter.Particularly, this bias voltage contact 30,31 can be the conductive path that is formed in the superlattice 25, and also can use surperficial contact or metallization in certain embodiments.Conductive traces/ metallization 32,33 is connected to bias voltage contact 30,31 on the positive and negative connector of drive circuit 24 respectively.Like this; When drive circuit 24 applies a bias voltage through bias voltage contact 30,31 for superlattice 25; To cause the superlattice mechanical deformation, and then can cause moving meter to move to second electric contact piece 27, shown in the four-headed arrow among Fig. 1 from first electric contact piece 26.This will close this switch easily and make a signal (like the RF signal) at first and second holding wires 28, conduct between 29.In addition, when bias voltage was removed, moving meter was removed first contact 26 from second contact 27, thereby switch is opened, as well-known to those skilled in the art.
Oxide layer 34 (Fig. 2) is formed on the top of whole superlattice semiconductor region, and preferably removes the part at this super crystal lattice material place of expectation contact.Should be noted that in illustrated embodiment, the side/bottom of groove 22 and moving meter is shown as and is not passivated.Yet,, can also on the semi-conducting material that exposes, form dielectric layer, for example SiO if some embodiment need
2, as well known to those skilled in the art.
Referring to Fig. 3 and 4, the structure of superlattice 25 is controlled in the level of atom or molecule, and can utilize known atom or molecular layer deposition technique to form.These superlattice 25 comprise a plurality of layer group 45a-45n that arrange with the form of piling up, and as stated, can understand its stacked relation better referring to Fig. 3 sectional view.
Each layer of superlattice 25 group 45a-45n comprises exemplarily that a plurality of piling up basically partly lead this individual layer 46, its defined basic semiconductor region 46a-46n separately with and top can be with modified layer 50.In Fig. 3,, represent to be with modified layer 50 with pointillism for clearly expression.
Illustratedly can exemplarily comprise a monolayer in the lattice that is limited in adjacent basic semiconductor portions with modified layer 50.That is, the relative basic semiconductor monolayer 46 in adjacent groups of layers 45a-45n is chemically bound in together.For example, under the situation of silicon single-layer 46, on the top of individual layer group 46a or the bottom of some silicon atoms in the top semiconductor monolayer and individual layer group 46b or some the silicon atom covalent bondings in the individual layer of bottom.Have some monolayer (like the oxygen individual layer) although this makes, lattice still keeps continuously in whole layer group.Certainly, between the relative silicon layer 46 of adjacent groups of layers 45a-45n, be not the simple covalent bonding of complete sum because all have in every layer some silicon atoms will with non-semiconductor atom (like oxygen in the present embodiment) bonding, as understood by one of ordinary skill in the art.
In other embodiments, can have more than a monolayer.As an example, can be preferably less than about 5 individual layers, can be with the modification performance thereby can provide required with the number of the monolayer in the modified layer 50.
Should be noted that non-semiconductor or the semiconductor monolayer mentioned mean that the material that is used for individual layer so is exactly non-semiconductor or semiconductor if become the piece manufacturing here.That is, a monolayer material, semiconductor for example, the identical character that can show into the piece manufacturing or had when making with thicker relatively layer, as it will be apparent to those skilled in the art that.
Under situation about being not wishing to be bound by theory, the applicant's reasoning can be with modified layer 50 and adjacent basic semiconductor region 46a-46n, makes superlattice 25 on the parallel layers direction, the electric charge current-carrying in suitable conductivity effective mass be lower than other situation.Consider this parallel direction and stacking direction quadrature in another way.Can also make superlattice 25 have common band structure with modified layer 50, in addition can also be advantageously as insulator between the vertical layer of superlattice 25 upper and lowers and zone.In addition, this structure can also be oozed out or spread the vertical layer of superlattice 25 upper and lowers and the doping between the zone and/or material provides a barrier layer (barrier).In addition, under situation about being not wishing to be bound by theory, the applicant's reasoning superlattice 25 can become piezoelectrics through electric polarization, as it will be apparent to those skilled in the art that.
Can also infer, superlattice 25 are higher than other situation based on the charge carrier mobility that lower conductivity effective mass provides.Certainly, the character of the not all above-mentioned ultra crystal 2 of mentioning 5 is all used in each is used and is obtained.For example, in some applications, the doping of only using superlattice 25 stops/mobility of insulating properties or its raising, or the two is all used and obtains in other is used, as known in those skilled in the art.
Cap rock 52 is positioned on the upper layer group 45n of superlattice 25.Cap rock 52 can comprise a plurality of basic semiconductor monolayer 46.Cap rock 52 can have 2 to 100 basic semiconductor monolayer, and more preferably has 10 to 50 individual layers.Also can use other thickness.
Each basic semiconductor portions 46a-46n can comprise the basic semiconductor that is selected from the group that is made up of IV family semiconductor, III-V family semiconductor and II-VI family semiconductor.Certainly, it will be understood by those skilled in the art that term IV family semiconductor also comprises IV-IV family semiconductor.More specifically be that basic semiconductor can comprise at least one in the for example silicon and germanium.
Each can comprise the for example non-semiconductor of one of oxygen, nitrogen, fluorine and carbon oxygen with modified layer 50.Non-semiconductor is also preferably thermally-stabilised through one deck under the deposition, thereby is convenient to make.It will be understood by those skilled in the art that in other embodiments non-semiconductor can be another kind of and given compatible inorganic or organic element or the compound of semiconductor technology.
Should be noted that term " individual layer " means comprises single atomic layer and individual molecule layer.Shall also be noted that by what individual layer provided and can be with modified layer 50, also mean and comprise the individual layer that does not wherein occupy all possible positions.For instance, specifically with reference to the atomic diagram of Fig. 3, for as the silicon of basic semi-conducting material with as can be with material modified oxygen, for example clear a kind of 4/1 repetitive structure.Oxygen has only occupied half possible position.
It will be understood by those skilled in the art that in other embodiment and/or different materials, this half occupy all situation that is not necessarily.In fact even in said sketch map, also can find out single oxygen atom in given individual layer not accurately along planar alignment, this technical staff for the atomic deposition field also is understandable.For instance, preferably occupy scope and be from whole 1/8th to half the, although also can use other quantity in certain embodiments.
Silicon and oxygen are widely used in traditional semiconductor technology at present, so the manufacturer can use these materials described herein.Atom or monolayer deposition also are present widely used technology.Therefore, as it will be apparent to those skilled in the art that, comprise according to the semiconductor device of disclosed superlattice 25 and can use easily and realize.
Under the situation of not accepting the opinion constraint; The applicant's reasoning, for instance for for the superlattice of Si/O, the number of silicon single-layer preferably should be 7 layers or still less; Make that being with in entire scope of superlattice is identical or even relatively, thereby realize required advantage.For Si/O, provided the model of 4/1 repetitive structure shown in Figure 3, point out that electronics and hole show the mobility of enhancing on the x direction.For instance, the electronic conductivity effective mass of being calculated (is isotropic for piece silicon) is 0.26, and 4/1 SiO superlattice are 0.12 in the directions X, so ratio is 0.46.Similarly, be 036 to the value that calculates for piece silicon in hole, be 0.16 for the value of 4/1 Si/O superlattice, so ratio be 0.44.
Although this direction preferred feature is favourable in some semiconductor device, in other device, the even increase of the mobility on any direction that is parallel to layer group plane then maybe be more favourable.Increase when it will be understood by those skilled in the art that electronics or hole mobility, it also is favourable perhaps having only wherein a kind of charge carrier mobility increase.
For 4/1 Si/O embodiment of superlattice 25, what its conductivity effective mass can be than non-superlattice conductivity effective mass is 2/3 also low, and this all is suitable for electronics and hole.For ultra crystal 25 mixes also possibly be suitable.Certainly, it will be understood by those skilled in the art that one of superlattice 25 or more multilayer group 45 can keep basic non-impurity-doped, depend on the position of superlattice in particular type and the device of the MEMS device that is implemented.
With reference to Fig. 5, another embodiment that has superlattice 25 ' of different nature according to of the present invention is described in addition.In this embodiment, for example clear 3/1/5/1 repeat pattern.More particularly, nethermost basic semiconductor portions 46a ' has three individual layers, and the second nethermost basic semiconductor portions 46b ' has five individual layers.In whole superlattice 25 ', repeat this pattern.Each can comprise an individual layer to be with modified layer 50.For this superlattice 25 ' that comprise Si/O, the raising of charge carrier mobility and the orientation of layer plane are irrelevant.Other element of those that specifically do not mention among Fig. 5 is similar with the element of discussing in the above with reference to Fig. 3, need not repeat herein to discuss.
In some device embodiment, the basic semiconductor portions 46a-46n of all of superlattice 25 can be the thickness of same number of monolayers.In further embodiments, at least some basic semiconductor portions 46a-46n can be the thickness of varying number individual layer.In further embodiments, all basic semiconductor portions 46a-46n can be the thickness of varying number individual layer.
In Fig. 6 A-6C, represented the band structure that use density functional theory (DFT) is calculated.DFF known in this field can underestimate the absolute value of band gap.Therefore, all can be with above the band gap can be squinted through suitable " scissors correction " (" scissors correction ").But the known shape that can be with then is comparatively reliable.Should explain vertical energy axes in this manner.
Fig. 6 A has represented the γ point (G) of band structure calculate from to(for) piece silicon (line by continuous is represented) and 4/1Si/O superlattice 25 (as shown in Figure 3), and it is represented with dotted line in Fig. 6 A.Although (001) direction is corresponding with (001) direction of traditional Si unit cell among the figure, this direction refers to the unit cell of 4/1Si/O structure rather than traditional Si unit cell, therefore representes the desired position of Si conduction band minimum.(100) among the figure are corresponding with (110) and (110) direction of traditional Si unit cell with (010) direction.It will be understood by those skilled in the art that being with folding direction of Si shows on the figure, so that on the suitable reciprocal lattice direction of 4/1 SiO structure, show.
Can find out that (Si) compares with piece silicon, the conduction band minimum of 4/1 Si/O structure is positioned on the γ point, and valence band minimum is positioned at the edge of (001) direction Brillouin zone, and we are called the Z point.What it is further noted that the disturbance that caused by additional oxygen layer causes can be with division, compares with the curvature of Si conduction band minimum, and the conduction band minimum of 4/1 Si/O structure has bigger curvature.
Fig. 6 B representes the Z point of band structure calculate from to(for) the 4/1Si/O superlattice 25 (dotted line) of piece silicon (continuous lines) and Fig. 3.The figure illustrates the curvature that valence band increases on (100) direction.
Fig. 6 C representes the Z point of band structure calculate from γ point and to(for) the 5/1/3/1 Si/O superlattice 25 ' (dotted line) of piece silicon (continuous lines) and Fig. 5.Because the symmetry of 5/1/3/1 Si/O structure, the band structure of on (100) and (010) direction, calculating is equal to.Therefore, in the plane parallel with each layer, promptly perpendicular on (001) stacking direction, conductivity effective mass and mobility can expect it is isotropic.Attention is in 5/1/3/1 Si/O instance, and conduction band minimum and valence band maximum all are in perhaps near the Z point.
Although the index that the curvature increase is an effective mass to be reduced can be made suitable comparison and distinguishes by the calculating of the anti-effective mass tensor of conductivity.This just causes applying for person's one step reasoning 5/1/3/1 superlattice 25 ', should be basic direct band gap.It will be understood by those skilled in the art that be used for suitable matrix unit that optics shifts be directly and another of indirect band gap behavior distinguish index.
Under the situation of not accepting the opinion constraint, the distortion of the lattice of discussing in the above paragraph of the applicant's reasoning has produced superlattice semiconductor material, is different from the silicon that does not have piezoelectricity, and this material has piezoelectric property.
The various technological processes of the superlattice 25 that introducing now is shaped is used for the MEMS device.In general, MEMS device 20 is to make through the piezoelectric regions or the piezoelectric film that include ultra crystal 25 along trenched side-wall formation one.After piezoelectric film was shaped and metallizes, except an end, it did not need mechanical support (that is, groove 22 is following) and carries out etching, in the embodiment shown in Fig. 1 and 2, is supported by dielectric anchor 23.
Referring to Fig. 7 A-7F, introduce first technological process now.This process sequence has used deposition step to be filled in etched groove 70 on silicon-on-insulator (SOI) substrate.More specifically, this SOI substrate comprises that a dielectric is (like SiO
2) layer 71 and semiconductor (like the silicon) layer 72 that is positioned on the dielectric layer.On semiconductor layer 72, be formed with a pad (pad) oxide layer 73, a nitrogenize (like silicon nitride) layer 74 deposition are carried out photoetching and etching step subsequently and are formed groove 70 above that then.
Then, superlattice 75 (as stated) optionally are deposited on the wall of groove 70.Dielectric 76, dielectric interlayers, or other trench fill material is deposited on superlattice 75 and the nitration case 74 subsequently, then carries out planarization steps (Fig. 7 D), and all material that is about on the nitration case is all removed.Nitration case 74 and pad oxide layer 73 are removed through etching, then are semiconductor layers 72.The material (for example, dielectric 76) that is used for filling groove 70 is etched then, thereby substrate is ready for oxidation at this moment, contact is shaped, metallizes and release etch forms above-mentioned MEMS device 20 (or other MEMS device).
With reference now to accompanying drawing 8A-8F,, introduces other same technological process of using deposition step to fill etched trench.Be noted that these with the flow chart of following discussion in, similar element is represented (for example, dielectric layer 71 and dielectric layer 81,91 are similar, or the like) with 10 increment.Like this, these elements only need be introduced when occurring for the first time.
The technology that technology shown in Fig. 8 A-8F and above Fig. 7 A-7F introduce is similar; Except monocrystalline superlattice semi-conducting material in superlattice 85 deposition process is formed on the wall of groove 80, polycrystalline superlattice semiconductor material 87 (showing with pointillism for clear) is formed on channel bottom and the nitration case 84 simultaneously.After trench fill and planarization steps (Fig. 8 C and 8D), part polysilicon 87 is etched removal, and remainder is oxidized to oxide layer 88 (Fig. 8 E).Nitration case 84 is removed (that is etching) with pad oxide layer 83.Substrate is ready for contact shaping, metallization and release etch, (Fig. 8 F) as stated.
Introduce four technological processes referring now to Fig. 9-12, it is used for forming independent side piezoelectric cantilever superlattice structure along the sidewall of each groove.More specifically, the technology shown in the technology shown in Fig. 9 A-9F and Fig. 7 A-7F is similar, except superlattice 95 optionally are deposited on the trench wall 90, rather than fills whole groove.
Similar technical process shown in another and Fig. 9 A-9F is shown in Figure 10 A-10F.This technology starts from a standard semiconductor substrate 102, rather than the SOI substrate.Other difference be on the sidewall that superlattice 105 optionally is deposited on groove (Figure 10 B) before, with an oxide layer (like, SiO
2) be formed in the bottom of groove 100.Another technology that is illustrated in Figure 11 A-11F is similar with the technology that is illustrated in Fig. 8 A-8F, optionally is deposited on except superlattice 115 on the sidewall of groove 110, rather than fills whole groove.Another technology that is illustrated in Figure 12 A-12G is similar with the technology that is illustrated in Figure 10 A-10G, except it has comprised as with reference to the described polysilicon deposition of Fig. 8 A-8F.Just like the technological process shown in Fig. 9-12 in, before forming contact openings, on the top of piezoelectric superlattice material, have layer of silicon dioxide.
Under the instruction that explanation in front and relevant drawings provide, those skilled in the art can make many modifications and other embodiment to the present invention.Therefore, be to be understood that these are revised and embodiment is included in the scope of accessory claim.
Claims (23)
1. a Micro Electro Mechanical System MEMS device comprises
Substrate; With
At least one moving meter by said substrate supports; Said moving meter includes the superlattice that comprise a plurality of layer group of piling up; Each of said superlattice layer group comprises a plurality of basic semiconductor monolayer of piling up and at least one monolayer; Wherein said basic semiconductor monolayer defines basic semiconductor portions, and said monolayer is limited in the lattice of adjacent basic semiconductor portions;
Be chemically bound in together from least some semiconductor atoms of basic relatively semiconductor portions at least one monolayer through therebetween;
Wherein said superlattice comprise electropolarized superlattice.
2. MEMS device as claimed in claim 1 also comprises the driver that is used for driving said at least one moving meter by said substrate supports.
3. MEMS device as claimed in claim 1 also comprises by first conductive contact piece of said at least one moving meter support with by said substrate supports and second conductive contact piece that aim at said first conductive contact piece.
4. MEMS device as claimed in claim 3 also comprises the first radio frequency rf signal line that is connected with said first conductive contact piece, with the 2nd RF holding wire that is connected with said second conductive contact piece.
5. MEMS device as claimed in claim 1 also comprises a pair of bias voltage contact, is used for bias voltage is applied on the said superlattice to move said at least one moving meter.
6. MEMS device as claimed in claim 1, center divide said superlattice and said substrate separately.
7. MEMS device as claimed in claim 1 also comprises the dielectric anchor by said substrate supports, and wherein said at least one moving meter is supported by said dielectric anchor.
8. MEMS device as claimed in claim 1, wherein said basic semiconductor comprises silicon.
9. MEMS device as claimed in claim 1, wherein said at least one monolayer comprises oxygen.
10. MEMS device as claimed in claim 1, wherein said at least one monolayer comprises the non-semiconductor that is selected from the group that is made up of oxygen, nitrogen, fluorine and carbon-oxygen.
11. MEMS device as claimed in claim 1, wherein said at least one monolayer are thickness in monolayer.
12. MEMS device as claimed in claim 1, wherein all said basic semiconductor portions thickness that all is same number of monolayers.
13. MEMS device as claimed in claim 1, at least some have the thickness of varying number individual layer in the wherein said basic semiconductor portions.
14. a method that is used to make Micro Electro Mechanical System MEMS device comprises the steps:
Substrate is provided; With
Formation is by at least one moving meter of said substrate supports; Said moving meter includes the superlattice that comprise a plurality of layer group of piling up; Each of said superlattice layer group comprises a plurality of basic semiconductor monolayer of piling up and at least one monolayer; Wherein said basic semiconductor monolayer defines basic semiconductor portions, and said monolayer is limited in the lattice of adjacent basic semiconductor portions;
Be chemically bound in together from least some semiconductor atoms of basic relatively semiconductor portions at least one monolayer through therebetween;
Wherein said superlattice comprise electropolarized superlattice.
15. method as claimed in claim 14 also comprises the steps: to provide the driver that is used for driving said at least one moving meter by said substrate supports.
16. method as claimed in claim 14 also comprises the steps: to form first conductive contact piece that is supported by said at least one moving meter and form by said substrate supports and second conductive contact piece that aim at said first conductive contact piece.
17. method as claimed in claim 16 also comprises the steps: to form the first radio frequency rf signal line that is connected with said first conductive contact piece, the 2nd RF holding wire that is connected with said second conductive contact piece with formation.
18. method as claimed in claim 14 also comprises the steps: to be formed for bias voltage is applied on the said superlattice to move a pair of bias voltage contact of said at least one moving meter.
19. method as claimed in claim 14, center are divided said superlattice and said substrate separately.
20. method as claimed in claim 14 also comprises the steps: to form the dielectric anchor by said substrate supports, wherein said at least one moving meter is supported by said dielectric anchor.
21. method as claimed in claim 14, wherein said basic semiconductor comprises silicon; And said at least one monolayer comprises oxygen.
22. method as claimed in claim 14, wherein said at least one monolayer comprises the non-semiconductor that is selected from the group that is made up of oxygen, nitrogen, fluorine and carbon-oxygen.
23. method as claimed in claim 14, wherein said at least one monolayer are thickness in monolayer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US68599605P | 2005-05-31 | 2005-05-31 | |
| US60/685,996 | 2005-05-31 | ||
| PCT/US2006/021082 WO2006130665A2 (en) | 2005-05-31 | 2006-05-31 | Microelectromechanical systems (mems) device including a superlattice and associated methods |
Publications (2)
| Publication Number | Publication Date |
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| CN101258100A CN101258100A (en) | 2008-09-03 |
| CN101258100B true CN101258100B (en) | 2012-01-04 |
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| CN2006800188160A Expired - Fee Related CN101258100B (en) | 2005-05-31 | 2006-05-31 | Microelectromechanical systems (MEMS) device including a superlattice and associated methods |
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| Country | Link |
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| EP (1) | EP1896361A2 (en) |
| JP (1) | JP2008545542A (en) |
| CN (1) | CN101258100B (en) |
| AU (1) | AU2006252590A1 (en) |
| CA (1) | CA2609614A1 (en) |
| TW (2) | TWI306666B (en) |
| WO (1) | WO2006130665A2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8604898B2 (en) * | 2009-04-20 | 2013-12-10 | International Business Machines Corporation | Vertical integrated circuit switches, design structure and methods of fabricating same |
| CN102442631A (en) * | 2010-10-08 | 2012-05-09 | 探微科技股份有限公司 | Micro-electromechanical device and composite base material used in one micro-electromechanical device |
| CN105428520A (en) * | 2015-11-09 | 2016-03-23 | 业成光电（深圳）有限公司 | Method for manufacturing piezoelectric element and piezoelectric substrate |
Citations (3)
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| US5393375A (en) * | 1992-02-03 | 1995-02-28 | Cornell Research Foundation, Inc. | Process for fabricating submicron single crystal electromechanical structures |
| CN1429408A (en) * | 2000-05-19 | 2003-07-09 | 秦内蒂克有限公司 | Charge carrier extracting transistor |
| EP1150318B1 (en) * | 1998-12-22 | 2007-11-28 | Denso Corporation | Micromachine switch and its production method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4590399A (en) * | 1984-02-28 | 1986-05-20 | Exxon Research And Engineering Co. | Superlattice piezoelectric devices |
| EP1410427A4 (en) * | 2001-06-14 | 2008-04-23 | Nanodynamics Inc | Epitaxial sio x? barrier/insulation layer---------------------- |
| JP2003217421A (en) * | 2002-01-24 | 2003-07-31 | Matsushita Electric Ind Co Ltd | Micromachine switch |
| US6897472B2 (en) * | 2003-06-26 | 2005-05-24 | Rj Mears, Llc | Semiconductor device including MOSFET having band-engineered superlattice |
-
2006
- 2006-05-31 CN CN2006800188160A patent/CN101258100B/en not_active Expired - Fee Related
- 2006-05-31 WO PCT/US2006/021082 patent/WO2006130665A2/en active Search and Examination
- 2006-05-31 AU AU2006252590A patent/AU2006252590A1/en not_active Abandoned
- 2006-05-31 CA CA002609614A patent/CA2609614A1/en not_active Abandoned
- 2006-05-31 EP EP06760587A patent/EP1896361A2/en not_active Withdrawn
- 2006-05-31 JP JP2008513842A patent/JP2008545542A/en active Pending
- 2006-06-01 TW TW95119424A patent/TWI306666B/en not_active IP Right Cessation
- 2006-06-01 TW TW95119421A patent/TWI306646B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393375A (en) * | 1992-02-03 | 1995-02-28 | Cornell Research Foundation, Inc. | Process for fabricating submicron single crystal electromechanical structures |
| EP1150318B1 (en) * | 1998-12-22 | 2007-11-28 | Denso Corporation | Micromachine switch and its production method |
| CN1429408A (en) * | 2000-05-19 | 2003-07-09 | 秦内蒂克有限公司 | Charge carrier extracting transistor |
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| Tsu.Phenomena in silicon nanostructure devices.《Applied Physics A》.2000,第71卷(第4期),第391-402页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008545542A (en) | 2008-12-18 |
| AU2006252590A1 (en) | 2006-12-07 |
| AU2006252590A8 (en) | 2008-04-03 |
| WO2006130665A3 (en) | 2007-01-18 |
| CN101258100A (en) | 2008-09-03 |
| TWI306646B (en) | 2009-02-21 |
| WO2006130665A2 (en) | 2006-12-07 |
| TWI306666B (en) | 2009-02-21 |
| TW200711124A (en) | 2007-03-16 |
| TW200707650A (en) | 2007-02-16 |
| CA2609614A1 (en) | 2006-12-07 |
| EP1896361A2 (en) | 2008-03-12 |
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