JP2008545542A - Microelectromechanical system (MEMS) device having a superlattice and related methods - Google Patents

Abstract

A microelectromechanical system (MEMS) device may include a substrate and at least one movable portion supported by the substrate. The at least one movable portion may include a superlattice having a plurality of groups each including a plurality of layers. Each of the superlattice groups is internally constrained to a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion and a crystal lattice of an adjacent basic semiconductor portion. Having at least one non-semiconductor molecular layer;

Description

  The present invention relates to the semiconductor field. More particularly, the present invention relates to a semiconductor device having a superlattice and related methods.

  Structures and methods have been proposed for improving the performance of semiconductor devices, such as improving charge carrier mobility. For example, Patent Document 1 discloses a strained material layer made of silicon, silicon-germanium, and relaxed silicon. These material layers also have regions that do not contain impurities so as not to cause performance degradation. As a result of the biaxial strain in the upper silicon layer, the carrier mobility changes. Thereby, a higher speed and / or lower power consumption element is possible. Patent Document 2 discloses a CMOS inverter based on the same strained silicon technology.

  Patent Document 3 discloses a semiconductor element in which a conduction layer and a valence band of a second silicon layer are affected by tensile strain by having silicon and a carbon layer sandwiched between silicon layers. It is believed that the n-channel MOSFET has a higher mobility because electrons having a smaller effective mass and electrons induced by the electric field applied to the gate electrode are confined to the second silicon layer.

  Patent Document 4 discloses a superlattice in which a plurality of layers having fewer than eight layers and having a fractional ratio or a binary compound semiconductor layer are alternately epitaxially grown. The direction in which the current mainly flows is perpendicular to the superlattice layer.

  Patent Document 5 discloses a Si—Ge short period superlattice in which high mobility is realized by reducing alloy scattering in the superlattice. In accordance with this policy, Patent Document 6 is a MOSFET having a channel layer having an alloy of silicon and a second material, and the second material is in such a ratio that the channel layer is subjected to tensile strain. Discloses a MOSFET with improved mobility by being in a substituted state in the silicon lattice.

Patent Document 7 discloses a quantum well having two barrier regions and an epitaxially grown semiconductor thin film sandwiched between the barrier layers. Each barrier region is typically composed of a repeating layer of SiO ₂ / Si having a thickness in the range of 2 to 6 molecular layers. A fairly thick silicon part is sandwiched between barriers.

  Non-patent document 1 entitled “Phenomena in silicon nanostructure device” by Tsu discloses a semiconductor-atomic superlattice (SAS) composed of silicon and oxygen. is doing. Si / O superlattices are disclosed as being useful as silicon quantum devices and light emitting devices. In particular, a green electroluminescent diode structure has been constructed and tested. The current in the diode structure flows vertically, ie perpendicular to the SAS layer. The disclosed SAS may have semiconductor layers separated by adsorbing species such as oxygen atoms and CO molecules. It can be said that the growth of silicon on the adsorbed oxygen molecular layer is an epitaxial growth with a considerably low defect density. One SAS structure has a silicon portion of 1.1 nm thickness, which is about 8 atomic layers of silicon, and the other SAS structure has twice the thickness of this silicon. Non-patent document 2 entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” by Luo et al. Is discussed further.

  Patent Document 8 discloses a barrier that is composed of thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen, thereby reducing the current flowing vertically through the lattice by less than four orders of magnitude. The insulating / barrier layer allows low defect silicon to be epitaxially grown on the insulating layer.

Patent Document 9 discloses that the principle of an aperiodic photonic band gap (APBG) structure is consistent with electronic band gap engineering. In particular, the application discloses that by adjusting material parameters such as the position of the band minimum, effective mass, etc., a new aperiodic material having the desired band structure characteristics can be obtained. Other parameters such as conductivity, thermal conductivity, dielectric constant, or permeability are also disclosed as enabling material design.
US Patent Application Publication No. 2003/0057416 US Patent Application Publication No. 2003/0034529 U.S. Pat. U.S. Pat. No. 4,937,204 U.S. Pat.No. 5,357,119 U.S. Patent No. 5683934 U.S. Pat.No. 5,216,262 International Publication No. 2002/103767 Pamphlet UK Patent Application No. 2347520 Tsu, Applied Physics and Materials Science & Processing, pp.391-402, published online September 6, 2000 Luo et al., Physical Review Letters, Vol. 89, August 12, 2002 Los Santo et al., “EF MEMS for Ubiquitous Wireless Connectivity (“ RF MEMS Ubiquitous Wireless Connectivity ”)” IEEE Microwave, December 2004

  The present invention relates to the semiconductor field. More particularly, the present invention relates to a semiconductor device having a superlattice and related methods.

  A microelectromechanical system (MEMS) device may include a substrate and at least one movable portion supported by the substrate. The at least one movable portion may include a superlattice having a plurality of groups each including a plurality of layers. Each of the superlattice groups is internally constrained to a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion and a crystal lattice of an adjacent basic semiconductor portion. Having at least one non-semiconductor molecular layer;

  More particularly, the superlattice may be a piezoelectric superlattice. The MEMS element may further include a driving device that drives at least one movable part while being supported by the substrate. Further, the first conductive contact may be supported by the at least one movable part, and the second conductive contact may be supported by the substrate and aligned with the first conductive contact.

  The MEMS device may further include a first radio frequency (RF) signal connected to the first conductive contact and a second RF signal connected to the second conductive contact. In addition, a pair of bias voltage contacts for applying a bias voltage to the superlattice to move the at least one movable part may be included. Furthermore, the superlattice portion may be provided spaced from the substrate. The MEMS device may further include a dielectric anchor supported by the substrate. The at least one movable part may be supported by the dielectric anchor.

  As for the superlattice, for example, the basic semiconductor may include silicon, and the at least one non-semiconductor molecular layer may include oxygen. More specifically, the at least one non-semiconductor molecular layer may comprise a non-semiconductor selected from the group consisting essentially of oxygen, nitrogen, fluorine, and carbon-oxygen. Further, the at least one non-semiconductor molecular layer may be a monomolecular layer thickness. All of the basic semiconductor portions may have the same molecular layer thickness, or at least some of the basic semiconductor portions may have different molecular layer thicknesses. In addition, opposing basic semiconductor portions included in adjacent groups of a plurality of layers of the at least one superlattice may be chemically bonded together.

  The method aspect may be a method for manufacturing a MEMS device, which includes a step of providing a substrate and a step of forming at least one movable part supported by the substrate. The at least one movable portion may include a superlattice having a plurality of groups each including a plurality of layers. Each of the superlattice groups is internally constrained to a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion and a crystal lattice of an adjacent basic semiconductor portion. Having at least one non-semiconductor molecular layer;

  The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments are shown. However, the invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this specification, the same reference numbers will refer to the same elements, and the dash will be used to refer to similar elements in alternative embodiments.

  The present invention relates to improving the performance of semiconductor devices by controlling the properties of semiconductor materials at the atomic or molecular level. The present invention further relates to the identification, fabrication, and utilization of improved materials used in the conduction paths of semiconductor devices.

Applicants hypothesize that certain superlattices described herein reduce the effective mass of charge carriers and thereby increase the mobility of charge carriers. However, applicants are not obsessed with that hypothesis. Effective mass is described by various definitions in the reference. Applicants used “conductivity reciprocal effective mass tensor”, M _e ⁻¹ and M _h ⁻¹ as an indicator that the effective mass was improved. The conductive inverse effective mass tensor M _e ^{−1 for} electrons and the conductive inverse effective mass tensor M _h ⁻¹ for holes are respectively defined as follows.

ここでfはフェルミ-ディラック分布関数、E_Fはフェルミエネルギー、Tは温度、E(k,n)は波数ベクトルk及びn番目のエネルギーバンドに対応する状態での電子のエネルギー、指数i及びjはガリレオ座標x,y,及びzを意味し、積分はブリュアンゾーン(B.Z.)全体で取られ、かつ総和は、電子のフェルミエネルギーよりも高いエネルギーを有するバンドについて、及び正孔のフェルミエネルギーよりも低いエネルギーを有するバンドについて、それぞれ取られている。

Where f is the Fermi-Dirac distribution function, E _F is the Fermi energy, T is the temperature, E (k, n) is the energy of the electron in the state corresponding to the wave vector k and the nth energy band, the indices i and j Means Galileo coordinates x, y, and z, the integral is taken over the entire Brillouin zone (BZ), and the summation is for bands with energies higher than the Fermi energy of the electrons and than the Fermi energy of the holes Each of the bands with low energy is taken.

  Applicants' definition of a conductive inverse effective mass tensor is such that the tensor component for the conductivity of the material increases as the corresponding component of the conductive inverse effective mass tensor increases. To reiterate, Applicants have found that the superlattice described herein has a conductive inverse effective mass tensor value, for example, the conductivity properties of a material, typically charge carrier transport in a preferred direction. I hypothesized that it would be set to improve. However, applicants are not obsessed with that hypothesis. The reciprocal of the appropriate tensor element is called the conductive effective mass. In other words, to evaluate the structure of the semiconductor material, the improved material is identified using the above-described conductive effective mass for electrons / holes calculated for the intended carrier transport direction.

  By using the above-mentioned index, a material having an improved band structure can be selected for a specific purpose. One such example is a superlattice material 25 (described in detail below) used in microelectromechanical system (MEMS) devices. Applications have developed where it is desirable to use relatively small devices such as variable capacitors, switches, and the like. By using a MEMS manufacturing process that forms very small moving parts on a substrate using a process that combines deposition, coating, or other additional processes, and selective etching and / or other lift-off processes. The element can be advantageously produced.

  Such a method ultimately forms a partially released or floating structure to allow mechanical movement. The electrostatic force may be generated by applying an electric field to conductors that are spaced apart from each other. One common MEMS structure is a switch provided by a conductive beam supported at one end. The opposite end may be coupled to an adjacent contact by an applied electrostatic force.

  Non-Patent Document 3 discusses various applications of MEMS devices. Non-Patent Document 3 describes that MEMS can provide passive elements such as switches, switchable (two-state) capacitors, variable capacitors (varactors), inductors, transmission lines, and resonators, for example. The technology states that it can be applied to radio frequency (RF) / microwave systems. Alternatively, these elements may be used in wireless applications that operate in the home / ground, in mobile, and in space, such as terminals, base stations and satellites.

  First, a typical MEMS device 20 (ie, a switch) having a superlattice 25 will be described with reference to FIGS. Although a preferred embodiment of a MEMS switch is described herein, it should be noted that the superlattice 25 can be used for many types of MEMS devices, including those already mentioned. I want. This will be apparent to those skilled in the art based on the disclosure herein.

  As described in Non-Patent Document 3, one of the physical laws underlying the operation of MEMS is the inverse piezoelectric effect. When a voltage is applied across the piezoelectric layer, the applied voltage causes the layer to mechanically deform. The resulting deformation can open a closed relay or close an open relay. A conventional method of making a MEMS switch is to make a relay using a cantilever structure. Such a structure may provide the desired function, but fabrication may be difficult.

  In the MEMS element 20, the superlattice 25 becomes piezoelectric due to its electrical polarity, thereby providing a movable part of the MEMS element as described above. Specifically, as shown, the MEMS element 20 further includes a substrate 21 such as a semiconductor substrate (eg, silicon, SOI, etc.). Grooves 22 are formed in the substrate 21 located around and immediately below the superlattice 25. Thereby, as shown, the superlattice portion is spaced from the substrate (ie, the lower surface of the substrate), and the dielectric anchor 23 secures the superlattice to the substrate on the bottom of the trench. Of course, other configurations may be used. This will be apparent to those skilled in the art.

  As shown in the figure, the MEMS element 20 may further include a drive circuit 24 for driving the superlattice 25, that is, the movable part, as instructed by the substrate 21. In the illustrated MEMS switch embodiment, the first conductive contact 26 is supported by the movable part, and the second conductive contact 27 is supported by the substrate 21 and aligned with the first conductive contact. (Figure 1). In addition, as shown, a first signal line 28, such as an RF signal line, for example, connects to the first conductive contact 26 and a second signal line 29 (which can also be an RF signal line). ) Is connected to the second conductive contact 27.

  A pair of bias voltage contacts 30, 31 that apply a bias voltage to the superlattice 25 is coupled to the superlattice 25 to move the movable part. Specifically, the bias voltage contacts 30, 31 may be conductive vias formed in the superlattice 25 as shown. However, in some embodiments, surface contact or metallization may be used. Conductive trace / metallization 32 connects bias voltage contact 30 to the positive connector of drive circuit 24 and conductive trace / metallization 33 connects bias voltage contact 31 to the negative connector of drive circuit 24 . As such, when the drive circuit 24 applies a bias voltage to the superlattice 25 via the bias voltage contacts 30 and 31, mechanical deformation of the superlattice occurs, which is indicated by the double-headed arrow in FIG. As indicated, the first electrical contact 26 varies toward the second electrical contact 27. This advantageously closes the switch and allows transmission of signals (eg RF signals) between the first signal line 28 and the second signal line 29. In addition, when the bias voltage is removed, the movable part moves the first contact 26 away from the second contact 27. Thereby, the switch is opened. This will be apparent to those skilled in the art.

An oxide film 34 (FIG. 2) is formed over the entire superlattice semiconductor region. The oxide film 34 is selectively removed in regions where contact with the superlattice material is desired. In the illustrated embodiment, the groove 22 and the side / bottom of the movable part are shown unprotected. However, in some embodiments, a dielectric layer such as SiO ₂ can be formed on the exposed semiconductor material if desired. This will be apparent to those skilled in the art.

  Referring now also to FIGS. 3 and 4, the superlattice 25 has a structure that is controlled at the atomic or molecular level and can be fabricated using known atomic or molecular layer deposition techniques. As can be understood by referring to the schematic cross-sectional view of FIG. 2 in detail, the superlattice 25 has a group 45a-45n consisting of a plurality of layers arranged in a stacked state.

  Each of the plurality of layers 45a-45n of the superlattice 25 includes a plurality of stacked basic semiconductor molecular layers 46, and energy thereon, defining each corresponding basic semiconductor portion 46a-46n. A band correction layer 50 is provided. The energy band correction layer 50 is illustrated as being dotted in FIG. 3 for the sake of clarity.

  As shown, the energy band correction layer 50 has a single non-semiconductor molecular layer constrained within the crystal lattice of the adjacent underlying semiconductor portion. That is, the opposing basic semiconductor molecular layers 46 in the adjacent groups 45a to 45n composed of a plurality of layers are chemically bonded together. For example, in the case of the silicon molecular layer 46, a part of silicon atoms contained in the semiconductor molecular layer located above the group 46a composed of a plurality of molecular layers is contained in the semiconductor molecular layer located below the group 46b. Covalently bonded to some of the silicon atoms. For this reason, the crystal lattice can be continued through a group of layers despite the presence of the (several) non-semiconductor molecular layers (for example, the (several) oxygen molecular layers). Of course, there is no complete or pure covalent bonding between opposing silicon layers 46 of adjacent groups 45a-45n. This is because a plurality of silicon atoms contained in each of these layers are bonded to non-semiconductor atoms (that is, oxygen in this embodiment). This is obvious to those skilled in the art.

  In other embodiments, two or more non-semiconductor layers can be used. By way of example, the number of non-semiconductor molecular layers in the energy band correction layer 50 may be preferably less than about 5 molecular layers to provide the desired energy band correction characteristics.

  When referring to non-semiconductor molecules or semiconductor molecules, it should be noted that it means that the material used for the molecular layer is a non-semiconductor or semiconductor when formed in bulk. That is, a monomolecular layer of a material such as a semiconductor does not necessarily have to exhibit the same characteristics when formed in a bulk or relatively thick state. This will be apparent to those skilled in the art.

  Applicants have found that due to the energy band modifying layer 50 and the adjacent underlying semiconductor portions 46a-46n, the superlattice 25 has a more suitable conductive effective mass of charge carriers than the prior art in which they did not exist. The hypothesis was that it would be smaller in the direction of the parallel layers. However, applicants are not obsessed with that hypothesis. From another viewpoint, the parallel direction is perpendicular to the stacking direction. The band modification layer 50 may also be such that the superlattice 25 has a common energy band structure. On the other hand, the band modifying layer 50 advantageously functions as an insulator between layers or regions located above and below the superlattice. Moreover, this structure also advantageously provides a barrier to the outflow or diffusion of dopants and / or materials between the layers that sandwich the superlattice 25. In addition, it was hypothesized that the superlattice 25 could be electrically polar so as to be piezoelectric. It will be apparent to those skilled in the art that piezoelectricity is achieved by having electrical polarity. However, applicants do not stick to this hypothesis.

  It was also hypothesized that the superlattice 25 provides higher charge carrier movement than the absence of a superlattice based on the reduced conductive effective mass. Of course, not all of the above properties associated with superlattice 25 need to be utilized in all applications. For example, in some applications, the superlattice 25 may utilize only its dopant block / insulating properties, or its improved mobility. Alternatively, in other applications, both its dopant block / insulating properties and its improved mobility would be utilized. This will be apparent to those skilled in the art.

  The cap layer 52 is present on the group of layers 45n located above the superlattice 25. The cap layer 52 may comprise 2 to 100 basic semiconductors, more preferably 10 to 50 molecular layers. Other thickness semiconductors may be used.

  Each basic semiconductor portion 46a-46n may comprise a basic semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, the term group IV semiconductor also includes group IV-IV semiconductors. This will be apparent to those skilled in the art. More specifically, the basic semiconductor may include at least one of silicon and germanium, for example.

  Each energy band modifying layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example. Non-semiconductors also aid in fabrication because they are thermally stable during the deposition of the next layer. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with a given semiconductor process. This will be apparent to those skilled in the art. More particularly, the basic semiconductor may comprise at least one of silicon and germanium, for example.

  It should be noted that the term “molecular layer” is meant to include monoatomic and monomolecular layers. It should also be noted that the energy band modifying layer 50 provided by the monolayer is meant to include molecular layers that do not occupy all possible sites. For example, referring in detail to the atomic scale diagram of FIG. 3, a 4/1 repeating structure is illustrated, using silicon as the basic semiconductor material and oxygen as the energy band modifying material. Only half of the possible sites for oxygen are occupied.

  In other embodiments and / or different materials, it is not necessarily a problem that this half is occupied, as will be apparent to those skilled in the art. In particular, even in this schematic, it can be seen that the individual oxygen atoms in a given molecular layer are not in precise positions along the plane. This is obvious to those skilled in the art. By way of example, a suitable occupation range is about 1/8 to 1/2 of all possible oxygen sites. Nevertheless, other numbers may be used in some embodiments.

  Silicon and oxygen are widely used at present in conventional semiconductor processes. Thus, manufacturers can readily use these materials described herein. Atomic or molecular deposition is also widely used today. Accordingly, a semiconductor device comprising a superlattice 25 according to the present invention can be readily implemented and implemented. This will be apparent to those skilled in the art.

  For example, for a superlattice such as a Si / O superlattice, the number of silicon molecular layers is preferably 7 or less, so that the energy band of the superlattice is generally common or relatively uniform. Hypothesized that the desired benefits would be realized. However, depending on the embodiment, eight or more layers may be used. The Si / O 4/1 repeat structure illustrated in FIGS. 2 and 3 was modeled to show improved electron and hole mobility in the X direction. For example, the calculated effective conductive mass for electrons is 0.26 (isotropic in bulk silicon), and for a 4/1 SiO superlattice in the X direction, the effective mass of electrons is 0.12, so the ratio is 0.46. Similarly, the calculation for holes yields a value of 0.36 for bulk silicon and a value of 0.16 for the 4/1 Si / O superlattice. As a result, the ratio is 0.44.

  Such a direction selectivity feature is desirable in certain semiconductor devices, but other devices have the advantage of more uniform mobility in any direction parallel to the group of layers. Will enjoy. It may be advantageous to increase the mobility of both electrons and holes, or it may be advantageous to increase the mobility of only one of these types of charge carriers. This will be apparent to those skilled in the art.

  The small conductive effective mass for the 4/1 Si / O embodiment according to the superlattice 25 is less than 2/3 of the conductive effective mass according to the prior art. This is true for both electrons and holes. It may be appropriate to dope the superlattice 25. However, depending on the particular type of MEMS device being mounted, and the location of the superlattice within the device, one or more groups of multiple layers 45 of the superlattice 25 may remain undoped. It should be noted that it is good. This is obvious to those skilled in the art.

  Still referring to FIG. 5, another embodiment of a superlattice 25 'having various properties is described in accordance with an embodiment of the present invention. In this embodiment, a repeating pattern of 3/1/5/1 is shown. More specifically, the basic semiconductor portion 46a 'at the bottommost portion has a trimolecular layer, and the basic semiconductor portion 46b' positioned next to the bottommost portion has a five molecular layer. This pattern is repeated throughout the superlattice 25 '. Each of the energy band modifying layers 50 'may include a single molecular layer. For such superlattices 25 'with Si / O, the improvement in charge carrier mobility is independent of the in-plane orientation of the layer. Other elements in FIG. 5 without specific mention are the same as those discussed above with reference to FIG. 3 and need not be discussed further here.

  In the device embodiments, all of the semiconductor portions 46a-46n on which the superlattice 25 is based may have the same number of molecular layers. In another device embodiment, at least some of the underlying semiconductor portions 46a-46n may have different numbers of molecular layer thicknesses. In another device embodiment, all of the semiconductor portions 46a-46n that form the basis of the superlattice 25 may have different numbers of molecular layer thicknesses.

  In FIGS. 5A-5C, band structures calculated using density functional theory (DFT) are given. It is well known to those skilled in the art that DFT estimates the absolute value of the band gap small. All bands above the gap will therefore be shifted by an appropriate “scissors correction”. However, the shape of the band is known to be quite reliable. The energy on the vertical axis must be interpreted taking this viewpoint into account.

  6A shows the bulk silicon band structure calculated for the γ point (G) (represented by a continuous line) and the band structure of the 4/1 Si / O superlattice 25 shown in FIG. 3 (dashed line). Is represented). The direction shown in the figure means a unit cell having a 4/1 Si / O structure, and does not represent a unit cell normally used for Si. Nonetheless, the (001) direction in the figure corresponds to the (001) direction of the unit cell conventionally used for Si, and thus indicates the position of the expected minimum value of the conduction band of Si. The (100) and (010) directions in the figure correspond to the (110) and (−110) directions of unit cells conventionally used for Si. It will be apparent to those skilled in the art that the silicon bands shown in the figure are folded to represent bands in the appropriate reciprocal lattice direction for the 4/1 Si / O structure.

  In contrast to bulk silicon (Si), the minimum of the conduction band of the 4/1 Si / O structure is located at the γ point, while the maximum of the valence band is what we call the Z point. It can be seen that it is located at the end of the Brillouin zone in the (001) direction. It can also be seen that the curvature of the conduction band minimum of the 4/1 Si / O structure is larger than the curvature of the Si conduction band minimum due to the band splitting due to the perturbation introduced by the added oxygen layer. right.

  FIG. 6B represents the band structure of the bulk silicon calculated for the Z point (represented by continuous lines) and the band structure of the 4/1 Si / O superlattice 25 (represented by broken lines). This figure shows that the curvature of the valence band in the (100) direction is improved.

  FIG. 6C shows the bulk silicon band structure calculated for the γ and Z points (represented by continuous lines) and the 5/1/3/1 Si / O band of the superlattice 25 ′ of FIG. Represents the structure (represented by a dashed line). Due to the symmetry of the 5/1/3/1 Si / O structure, the band structure calculated for the (100) direction and the band structure calculated for the (010) direction are equivalent. Therefore, it is expected that the conductive effective mass and mobility are isotropic in a plane parallel to the layer, that is, perpendicular to the (001) stacking direction. In the 5/1/3/1 Si / O structure example, note that both the conduction band minimum and valence band maximum are located at or near the Z point.

  Even though an increase in curvature indicates a decrease in effective mass, an appropriate comparison and distinction may be made through a conductive inverse effective mass tensor. Thereby, Applicants have further hypothesized that the 5/1/3/1 superlattice 25 'is substantially a direct transition bandgap. As will be apparent to those skilled in the art, an appropriate matrix element for optical transitions is another indicator that distinguishes the behavior of direct and indirect transition band gaps.

  Applicants have hypothesized that the lattice deformation described in the above paragraph makes the superlattice semiconductor material piezoelectric, unlike silicon, which is non-piezoelectric. However, applicants do not stick to this hypothesis.

  Various process flows for fabricating the superlattice 25 used in the MEMS element will now be described. In general, the MEMS element 20 is fabricated by forming a piezoelectric region or film having a superlattice 25 along the sidewalls of a groove. After the film is formed and metallized, the film is etched so that it is mechanically unsupported except for one end (that is, a groove 22 is formed under the film). . The one end is supported by the dielectric anchor 23 in the embodiment of FIGS.

Turning to FIGS. 7A-7F, the first process flow is described. This process procedure uses a deposition process that fills the etched trenches 70 in a silicon (SOI) substrate on an insulator. More specifically, the SOI substrate has a dielectric (eg, SiO ₂ ) layer 71 and a semiconductor (eg, silicon) layer 72 on the dielectric layer. An oxide film 73 that is a pad is formed on the semiconductor layer 72. Thereafter, a nitride (for example, silicon nitride) film 74 is deposited on the oxide film 73, and a photomask process and an etching process are performed, so that the groove 70 is formed.

  Subsequently, a superlattice 75 (eg, as described above) is selectively deposited on the walls of the trench 70. A dielectric 76, dielectric sandwich, or other material filling the trench is then deposited over the superlattice 75 and nitride film 74. Subsequently, a planarization process (FIG. 7D) is performed to remove all the material on the nitride film. Subsequently, the nitride film 74 and the oxide film 73 as a pad are removed, and then the semiconductor layer 72 is removed. The material used to fill trench 70 (ie dielectric 76) is etched. At the etched location, the substrate is ready for oxidation, contact formation, and release etching to produce the above-described MEMS device (or other MEMS device).

  Referring to FIGS. 8A-8F, there is further described another process flow that similarly uses the process of filling trenches formed by etching. Note that in these process flows and in the series of flow diagrams described below, the same components are designated by a number increased by 10 (eg, dielectric layer 71 is identical to dielectric layers 81, 91, etc.). Is). As such, these components are given an explanation only when they first appear.

  The process illustrated in FIGS. 8A-8F is identical to the method previously described in FIGS. 7A-7F. However, during the deposition of the superlattice 85, a single crystal superlattice semiconductor material is fabricated on the walls of the trench 80, while the polycrystalline superlattice semiconductor material 87 (shown in dots for clarity of illustration) Is different on the bottom of the trench and the nitride film 84. After the step of filling the trench and the planarization step (FIGS. 8C and 8D), a part of the polycrystalline silicon 87 is removed by etching, and the remaining polycrystalline silicon 87 is oxidized to form an oxide film 88. (Figure 8E). The nitride film 84 and the oxide film 83 as a pad are removed (that is, etched). Thus, the substrate is ready for oxidation, contact formation, and release etching as described above (FIG. 8F).

  Referring to FIGS. 9-12, the process flow of each independent lateral piezoelectric cantilever superlattice structure 4 made along each sidewall of the groove is described. More specifically, the process illustrated in FIGS. 9A-9F is the same as the process illustrated in FIGS. 7A-7F. However, the superlattice 95 is selectively deposited on the groove wall 90, as opposed to filling the entire groove.

  Another process that is identical to the process illustrated in FIGS. 9A-9F is illustrated in FIGS. 10A-10F. This process begins with a standard semiconductor substrate 102 as opposed to an SOI substrate. Another difference is that an oxide film is formed at the bottom of the trench 100 before selectively depositing the superlattice 105 on the trench sidewalls (FIG. 10B). The other processes illustrated in FIGS. 11A-11F are the same as the processes illustrated in FIGS. 8A-8F. However, the superlattice 115 is selectively deposited on the sidewalls of the trench 110 as opposed to filling the entire trench. Further, the other processes illustrated in FIGS. 12A-12G are the same as the processes illustrated in FIGS. 10A-10F. However, it differs in that it includes the deposition of polycrystalline silicon as described above in FIGS. 8A-8F. In all the process steps illustrated in FIGS. 9-12, a silicon dioxide layer is present on top of the piezoelectric superlattice before the contact openings are formed.

  Many modifications and other embodiments of the invention may occur to those skilled in the art having the benefit of the teachings set forth in the foregoing description and related figures. Therefore, it should be noted that the invention should not be limited to the specific embodiments disclosed, and that modifications and variations are included within the scope of the claims. .

1 is a top view of a micro electro mechanical system (MEMS) device according to the present invention having a superlattice. FIG. FIG. 2 is a cross-sectional view of the MEMS device of FIG. 1 taken along line 2-2. FIG. 2 is a schematic cross-sectional view in which the superlattice shown in FIG. 1 is considerably enlarged. FIG. 4 is a schematic perspective view of a part of the superlattice illustrated in FIG. 3 on an atomic scale. FIG. 3 is a schematic cross-sectional view, which is considerably enlarged, of another embodiment of a superlattice that can be used in the device of FIG. A graph of the band structure calculated at the γ point (G) for bulk silicon as a prior art and the band structure calculated at the γ point (G) for the 4/1 Si / O superlattice shown in FIG. It is a graph. FIG. 2 is a graph of a band structure calculated at a Z point for bulk silicon as a conventional technique, and a graph of a band structure calculated at a Z point for the 4/1 Si / O superlattice illustrated in FIG. Band structure graph calculated at both γ point (G) and Z point for bulk silicon as a prior art, and γ point (5/1/3/1 Si / O superlattice illustrated in FIG. 5 ( It is a graph of the band structure calculated at both G) and Z points. 1 is a series of cross-sectional views illustrating a method of fabricating a superlattice for a MEMS device according to the present invention. 1 is a series of cross-sectional views illustrating a method of fabricating a superlattice for a MEMS device according to the present invention. 1 is a series of cross-sectional views illustrating a method of fabricating a superlattice for a MEMS device according to the present invention. 1 is a series of cross-sectional views illustrating a method of fabricating a superlattice for a MEMS device according to the present invention. 1 is a series of cross-sectional views illustrating a method of fabricating a superlattice for a MEMS device according to the present invention. 1 is a series of cross-sectional views illustrating a method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention. FIG. 6 is a series of cross-sectional views illustrating yet another method of fabricating a superlattice for a MEMS device according to the present invention.

Claims (27)

A substrate; and at least one movable part supported by the substrate;
A microelectromechanical system (MEMS) device having
The at least one movable part has a superlattice having a plurality of groups each composed of a plurality of layers,
Each of the group of superlattice layers is internally constrained to a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion and a crystal lattice of adjacent basic semiconductor portions. Having at least one non-semiconductor molecular layer,
MEMS element.   The MEMS element according to claim 1, wherein the superlattice has a piezoelectric superlattice.   2. The MEMS element according to claim 1, further comprising: a driving device that drives the at least one movable part while being supported by the substrate. A first conductive contact supported by the at least one movable part; and a second conductive contact supported by the substrate and aligned with the first conductive contact;
The MEMS device according to claim 1, further comprising: A first radio frequency (RF) signal connected to the first conductive contact; and a second RF signal connected to the second conductive contact;
The MEMS device according to claim 1, further comprising:   2. The MEMS device according to claim 1, further comprising a pair of bias voltage contacts for applying a bias voltage to the superlattice for moving the at least one movable part.   2. The MEMS element according to claim 1, wherein the superlattice portion is provided at a distance from the substrate. A MEMS device having a dielectric anchor supported by a substrate,
The at least one movable part is supported by the dielectric anchor;
The MEMS device according to claim 1.   2. The MEMS element according to claim 1, wherein the basic semiconductor includes silicon.   2. The MEMS device according to claim 1, wherein the at least one non-semiconductor molecular layer contains oxygen.   2. The MEMS element according to claim 1, wherein the at least one non-semiconductor molecular layer has a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.   2. The MEMS device according to claim 1, wherein the at least one non-semiconductor molecular layer has a thickness of a monomolecular layer.   2. The MEMS element according to claim 1, wherein all of the basic semiconductor portions have the same molecular layer thickness as the number of layers.   2. The MEMS element according to claim 1, wherein at least a part of the basic semiconductor portion has a molecular layer thickness with a different number of layers.   2. The MEMS element according to claim 1, wherein opposing basic semiconductor portions included in adjacent groups composed of a plurality of layers of the at least one superlattice are chemically bonded together. A method of manufacturing a micro-electromechanical system (MEMS) device comprising:
Providing a substrate; and forming at least one movable part supported by the substrate;
Have
The at least one movable part has a superlattice having a plurality of groups each composed of a plurality of layers,
Each of the group of superlattice layers is internally constrained to a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion and a crystal lattice of adjacent basic semiconductor portions. Having at least one non-semiconductor molecular layer,
Method.   The method of claim 16, wherein the superlattice comprises a piezoelectric superlattice.   17. The method according to claim 16, further comprising providing a driving device that drives the at least one movable part while being supported by the substrate. Forming a first conductive contact supported by the at least one movable part; and forming a second conductive contact supported by the substrate and aligned with the first conductive contact. The step of:
17. The method of claim 16, further comprising: Forming a first radio frequency (RF) signal connected to the first conductive contact; and forming a second RF signal connected to the second conductive contact;
17. The method of claim 16, further comprising:   17. The method of claim 16, further comprising forming a pair of bias voltage contacts that apply a bias voltage to the superlattice to move the at least one movable part.   The method of claim 16, wherein the superlattice portion is spaced from the substrate. Forming a dielectric anchor supported by a substrate, further comprising:
The at least one movable part is supported by the dielectric anchor;
The method of claim 16. The basic semiconductor has silicon, and the at least one non-semiconductor molecular layer has oxygen,
The method of claim 16.   17. The method of claim 16, wherein the at least one non-semiconductor molecular layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.   17. The method of claim 16, wherein the at least one non-semiconductor molecular layer is a monolayer thickness. 17. The method of claim 16, wherein opposing basic semiconductor portions included in adjacent groups of layers of the at least one superlattice are chemically bonded together.

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