CN101257418B - Method and apparatus for generating error code and system for realizing error code insertion - Google Patents
Method and apparatus for generating error code and system for realizing error code insertion Download PDFInfo
- Publication number
- CN101257418B CN101257418B CN200810066444XA CN200810066444A CN101257418B CN 101257418 B CN101257418 B CN 101257418B CN 200810066444X A CN200810066444X A CN 200810066444XA CN 200810066444 A CN200810066444 A CN 200810066444A CN 101257418 B CN101257418 B CN 101257418B
- Authority
- CN
- China
- Prior art keywords
- error code
- data
- input
- output
- control command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The embodiment of the invention provides a device and a method for generating error code. The device includes an error code controller, an inverter and a multiplexor. The error code controller is used for outputting an error code control command which contains an error code generating command. The invention is used for receiving input data and outputting the inverse phase bit of the data. The multiplexor can outputs the inverse phase bit of the data when the error code control command is the error code generating command. The embodiment of the invention can control the error insertion accurately so as to perform reliability testing onto the communication device more precisely.
Description
Technical field
The present invention relates to the communication technology, especially about a kind of method and apparatus of error code generation and the system that realizes the error code insertion.
Background technology
In the reliability testing of communication equipment, the various interface of communication equipment is because deterioration or damage, can bring influence to the functional reliability of communication equipment, usually the deterioration of communication device interface or damage can to the data of process produce abnormal conditions such as out of order, delay, error code or shake, communication equipment requires still can reliably working under above-mentioned abnormal conditions.So, this need carry out the physically impaired simulation test of interface to communication equipment, that is to say, by analog interface deterioration or exception message that damage produced, communication equipment comes test communications equipment can identify this exception message, and can handle normal message, if can be distinguished exception message and normal message, and normal message handled, then this communication equipment has passed through reliability testing.We are example with the router, and the interface of router has a variety of, as POS (Packetover sonet/SDH) interface of various speed, Ethernet interface, the E1/E3/T1/T3 interface of low speed, synchronous/asynchronous serial port etc.The physical link that interconnects between the router is if deterioration or damage, then can cause the data of process produce abnormal conditions.
The method of the exception message that analog interface deterioration or damage at present produces the normally angle and the power of the sending and receiving device by adjusting microwave SDH is made error code, perhaps use adjustable light decay, the critical value that Output optical power is dropped to receiver sensitivity is made error code, but the bad control of accuracy that these two kinds of error codes insert.
Summary of the invention
In view of this, the main purpose of the embodiment of the invention provides accurately controlled apparatus and method of error code insertion amount.
The purpose of the embodiment of the invention is achieved through the following technical solutions:
The embodiment of the invention provides a kind of error code generation device, comprising: error code instruction control unit, inverter and multiplexer; Described error code instruction control unit is used to export the error code control command, and described error code control command comprises that producing error code instructs; Described inverter is used for receiving the input data, exports the antiphase of described data; Described multiplexer is used for exporting the antiphase of described data when described error code control command is instructed for producing error code.
The embodiment of the invention also provides a kind of error code production method, comprising: write the error code control command, described error code control command comprises that producing error code instructs; Input clock frequency according to the input data is exported described error code control command; When described error code control command is instructed for producing error code, then output and the anti-phase position of input data.
The embodiment of the invention also provides a kind of system that realizes that error code inserts, and comprising: receiver module is used to receive input traffic; The first optical interface module is used for described data flow is carried out opto-electronic conversion, exports second data flow; The first clock data processing module is used for described second data flow is carried out clock and data separating; The error code generation device, be used for the frequency of the described clock count frequency as clock counter is write the error code control command according to the default error rate, when described error code control command when producing the error code instruction, then output and the anti-phase position of input data, the data of error code are inserted in output; The second clock data processing module is used for the data of described clock and described insertion error code are synthesized, and exports the 3rd data flow; The second optical interface module is used for described the 3rd data flow is carried out the electric light conversion, and the data flow of error code is inserted in output; Output module is used to export the data flow of described insertion error code.
The embodiment of the invention can be inserted accurately control to error code, thereby more exactly communication equipment is carried out reliability testing.
Description of drawings
Fig. 1 is the flow chart of the error code production method of the embodiment of the invention;
Fig. 2 is the schematic diagram of the error code generation device of the embodiment of the invention two;
Fig. 3 is another schematic diagram of the error code generation device of the embodiment of the invention two;
Fig. 4 is the system schematic that the realization error code of the embodiment of the invention three inserts;
Fig. 5 is that the pos interface of the embodiment of the invention four is realized the system schematic that error code inserts;
Fig. 6 is that the Ethernet interface of the embodiment of the invention five is realized the system schematic that error code inserts.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, by the following examples, and, the embodiment of the invention is further described with reference to accompanying drawing.
Embodiment one, the embodiment of the invention provide a kind of error code production method, and referring to Fig. 1, Fig. 1 is the flow chart of the error code production method of the embodiment of the invention.Comprise:
101, write the error code control command, described error code control command comprises producing the error code instruction and not producing error code instructs;
The error code control command is relevant with the desired error rate.The error rate (BER:bit error) is to weigh the data index of transfer of data accuracy at the appointed time.Its expression digital system " faults occurs " in how many bit data in transmission course.If a faults in myriabit data, occurs, promptly the error rate be ten thousand/, i.e. 10E-4.For instance, we to wish to insert the error rate be 10
-3Error code, like this, when carrying out error code testing, to transmit 2
16=65536bit figure place is inserted the cycle as error code, and we transmit 65536bit and just need 65536*10 so
-3=66 error codes.We are used as 1 and produce the error code instruction, and 0 is used as and does not produce the error code instruction, and we need write 66 1, and other bits are 0, have so just realized having in the 65536bit figure place 66 to produce the error codes instruction, and other instruct for not producing error code.Vice versa, and we are used as 0 and produce the error code instruction, and 1 is used as and does not produce the error code instruction, and we need write 66 0, and other bits are 1, and same like this realization has 66 error codes in the 65536bit figure place.
102, export described error code control command according to the input clock frequency of input data;
When specific implementation of the present invention, we can select the identical clock counter of input clock frequency of count frequency and input data, like this, export the error code control command that writes according to the count frequency of clock counter, for example, the above-mentioned 65536bit figure place of mentioning.
103, when described error code control command is instructed for producing error code, then output and the anti-phase position of described input data.
When specific implementation of the present invention, we can select multiplexer to realize this function, and multiplexer MUX belongs to a kind of logical device, and it has a plurality of inputs but has only an output.M U X can select one as output from a plurality of inputs, this realizes by a control end.Control end can determine which the input linked output, we are the input of error code control command as control end, like this, when described error code control command when producing the error code instruction, then the multiplexer input selecting to link to each other with inverter is promptly exported error code as output.As mentioned above, if 0 be used as and produce the error code instruction, 1 is used as and does not produce the error code instruction, and then when the error code control command is 0, then the input that links to each other with inverter of multiplexer selection is as output.
104, when described error code control command is instructed for not producing error code, the normal position of then exporting described input data.
When described error code control command for not producing error code when instruction, then the multiplexer input selecting to link to each other with described reception input data is as output, i.e. normal of output.As mentioned above, if 0 be used as and produce the error code instruction, 1 is used as and does not produce the error code instruction, and when the error code control command was 1, then the multiplexer input selecting to link to each other with described reception input data was as output.
Embodiment two:
Present embodiment provides a kind of error code generation device, and referring to Fig. 2, Fig. 2 is the schematic diagram of the error code generation device of the embodiment of the invention two.Comprise: error code instruction control unit, inverter and multiplexer; Described error code instruction control unit is used to export the error code control command, and described error code control command comprises that producing error code instructs; Described inverter is used for receiving the input data, exports the antiphase of described data; Described multiplexer is used for exporting the antiphase of described data when described error code control command is instructed for producing error code.Described error code control command comprises that also not producing error code instructs; Correspondingly, described multiplexer is used for when described error code control command is instructed for not producing error code, the normal position of exporting described input data.
When specific implementation of the present invention, multiplexer MUX can be used as a kind of logical device, and it has a plurality of inputs but has only an output.MUX can select one as output from a plurality of inputs, this realizes by a control end.Control end can determine which the input linked output, so described multiplexer comprises a control end and at least two inputs and an output, one input is used for receiving the input data, at least other inputs connect an end of inverter, and the other end of described inverter is used to receive described input data; Described control end links to each other with described error code instruction control unit; Described error code instruction control unit is used to export the control end that the error code control command is given described multiplexer, and described error code control command comprises producing the error code instruction and not producing error code instructs;
Instruct for producing error code when the instruction that described control end receives, output is issued in the input of the end that then described multiplexer selection links to each other with inverter, the output error code.Instruct for not producing error code when the instruction that described control end receives, then described multiplexer selection is issued output with the input of an end of described reception data, normal yard of output.
Described error code instruction control unit is used for the count frequency output error code control command according to the clock control counter, and the count frequency of described clock control counter is identical with the input clock frequency of described input data.When specific implementation of the present invention, described error code instruction control unit comprises two inputs and an output at least; One input is used to import the error code control command; One input is used to connect clock counter; Described output is used for the count frequency output error code control command according to described clock control counter.One end of described input error code control command can be connected with CPU, by CPU input error code control command.
When specific implementation of the present invention, the error code instruction control unit can be used random access memory (RAM; Random Access Memory) realize the function of error code commands for controlling, be specially: the input of memory comprises two at least, for convenience, with 2 be example, input is A and B, the memory output is C.Input A cpu peripheral is used for writing the error code control command according to the error rate and error code insertion cycle; Input B external clock counter, the count frequency of described clock counter is with the incoming frequency of data; Output C is used for exporting the error code control command according to the count frequency of clock counter.Preferably, can be used as the error code instruction control unit with four port rams.We come for example with No. 2 multiplexer MUX, and 2 road MUX have two inputs, and wherein an input is used for receiving the input data; Another input is used to import the antiphase of data.How to import the antiphase of data, another input that common a kind of simple realization mode is MUX connects an end of inverter, and the other end of described inverter receives the input data; The output of 2 road MUX decides which input of selection to be linked output according to the output valve of the output C of RAM.So, when 2 road MUX select the end be connected with inverter input to output the time, then the antiphase of dateout has so just realized the error code insertion.Specifically can be referring to Fig. 3, Fig. 3 is another schematic diagram of the error code generation device of the embodiment of the invention two.
Embodiment three,
The embodiment of the invention provides a kind of system that realizes that error code inserts, and described system comprises the above-mentioned error code generation device of mentioning.Referring to Fig. 4, Fig. 4 is the system schematic that the realization error code of the embodiment of the invention three inserts.Comprise:
Receiver module is used to receive input traffic;
The first optical interface module is used for described data flow is carried out opto-electronic conversion, exports second data flow;
The first clock data processing module is used for described second data flow is carried out clock and data separating;
The error code generation device, be used for the frequency of the described clock count frequency as clock counter is write the error code control command according to the default error rate, when described error code control command when producing the error code instruction, then output and the anti-phase position of described data, the data of error code are inserted in output;
The second clock data processing module is used for the data of described clock and described insertion error code are synthesized, and exports the 3rd data flow;
The second optical interface module is used for described the 3rd data flow is carried out the electric light conversion, and the data flow of error code is inserted in output;
Output module is used to export the data flow of described insertion error code.
When specific implementation of the present invention, the first optical interface module and the second optical interface module can be integrated on the same optical interface circuit; The first clock data processing module and second clock data processing module also can be integrated on the same chip, for example can be integrated on the physical layer device.In addition; because it is a variety of that the interface of communication apparatus has, for example, the pos interface of various speed; Ethernet interface; the E1/E3/T1/T3 interface of low speed, synchronous/asynchronous serial port etc., herein, we are bright for instance with pos interface and Ethernet interface; the specific implementation of present embodiment; the implementation of other interfaces is similar with present embodiment, also within protection scope of the present invention, repeats no more.
Embodiment four:
We are that example describes with the pos interface, and another embodiment of the present invention provides pos interface to realize the system that error code inserts, and referring to Fig. 5, Fig. 5 is that the pos interface of the embodiment of the invention four is realized the system schematic that error code inserts.Concrete implementation comprises: receiver module is used to receive the POS data flow, and described POS data flow is realized sending to a POS Frame Handler after the opto-electronic conversion through the first optical interface module; The one POS Frame Handler extracts clock respectively and data send to error code insertion device; The error code generation device, be used for the frequency of described clock count frequency as clock counter, write the error code control command according to the default error rate, when described error code control command is instructed for producing error code, then output and the anti-phase position of described data, the data of error code are inserted in output, and the data of clock and input error code are sent to the 2nd POS Frame Handler; The specific implementation that the error code generation device inserts error code according to the count frequency of error code control command and clock counter repeats no more as mentioned above.
Send to the second optical interface module after the synthetic POS data of data of the 2nd POS Frame Handler with clock and insertion error code; The second optical interface module carries out the POS data that receive to send to output module after the electric light conversion, and output module output is exactly the POS data flow of inserting error code like this.
When specific implementation of the present invention, the first optical interface module and the second optical interface module can be integrated on the same optical interface circuit; The one POS Frame Handler and the 2nd POS Frame Handler also can be used as two modules and are integrated on the same POS Frame Handler.
Embodiment five:
We are that example describes with the Ethernet interface, and the embodiment of the invention five provides Ethernet interface to realize the system that error code inserts, and referring to Fig. 6, Fig. 6 is that the Ethernet interface of the embodiment of the invention five is realized the system schematic that error code inserts.Concrete implementation comprises: receiver module is used to receive ethernet data stream, and described ethernet data stream is realized sending to the first ethernet physical layer processor after the opto-electronic conversion through the first optical interface module; The first ethernet physical layer processor extracts clock respectively and data send to error code insertion device; The error code generation device, be used for the frequency of described clock count frequency as clock counter, write the error code control command according to the default error rate, when described error code control command is instructed for producing error code, then output and the anti-phase position of described data, the data of error code are inserted in output, and the data of clock and input error code are sent to the second ethernet physical layer processor; The specific implementation that the error code generation device inserts error code according to the count frequency of error code control command and clock counter repeats no more as mentioned above.
Send to the second optical interface module behind the synthetic Ethernet data of data of the second ethernet physical layer processor with clock and insertion error code; The second optical interface module carries out the Ethernet data that receives to send to output module after the electric light conversion, and output module output is exactly the ethernet data stream that inserts error code like this.
When specific implementation of the present invention, the first optical interface module and the second optical interface module can be integrated on the same optical interface circuit; The first ethernet physical layer processor and the second ethernet physical layer processor also can be used as two modules and are integrated on the same ethernet physical layer processor.
One of ordinary skill in the art will appreciate that all or part of step in the foregoing description method is to finish by the relevant hardware of program command, described program can be stored in the computer read/write memory medium, described storage medium can be ROM/RAM, magnetic disc, CD etc.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.
Claims (10)
1. an error code generation device is characterized in that, comprising:
Error code instruction control unit, inverter and multiplexer;
Described error code instruction control unit is used to export the error code control command, and described error code control command comprises producing the error code instruction and not producing error code instructs, and described error code control command writes to the error code instruction control unit according to the error rate and the error code cycle of inserting;
Described inverter is used for receiving the input data, exports the antiphase of described data;
Described multiplexer comprises a control end, at least two inputs and an output, wherein, have an input to receive the input data at least in described two inputs, also have an input to connect the output of inverter, described control end links to each other with described error code instruction control unit;
Instruct for producing error code when the instruction that described control end receives, the oppisite phase data that the input that then described multiplexer will link to each other with inverter receives is issued output, the output error code;
The instruction that receives when described control end is for producing the error code instruction, and then described multiplexer is issued output, normal yard of output with the data without anti-phase processing that the input of described reception input data receives.
2. device as claimed in claim 1 is characterized in that, described multiplexer is 2 path multiplexers.
3. device as claimed in claim 1, it is characterized in that, described error code instruction control unit is used for the count frequency output error code control command according to the clock control counter, and the count frequency of described clock control counter is identical with the input clock frequency of described input data.
4. device as claimed in claim 1, it is characterized in that, described error code instruction control unit comprises two inputs and an output at least, one input is used to import the error code control command, the described input that is used to import the error code control command is connected with CPU, by CPU input error code control command.
5. device as claimed in claim 4, it is characterized in that, described error code instruction control unit is a random access memory, described random asccess memory comprises two input A, B and an output C at least, input A cpu peripheral is used for writing the error code control command according to the error rate and error code insertion cycle; Input B external clock counter, the count frequency of described clock counter is with the incoming frequency of data; Output C is used for exporting the error code control command according to the count frequency of clock counter.
6. an error code production method is characterized in that, comprising:
Write the error code control command according to the error rate and the error code cycle of inserting to the error code instruction control unit, described error code control command comprises producing the error code instruction and not producing error code instructs;
Described error code instruction control unit is exported described error code control command according to the input clock frequency of input data;
When described error code control command was instructed for producing error code, then multiplexer was exported the oppisite phase data of inverter output as the dateout of described multiplexer, and described inverter is used for receiving the input data, exports the antiphase of described data;
When described error code control command was instructed for not producing error code, then multiplexer output was without the normal position of the described input data of inverter processing.
7. method as claimed in claim 6, it is characterized in that, described error code instruction control unit is a random access memory, described random asccess memory comprises two input A, B and an output C at least, input A cpu peripheral is used for writing the error code control command according to the error rate and error code insertion cycle; Input B external clock counter, the count frequency of described clock counter is with the incoming frequency of data; Output C is used for exporting the error code control command according to the count frequency of clock counter.
8. a system that realizes that error code inserts is characterized in that, comprising:
Receiver module is used to receive input traffic;
The first optical interface module is used for described data flow is carried out opto-electronic conversion, exports second data flow;
The first clock data processing module is used for described second data flow is carried out clock and data separating, and described data are as the input data of error code generation device;
The error code generation device comprises error code instruction control unit, inverter and multiplexer, and described error code generation device writes the error code control command to the error code instruction control unit with the frequency of the described clock count frequency as clock counter according to the default error rate; Described error code instruction control unit is used to export the error code control command to multiplexer, described error code control command comprises producing the error code instruction and not producing error code instructs, and described error code control command writes to the error code instruction control unit according to the error rate and the error code cycle of inserting; Described inverter is used for receiving the input data, exports the antiphase of described data; Described multiplexer comprises a control end, at least two inputs and an output, wherein, have an input to receive the input data at least in described two inputs, also have an input to connect the output of inverter, described control end links to each other with described error code instruction control unit; Instruct for producing error code when the instruction that described control end receives, the oppisite phase data that the input that then described multiplexer will link to each other with inverter receives is issued output, the output error code; The instruction that receives when described control end is for producing the error code instruction, and then described multiplexer is issued output, normal yard of output with the data without anti-phase processing that the input of described reception input data receives;
The second clock data processing module is used for the data of described clock and insertion error code are synthesized, and exports the 3rd data flow;
The second optical interface module is used for described the 3rd data flow is carried out the electric light conversion, and the data flow of error code is inserted in output;
Output module is used to export the data flow of described insertion error code.
9. system as claimed in claim 8 is characterized in that, described data flow is the POS data flow, and correspondingly, described first clock data processing module and described second clock data processing module are respectively a POS Frame Handler and the 2nd POS Frame Handler.
10. system as claimed in claim 8, it is characterized in that, described data flow is an ethernet data stream, and correspondingly, described first clock data processing module and described second clock data processing module are respectively the first ethernet physical layer processor and the second ethernet physical layer processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810066444XA CN101257418B (en) | 2008-03-31 | 2008-03-31 | Method and apparatus for generating error code and system for realizing error code insertion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810066444XA CN101257418B (en) | 2008-03-31 | 2008-03-31 | Method and apparatus for generating error code and system for realizing error code insertion |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101257418A CN101257418A (en) | 2008-09-03 |
| CN101257418B true CN101257418B (en) | 2011-03-30 |
Family
ID=39891908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810066444XA Expired - Fee Related CN101257418B (en) | 2008-03-31 | 2008-03-31 | Method and apparatus for generating error code and system for realizing error code insertion |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101257418B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111651311B (en) * | 2020-06-29 | 2023-07-11 | 中国人民解放军国防科技大学 | Configurable physical layer error code generating device, chip and equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1531226A (en) * | 2003-03-16 | 2004-09-22 | 华为技术有限公司 | Apparatus and method for analog optical signal code error |
| CN1738232A (en) * | 2004-08-18 | 2006-02-22 | 华为技术有限公司 | Intermittence error code real-time exact location system and method |
-
2008
- 2008-03-31 CN CN200810066444XA patent/CN101257418B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1531226A (en) * | 2003-03-16 | 2004-09-22 | 华为技术有限公司 | Apparatus and method for analog optical signal code error |
| CN1738232A (en) * | 2004-08-18 | 2006-02-22 | 华为技术有限公司 | Intermittence error code real-time exact location system and method |
Non-Patent Citations (1)
| Title |
|---|
| JP昭59-223862A 1984.12.15 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101257418A (en) | 2008-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112260689B (en) | Sampling calibration method for self-adaptive delay compensation serial ADC sampling system | |
| CN102301364B (en) | Cpu interconnecting device | |
| CN104022828B (en) | A kind of optical fiber data transmission method based on asynchronous communication model | |
| CN105357070A (en) | FPGA-based ARINC818 bus analysis and test apparatus | |
| CN111339003A (en) | General multichannel data sending system and method based on FPGA | |
| KR20150133220A (en) | Timestamp correction in a multi-lane communication link with skew | |
| CN106598889A (en) | SATA (Serial Advanced Technology Attachment) master controller based on FPGA (Field Programmable Gate Array) sandwich plate | |
| US7855969B2 (en) | Selective test point for high speed SERDES cores in semiconductor design | |
| CN103310850A (en) | Built-in self-test structure and method for on-chip network resource node storage device | |
| CN104714842A (en) | Method for repairing time sequence violation through adjusting clock path delay | |
| CN113190291A (en) | Configurable protocol conversion system and method based on network-on-chip data acquisition | |
| CN101149722A (en) | Method for executing CPU access to XFP optical module | |
| CN1757193B (en) | Techniques for automatic eye-diagram degradation for testing of a high-speed serial receiver | |
| CN110515879B (en) | Asynchronous transmission device and transmission method thereof | |
| CN109815073B (en) | PXI platform-based high-speed serial port SRIO test method | |
| CN101257418B (en) | Method and apparatus for generating error code and system for realizing error code insertion | |
| CN103186488B (en) | For voltage and the time sequence calibration method of memory system | |
| Laddha et al. | A review on serial communication by UART | |
| CN109800195A (en) | A kind of fibre channel adapter and data transmission method based on FPGA | |
| CN101599808B (en) | Method and system for testing cross board | |
| Laddha et al. | Implementation of serial communication using UART with configurable baud rate | |
| CN106603442A (en) | Cross-clock-domain high-speed data communication interface circuit of network on chip | |
| CN207367194U (en) | Multichannel AD acquisition and memory systems | |
| CN102882585B (en) | Data recording and playback device, system and method | |
| WO2022266959A1 (en) | Chip test circuit and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170825 Address after: 201, room 1, building A, No. 518053, front Bay Road, Qianhai, Shenzhen Shenzhen cooperation zone, Guangdong, China Patentee after: Shenzhen Zhitong World Technology Service Co. Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: Huawei Technologies Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110330 Termination date: 20200331 |