CN102882585B - Data recording and playback device, system and method - Google Patents
Data recording and playback device, system and method Download PDFInfo
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Abstract
The invention provides a data recording and playback system. The system comprises a signal input circuit, a signal output circuit, two memory units, a first FPGA (Field Programmable Gate Array), a second FPGA and an external recording device, wherein the first FPGA collaborates with the second FPGA. A caching structure is formed by the two memory units and the second FPGA, so as to perform ping-pang caching process on data. The memory capacity of the two memory units is determined by the first FPGA according to data rate of input data. The data recording and playback system can adapt to the data rate variation in the high-speed data transmission in a self-adaptive manner rather than modifying the system manually. In addition, the problems of system overflow and the like caused by input and output of instant high-speed signals can also be eliminated.
Description
Technical field
The present invention relates to digital communication technology field, more specifically, relate to and a kind of high-speed digital signal being recorded and data record and playback system and the method for playback.
Background technology
In high-speed digital communication system design process, for the ease of debugging and testing communication system, need to produce specific data and use this particular data that systematic function is debugged and tested.Simultaneously, efficiency when improving actual test and system-level uniting and adjustment examination, the signal of receiving in test process first need to be recorded as requested, and in the process of debugging, recorded data file is carried out to playback with the form of signal of telecommunication code speed as required, so that in debug process, find the problem existing in correction system also.
In remote sensing and satellite communication system, message transmission rate can change at 1 MBPS (Mbps) in the scope of 1000Mbps.In some main flow remote sensing and satellite communication system, message transmission rate has reached 100Mbps, or even the magnitude of Gigabits per second (Gbps), for example NASA and JAXA have had multiple satellite projects to realize the downlink transfer link of Gbps magnitude, and the transmission rate of China's Aerospace Satellite communication of future generation also will reach Gbps magnitude.
For the 1Mbps in adaptive remote sensing and satellite communication system is to the changes in data rate of 1000Mbps, in high-speed data recording and playback system that at present remote sensing and satellite communication system are used, manual change system need to be set conventionally.These manual change systems cause the complicated operation of high-speed data recording and playback system and easily occur mistake.In addition,, in current high-speed record and playback system, due to the input and output of moment high speed signal, cause system to produce the unstable situation such as overflow.
Summary of the invention
In view of the above problems, an object of the present invention is to provide a kind of data record and playback system and method, it is the variation in adaptation data transmission rate adaptively.
Another object of the present invention is to provide a kind of for realizing the device and method of high-speed data recording.
Another object of the present invention is to provide a kind of for realizing the device and method of high-speed data playback.
According to an aspect of the present invention, provide a kind of for realizing the device of high-speed data recording, comprising: signal input circuit, is configured to receive the baseband signal from outside input, and received baseband signal is converted to data; The one FPGA, be connected with described signal input circuit and be connected with external record device by bus, be configured to receive data from signal input circuit, and received data are continued to output to the 2nd FPGA, and receiving data from the 2nd FPGA, received data are carried out to record by bus transfer in external record device; The 2nd FPGA, be connected with a described FPGA, be configured to the data that receive from a FPGA to be written in a memory cell the first and second memory cell, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA, and in the time that the size of the data of inner buffer institute buffer memory reaches the first predetermined value, the data of inner buffer are sent to a FPGA; The first and second memory cell, be connected with described the 2nd FPGA, ping-pong buffer operation is carried out in wherein said two memory cell and described the 2nd FPGA cooperation, wherein, the memory capacity equal and opposite in direction of described the first and second memory cell, and set according to speed control the 2nd FPGA of input signal by a FPGA.
In one or more examples aspect above-mentioned, described device can also comprise: level and serial to parallel conversion unit, and for the signal of inputting from outside is carried out to level and serial to parallel conversion.
In one or more examples aspect above-mentioned, described device can also comprise: bridge, for realizing the bridge joint between the first bus and the second bus, wherein, a described FPGA is connected by the first bus with bridge, and described bridge is connected by the second bus with external record device.
In one or more examples aspect above-mentioned, described bridge can be PEX 8311.
According to a further aspect in the invention, provide a kind of for realizing the device of high-speed data playback, comprising: signal output apparatus, for received data are converted to baseband signal; The 3rd FPGA, be connected with described signal output apparatus and be connected with external record device by bus, be configured to read recorded data from external record device, and read data are transferred to the 4th FPGA constantly, and receiving data from the 4th FPGA, after being transferred to signal output apparatus and being converted to baseband signal according to assigned rate, received data carry out playback; The 4th FPGA, be connected with described the 3rd FPGA, be configured to the data that receive from the 3rd FPGA to be written in an internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA, and in the time that the size of the data of inner buffer institute buffer memory reaches the second predetermined value, the data of inner buffer are sent to the 3rd FPGA; And third and fourth memory cell, being connected with described the 4th FPGA, ping-pong buffer operation is carried out in wherein said the third and fourth memory cell and described the 4th FPGA cooperation.
In one or more examples aspect above-mentioned, described signal output apparatus can also comprise: level and parallel serial conversion unit, and for the data of exporting from the 3rd FPGA are carried out and string and level translation.
In one or more examples aspect above-mentioned, described device can also comprise: bridge, for realizing the bridge joint between the first bus and the second bus, wherein, described the 3rd FPGA is connected by the first bus with bridge, and described bridge is connected by the second bus with external record device.
In one or more examples aspect above-mentioned, described assigned rate is according to the playback rate information setting in received data readback instruction by the 3rd FPGA.
In one or more examples aspect above-mentioned, described assigned rate be by the 3rd FPGA according to the playback rate information in received data readback instruction, set by frequency synthesizer.
According to a further aspect in the invention, provide a kind of data record and playback system, comprising: be as above for realizing the device of high-speed record; As above for realizing high-speed playback device; And tape deck.
In one or more examples aspect above-mentioned, a described FPGA is identical with the 4th FPGA with described the 3rd FPGA respectively with the 2nd FPGA, and described the first and second memory cell are identical with described the third and fourth memory cell respectively.
According to a further aspect in the invention, a kind of data record method of being carried out by the device for realizing high-speed data recording is provided, comprise: receive the baseband signal of inputting from outside and be converted to data by signal input circuit, and by transfer of data to the FPGA after conversion; The one FPGA continues to output to the 2nd FPGA by received data; The 2nd FPGA is written to the data that receive from a FPGA in a memory cell the first and second memory cell, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA, and in the time that the size of the data of inner buffer institute buffer memory reaches the first predetermined value, the data of inner buffer are sent to a FPGA; And receiving data from the 2nd FPGA, the one FPGA carries out record by received transfer of data by bus in external record device, wherein, the memory capacity equal and opposite in direction of described the first and second memory cell, and set according to speed control the 2nd FPGA of input signal by a FPGA.
According to a further aspect in the invention, a kind of data readback method of being carried out by the device for realizing high-speed data playback is provided, comprise: the 3rd FPGA reads recorded data by bus from external record device, and read data are transferred to the 4th FPGA constantly; The 4th FPGA is written to the data that receive from the 3rd FPGA in an internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA, and in the time that the size of the data of inner buffer institute buffer memory reaches the second predetermined value, the data of inner buffer are sent to the 3rd FPGA; And receiving data from the 4th FPGA, the 3rd FPGA is transferred to received data signal output apparatus according to assigned rate and is converted to baseband signal and carries out playback.
Utilize above-mentioned data record and playback system, the changes in data rate in adaptive high speed data transfer adaptively, and without manual change system.In addition, can also eliminate due to moment high speed signal input and output cause system to produce the problem such as overflow.
In order to realize above-mentioned and relevant object, one or more aspects of the present invention comprise below by the feature that describes in detail and particularly point out in the claims.Explanation below and accompanying drawing describe some illustrative aspects of the present invention in detail.But, the instruction of these aspects be only some modes that can use in the variety of way of principle of the present invention.In addition, the present invention is intended to comprise all these aspects and their equivalent.
Brief description of the drawings
According to following detailed description of carrying out with reference to accompanying drawing, above and other object of the present invention, feature and advantage will become more apparent.In the accompanying drawings:
Fig. 1 shows according to the structured flowchart of the device for high-speed data recording of the embodiment of the present invention;
Fig. 2 shows the schematic diagram of a realization example of the signal input circuit of the device in Fig. 1;
Fig. 3 shows the bus control structure according to the embodiment of the present invention;
Fig. 4 shows according to the data buffer storage structure of the many speed of adaptation of the embodiment of the present invention;
Fig. 5 shows according to the structured flowchart of the device for high-speed data playback of the embodiment of the present invention;
Fig. 6 shows the schematic diagram of a realization example of the signal output apparatus of the device in Fig. 5;
Fig. 7 shows according to the structured flowchart of data record of the present invention and playback system;
Fig. 8 shows according to the schematic diagram of data record of the present invention and playback system example;
Fig. 9 shows according to the Bit Error Code Statistics structure in data record of the present invention and playback system;
Figure 10 show according to the embodiment of the present invention for carrying out the flow chart of method of high-speed data recording; With
Figure 11 show according to the embodiment of the present invention for carrying out the flow chart of method of high-speed data playback.
In institute's drawings attached, identical label is indicated similar or corresponding feature or function.
Embodiment
Various aspects of the present disclosure are described below.Should be understood that, instruction herein can be with varied form imbody, and disclosed any concrete structure, function or both are only representational in this article.Based on instruction herein, those skilled in the art should be understood that, an aspect disclosed herein can be independent of any other side and realize, and two or more aspects in these aspects can combine according to variety of way.For example, can use the aspect of any number described in this paper, implement device or hands-on approach.In addition, can use other structure, function or except one or more aspects described in this paper or be not the 26S Proteasome Structure and Function of one or more aspects described in this paper, realize this device or put into practice this method.In addition, any aspect described herein can comprise at least one element of claim.
Below in conjunction with brief description of the drawings according to embodiments of the invention.
Fig. 1 shows according to the structured flowchart of the device 100 for high-speed data recording of the embodiment of the present invention.
As shown in Figure 1, device 100 comprises signal input circuit 110, a FPGA 120, the 2nd FPGA130, the first internal storage location 140 and the second internal storage location 150.
Signal input circuit 110 is connected with a FPGA.In the time carrying out high-speed data recording, signal input circuit 110 is configured to receive the baseband signal from outside input, such as the ECL level signal from outside input, and received baseband signal is converted to data.Subsequently, by transfer of data to the FPGA 120 who obtains after conversion.
The level of the baseband signal that in an embodiment according to the present invention, signal input circuit 110 receives can require different from the level of the input signal of a FPGA 120.In addition, the baseband signal that signal input circuit 110 receives can be serial signal, instead of the desired parallel signal of the input signal of FPGA.In this case, signal input circuit 110 can also comprise level and serial to parallel conversion unit, for the baseband signal receiving from outside is carried out to level and serial to parallel conversion.Fig. 2 shows the configuration diagram of a realization example of signal input circuit in the time need to carrying out level and serial to parallel conversion to the baseband signal of outside input.
As shown in Figure 2, the level of the baseband signal of outside input is ECL level.In circuit structure, first, by EP 90 chips, the baseband signal of this outside input being carried out to level translation shown in figure 2, is LVPECL by the level translation of this baseband signal.Then, utilize FPGA (Field Programmable Gate Array) delay chip MC10EP195 to postpone the clock signal of EP 90 chips outputs, thereby realize strictly aliging of data and clock signal.The theoretical transmission rate of this chip is 1.2GHz, and delay precision is 10ps.Then, utilize MC10EP445 chip data are gone here and there and change, the data flow of maximum 1Gbps is become to the parallel data stream of the maximum 125MHz in 8 roads.Then, by MC100LVELT23 chip, MC10EP445 is converted to the parallel LVPECL signal obtaining and be converted into LVTTL level signal and give FPGA, MC100LVELT23 chip is that binary channels LVTTL drives chip, more than single channel transmission rate can reach 180MHz.FPGA receives by LVTTL interface.FPGA module (, a FPGA and the 2nd FPGA) adopts StratixII EP2S180F1020C3 chip, and maximum operating frequency reaches 550MHz, and wherein LVTTL interface transmission rate can reach 250Mbps.In addition, in this signal input circuit, also comprise MC100EPT22 chip, in order to realize the conversion of LVTTL level to LVPECL level, and realize the control to above chip.
The one FPGA 120 is configured to receive the data from signal input circuit output.In addition, a FPGA 120 is connected with the 2nd FPGA 130, for received data being continued to output to the 2nd FPGA130.And, the one FPGA 120 is also configured to be connected with external record device by bus, for in the time carrying out data record, from receiving the data that the 2nd FPGA 130 transmits, by bus, received transfer of data is carried out to record in external record device.
The 2nd FPGA 130 is connected with the second memory cell 150 with the first memory cell 140, and be configured to the data that receive from a FPGA 120 to be written in a memory cell the first memory cell 140 and the second memory cell 150, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA130.In addition,, in the time that the size of the data of inner buffer institute buffer memory reaches the first predetermined value, the 2nd FPGA 130 is configured to the data of inner buffer to be sent to a FPGA 120.
Described the first memory cell 140 and the second memory cell 150 are configured to data cached.In the present invention, the mode of utilizing two memory cell (being DDR2 internal memory in this example) to coordinate with the inside FIFO of the 2nd FPGA 130 is carried out ping-pong buffer operation, realizes the buffer memory of highspeed serial data stream.In the time carrying out ping-pong buffer operation, control the hardware time order of the first memory cell 140 and the second memory cell 150 by the 2nd FPGA 130.
For example, in the embodiment shown in fig. 1, inner buffer (, FIFO) the composition buffer structure of the first memory cell 140, the second memory cell 150 and the 2nd FPGA 130, and coordinate to come together to the operation of data-signal execution ping-pong buffer.Described ping-pong buffer operation refers in the time that a memory cell is carried out to write operation, and another memory cell is carried out to read operation.The first memory cell 140 and the second memory cell 150 are carried out and write and/or the switching sequence of read operation is controlled by the 2nd FPGA 130.In the time that the 2nd FPGA 130 carries out write operation and writes full this memory cell a memory cell, the 2nd FPGA 130 becomes this memory cell execution read operation.In the time that the 2nd FPGA 130 carries out read operation and reads empty this memory cell a memory cell, the 2nd FPGA 130 becomes this memory cell execution write operation.In addition, the memory capacity of the first memory cell 140 and the second memory cell 150 is set to equal and opposite in direction conventionally, and this size is set according to speed control the 2nd FPGA 130 of input signal by a FPGA 120.
In addition, in data recording process, data need to device 100 and external record device (for example, computer) between transmit, in order to reach the upper limit requirement of speed, device 100 can also comprise bridge 160, for realizing the bridge joint between the first bus and the second bus.In this case, conventionally need to be connected by the first bus (, local bus) between a FPGA 120 and bridge 160, and bridge 160 and external record device are (for example, computer) for example, be connected by the second bus (, PCI-E bus).In an example of the present invention, described bridge 160 can adopt the PEX8311 of PLX company.
Fig. 3 shows according to the diagram of an example of the bus control structure of the embodiment of the present invention.Figure 3 illustrates the relation of fpga chip, PEX8311 chip and PCI-E interface bus.PEX8311 is the bridging chip that a PCI-E bus of PLX company arrives local bus, supports the one-way transmission speed of 2.5Gbps, and data can be transmitted mutually by PCI-E bus and computer, meets rate requirement.The clock that local bus adopts 66M crystal oscillator to produce, data are with 32bit bit wide parallel transmission.
Fig. 4 shows according to the schematic diagram of an example of the data buffer storage structure of the many speed of adaptation of the embodiment of the present invention, adopt in the figure bridge PEX8311, in the time carrying out data record, the DMA transmission that first utilizes api function that PLX company provides to open PEX8311.
As shown in Figure 4, the work clock of DDR2 internal memory is 100MHz, is provided by FPGA.Owing to saving as 64bit highway width in DDR2, so more than the interface rate of DDR2 internal memory can reach 12Gbps, can tackle the serial data stream of 1Gbps completely.In the time carrying out data record, a FPGA 120 is constantly written to the 2nd FPGA 130, the two FPGA 130 by input data and writes data into and in DDR2 internal memory, carry out buffer memory.In the time that a slice DDR2 internal memory is written into, the 2nd FPGA 130 sense data and being cached in the FIFO of the 2nd FPGA 130 from another sheet DDR2 internal memory.In the time that the data in FIFO are greater than the first predetermined value, the data of buffer memory in FIFO are passed to a FPGA 120 by the 2nd FPGA 130.Subsequently, data are passed to bridge PEX8311 by a FPGA 120.Then, transmit by DMA, data-signal is for example transferred to, for example, in the assigned address (, specified file) of external record device (, computer) from bridge PEX8311.In addition,, in the time that of short duration obstruction appears in the DMA of PEX8311 transmission, the 2nd FPGA 140 reading out data from DDR2 internal memory also will suspend, but do not affect, the data of another piece internal memory be write.
In addition, can mate adaptively the changes in data rate of 1Mbps to 1000Mbps in order to make system, and can be because of the input and output of moment high speed signal, causing system to produce overflows, in the present invention, the memory capacity size (being buffer size) of the first memory cell 140 and the second memory cell 150 is set to set according to the data rate of input data, is set according to the data rate control of input signal the 2nd FPGA by a FPGA.For example, can be at outside tape deck end (for example, computer software end), the buffer size of needs being opened up according to input data rate is reached FPGA 120, the one FPGA 120 and then can be controlled the 2nd FPGA 130 and set buffer size by order.
In the present invention, buffer size is relevant with input data rate.In the time that input data rate is fast, buffer area is set to larger, thereby it is low and cause cache overflow to prevent that factor data from writing the momentary rate of PEX8311.In addition, buffer size also cannot be set to excessive, otherwise in the starting stage, and data are write full a slice DDR2 internal memory to be needed for a long time, will cause the FPGA for a long time cannot reading out data, affects record efficiency.
Fig. 5 shows according to the structured flowchart of the device 500 for high-speed data playback of the embodiment of the present invention.As shown in Figure 5, device 500 comprises signal output apparatus 510, the 3rd FPGA 520, the 4th FPGA530, the 3rd memory cell 540 and the 5th memory cell 550.
Signal output apparatus 510 is for being converted to baseband signal by received data.The 3rd FPGA 520 is connected with external record device by bus.In addition, the 3rd FPGA 520 is also connected with the 4th FPGA 530 with described signal output apparatus 510.In the time carrying out data readback, the 3rd FPGA 520 is configured to for example, read recorded data from external record device (, computer) by bus, and read data are transferred to the 4th FPGA constantly.In addition, receiving data from the 4th FPGA 530, the 3rd FPGA 520 is also configured to, by received data, be transferred to signal output apparatus 510 according to assigned rate, and carries out playback after being converted to signal by signal output apparatus 510.Described assigned rate is according to the playback rate information setting in received data readback instruction by the 3rd FPGA.In an example of the present invention, described assigned rate be by the 3rd FPGA according to the playback rate information in received data readback instruction, set by adjustable frequency synthesizer.
The 4th FPGA 530 is connected with the 4th memory cell 550 with described the 3rd FPGA 520, the 3rd memory cell 540.The inner buffer of the 4th FPGA 530 and the third and fourth memory cell composition buffer structure, carry out ping-pong buffer operation to data-signal.
The 4th FPGA 530 is configured to the data that receive from the 3rd FPGA 520 to be written in an internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA 530.In addition,, in the time that the size of the data of inner buffer institute buffer memory reaches the second predetermined value, the data of inner buffer are sent to the 3rd FPGA 520.
In another example of the present invention, device 500 can also comprise bridge 560, for realizing the bridge joint between the first bus and the second bus.In this case, between the 3rd FPGA 520 and bridge 560, for example, connect by the first bus (, local bus), and bridge 560 and external record device are (for example, computer) between by the second bus (for example, PCI-E bus) connect.
In addition, in another example of the present invention, device 500 can also comprise frequency synthesizer 570, the rate information of the data readback instruction receiving from the 3rd FPGA for basis, playback rate when data readback is set, the 3rd FPGA is transferred to the assigned rate of signal output apparatus.
In addition, in another example of the present invention, similar with the signal input circuit 110 in Fig. 1, data-signal output circuit 510 also can comprise and string and level translation unit, for the data of exporting from the 3rd FPGA are carried out and string and level translation, to be converted to baseband signal.
Fig. 6 shows according to the schematic diagram of the operation principle of data readback of the present invention and process.In this process, user for example, arranges playback rate by external record device end (, computer software end).In the time that the 3rd FPGA 520 receives data readback instruction, playback rate size information is passed to frequency synthesizer 570 by command word.Frequency synthesizer 570 is exported the sinusoidal signal of corresponding frequencies, by MAX9600 chip, sinusoidal signal is become to the clock signal of PECL level, the PECL of MAX9600 chip output is MC10EP446 through driving all the time chip MC100EP14 to give I/Q parallel-serial conversion chip again, it can carry out 1/8 frequency division according to input clock signal simultaneously, 1/8 fractional frequency signal obtaining is given after MC100LVELT23 chip becomes LVTTL level signal and passed to FPGA, realize 8 parallel-by-bit data outputs.In addition, in the circuit shown in Fig. 6, also adopt delay chip MC10EP195 that the serial i/Q signal of output is alignd with clock signal, I, the Q two paths of signals of the LVPECL clock signal of being exported by clock delay chip and chip MC10EP446 output are converted into NECL level signal through MC100EP91 chip.The end of playback section is MC10EP16 chip, in order to driving N ECL level signal.
Here be noted that above-mentioned the first predetermined value and the second predetermined value are set to fixed value conventionally, can be identical, also can be different.
Fig. 7 shows according to the structured flowchart of data record of the present invention and playback system 10.As shown in Figure 7, data record and playback system 10 comprise device 100 as above, device as above 500, tape deck 200.
Fig. 8 shows according to the schematic diagram of an example of data record of the present invention and playback system 10.In this example, a described FPGA is identical with the 4th FPGA with described the 3rd FPGA respectively with the 2nd FPGA, and described the first and second memory cell are identical with described the third and fourth memory cell respectively.In other words, a FPGA and the 3rd FPGA are same chips, and the 2nd FPGA and the 4th FPGA are same chips, and the first memory cell and the 3rd memory cell are same memory cell, and the second memory cell and the 4th memory cell are same memory cell.
In an example of the present invention, data record and playback system 10 can also have Bit Error Code Statistics function.Fig. 9 show according in the data record of the embodiment of the present invention and playback system for realizing the diagram of structure of Bit Error Code Statistics.
As shown in Figure 9, in a FPGA of data record and playback system 10, can also comprise: local M sequence generation module, synchronization module/XOR module and counting/Bit Error Code Statistics module.
M sequence generation module in local M sequence generation module and external circuit is all used shift register and XOR gate to form.
In the time that the M sequence that inputted outside M sequence generation module is generated is carried out Bit Error Code Statistics, received front several (number depends on the pattern of M sequence) data are input in the shift register of local M sequence generation module, register self circulation is obtained and the correct M sequence of channel synchronization.The M sequence of the M sequence that self-channel transmission is come and local generation synchronizes data and is carried out the XOR bit that locates errors by synchronization module.Then, error rate of system is added up and calculated to counting/Bit Error Code Statistics module to errored bit number.Finally, error rate numerical value comparison being obtained by Mailbox register is transferred to server, thus the statistics of the settling signal error rate.32 mailbox registers that Mailbox register can adopt PEX8311 to provide, the value of these registers can be read and write arbitrarily at software section Using API Function, also can in hardware, be read and write by local bus by FPGA according to certain sequential.
In the present invention, in carrying out high-speed data playback or record, the DMA data-transmission mode that utilizes PEX8311 to provide.Under DMA transmission mode, the api function that provides by PLX company starts and DMA transmission is set, and utilizes api function to obtain the data of record or spread out of the data of playback.
Data record according to the present invention and playback system are illustrated to Fig. 9 above with reference to Fig. 1.Data record according to the present invention and back method are described to Figure 11 below with reference to Figure 10.
Figure 10 show according to the embodiment of the present invention for carrying out the flow chart of method of high-speed data recording.
As shown in figure 10, in the time carrying out high-speed data recording, first, at step S1010, receive from the signal of outside input by signal input circuit, received signal is converted to data, then by transfer of data to the FPGA who obtains after conversion.Receiving from the data of signal input circuit transmission, at step S1020, a FPGA continues to output to the 2nd FPGA by received data.
Then, at step S1030, the data that the 2nd FPGA will receive from a FPGA be written in a memory cell the first and second memory cell, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA.Here, the memory capacity equal and opposite in direction of described the first and second memory cell, and set according to speed control the 2nd FPGA of input data by a FPGA.
Then,, at step S1040, judge whether the size of the data of inner buffer reaches the first predetermined value.In the time that the size of the data of inner buffer institute buffer memory reaches the first predetermined value, that is, the judged result of step S1040 when being, at step S1050, is sent to a FPGA by the data of inner buffer.Receiving data from the 2nd FPGA, at step S1060, a FPGA carries out record by received transfer of data by bus in external record device, completes thus high-speed data recording process.Exist bridge (for example, PEX8311), in situation, also need to utilize api function to open the DMA transfer function of PEX8311, and pass through local bus, import data into PEX8311 from a FPGA, then PEX8311 passes to external record device by data by PCI-E bus.
Figure 11 show according to the embodiment of the present invention for carrying out the flow chart of method of high-speed data playback.
In the time carrying out data readback, first, at step S1110, the 3rd FPGA reads recorded data by bus from external record device, and read data-signal is transferred to the 4th FPGA constantly.Exist bridge (for example, PEX8311), in situation, also need to utilize api function to open the DMA transfer function of PEX8311, and by PCI-E bus, import data into PEX8311 from external record device, then PEX8311 passes to the 3rd FPGA by data by local bus.
Receiving data from the 3rd FPGA, at step S1120, the data that the 4th FPGA will receive from the 3rd FPGA be written in an internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA.
Then,, at step S1130, judge whether the size of the data of inner buffer institute buffer memory reaches the second predetermined value.In the time that the size of the data of inner buffer institute buffer memory reaches the second predetermined value, the judged result of step S1130 is when being, and at step S1140, the data of inner buffer are sent to the 3rd FPGA by the 4th FPGA.
Receiving data from the 4th FPGA, at step S1150, the 3rd FPGA is transferred to signal output apparatus by received data according to assigned rate, and is converted to baseband signal and carries out playback.
Utilize data record of the present invention and playback system, by be provided for the memory capacity size (buffer size) of data cached memory cell according to the data rate of input data, changes in data rate in matched data transmission adaptively, and without manual change system is set.
In addition, be set to enough greatly by the cache size of buffer structure of the present invention, even if there are the input and output of moment high speed signal, can be because not overflowing obliterated data yet.
In addition, the method according to this invention can also be implemented as the computer program of being carried out by CPU.In the time that this computer program is carried out by CPU, carry out the above-mentioned functions limiting in method of the present invention.
In addition, said method step and system unit also can utilize controller (for example, processor) and realize for the computer readable storage devices of storing the computer program that makes controller realize above-mentioned steps or Elementary Function.
Although disclosed content shows exemplary embodiment of the present invention above, it should be noted that under the prerequisite of scope of the present invention that does not deviate from claim restriction, can carry out multiple change and amendment.Need not carry out with any particular order according to the function of the claim to a method of inventive embodiments described herein, step and/or action.In addition, although element of the present invention can be with individual formal description or requirement, also it is contemplated that multiple, unless be clearly restricted to odd number.
Be described although described each embodiment according to the present invention above with reference to figure, it will be appreciated by those skilled in the art that each embodiment that the invention described above is proposed, can also on the basis that does not depart from content of the present invention, make various improvement.Therefore, protection scope of the present invention should be determined by the content of appending claims.
Claims (9)
1. for realizing a device for high-speed data recording, comprising:
Signal input circuit, is configured to receive the baseband signal from outside input, and received baseband signal is converted to data;
The one FPGA, be connected with described signal input circuit and be connected with external record device by bus, be configured to receive data from signal input circuit, and received data are continued to output to the 2nd FPGA, and receiving data from the 2nd FPGA, received data are carried out to record by bus transfer in external record device;
The 2nd FPGA, be connected with a described FPGA, be configured to the data that receive from a FPGA to be written in a memory cell the first and second memory cell, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA, and in the time that the size of the data of inner buffer institute buffer memory reaches the first predetermined value, the data of inner buffer are sent to a FPGA;
The first and second memory cell, are connected with described the 2nd FPGA, and ping-pong buffer operation is carried out in wherein said two memory cell and described the 2nd FPGA cooperation; And
Bridge, for realizing the bridge joint between the first bus and the second bus, wherein, a FPGA is connected by the first bus with bridge, and described bridge is connected by the second bus with external record device,
Wherein, the memory capacity equal and opposite in direction of described the first and second memory cell, and set according to speed control the 2nd FPGA of input signal by a FPGA,
Described signal input circuit also comprises level and serial to parallel conversion unit, for the baseband signal of inputting from outside is carried out to level and serial to parallel conversion.
2. device as claimed in claim 1, wherein, described bridge is PEX 8311.
3. for realizing a device for high-speed data playback, comprising:
Signal output apparatus, for being converted to baseband signal by received data;
The 3rd FPGA, be connected with described signal output apparatus and be connected with external record device by bus, be configured to read recorded data from external record device, and read data are transferred to the 4th FPGA constantly, and receiving data from the 4th FPGA, after being transferred to signal output apparatus and being converted to baseband signal according to assigned rate, received data carry out playback;
The 4th FPGA, be connected with described the 3rd FPGA, be configured to the data that receive from the 3rd FPGA to be written in an internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA, and in the time that the size of the data of inner buffer institute buffer memory reaches the second predetermined value, the data of inner buffer are sent to the 3rd FPGA;
The third and fourth memory cell, is connected with described the 4th FPGA, and ping-pong buffer operation is carried out in wherein said the third and fourth memory cell and described the 4th FPGA cooperation; And
Bridge, for realizing the bridge joint between the first bus and the second bus, wherein, described the 3rd FPGA is connected by the first bus with bridge, and described bridge is connected by the second bus with external record device,
Wherein, described signal output apparatus also comprises level and parallel serial conversion unit, for the data of exporting from described the 3rd FPGA are carried out and string and level translation.
4. device as claimed in claim 3, wherein, described assigned rate is according to the playback rate information setting in received data readback instruction by the 3rd FPGA.
5. device as claimed in claim 4, wherein, described assigned rate be by the 3rd FPGA according to the playback rate information in received data readback instruction, set by frequency synthesizer.
6. data record and a playback system, comprising:
As the device as described in any one in claim 1 to 2;
As the device as described in any one in claim 3 to 5;
Tape deck.
7. data record as claimed in claim 6 and playback system, wherein, a described FPGA is identical with the 4th FPGA with described the 3rd FPGA respectively with the 2nd FPGA, and described the first and second memory cell are identical with described the third and fourth memory cell respectively.
8. a data record method of being carried out by device claimed in claim 1, comprising:
Receive the baseband signal of inputting from outside and be converted to data by signal input circuit, and by transfer of data to the FPGA through being converted to;
The one FPGA continues to output to the 2nd FPGA by received data;
The 2nd FPGA is written to the data that receive from a FPGA in a memory cell the first and second memory cell, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA, and in the time that the size of the data of inner buffer institute buffer memory reaches the first predetermined value, the data of inner buffer are sent to a FPGA; And
The one FPGA, receiving data from the 2nd FPGA, imports data into bridge by the first bus, and then bridge passes to data in external record device, to carry out record by the second bus,
Wherein, the memory capacity equal and opposite in direction of described the first and second memory cell, and set according to speed control the 2nd FPGA of input signal by a FPGA.
9. a data readback method of being carried out by device claimed in claim 3, comprising:
External record device imports data into bridge by the second bus, and then bridge passes to the 3rd FPGA by data by the first bus, and data are transferred to constantly the 4th FPGA by the 3rd FPGA;
The 4th FPGA is written to the data that receive from the 3rd FPGA in an internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA, and in the time that the size of the data of inner buffer institute buffer memory reaches the second predetermined value, the data of inner buffer are sent to the 3rd FPGA; And
Receiving data from the 4th FPGA, the 3rd FPGA is transferred to received data signal output apparatus according to assigned rate and is converted to baseband signal and carries out playback.
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| CN105141352B (en) * | 2015-07-24 | 2018-04-24 | 哈尔滨工业大学 | A kind of satellite high-speed digital transmission base band data Bit Error Code Statistics and frame sequence processing system and method |
| CN109492263B (en) * | 2018-10-17 | 2022-02-18 | 郑州云海信息技术有限公司 | High-speed cable model selection method and system |
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