CN101257027A - Nanometer silicon material lateral wall structure resetting flash memory and manufacturing and using method thereof - Google Patents
Nanometer silicon material lateral wall structure resetting flash memory and manufacturing and using method thereof Download PDFInfo
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- CN101257027A CN101257027A CNA2008100351178A CN200810035117A CN101257027A CN 101257027 A CN101257027 A CN 101257027A CN A2008100351178 A CNA2008100351178 A CN A2008100351178A CN 200810035117 A CN200810035117 A CN 200810035117A CN 101257027 A CN101257027 A CN 101257027A
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- 239000002210 silicon-based material Substances 0.000 title claims description 36
- 238000000034 method Methods 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000005543 nano-size silicon particle Substances 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 238000007667 floating Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000004069 differentiation Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
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Abstract
A lateral wall structure reset flash memory made by nano silicon material includes a substrate situated at the control gate, both side of the control gate has a lateral wall, the lateral wall has nano silicon layer, the nano silicon layer is overlapped by silicon dioxide, nano silicon and silicon dioxide in sequence. The flash memory unit area provided by the invention has micronization possibility.
Description
Technical field
The present invention relates to memory area, relate in particular to a kind of nanometer silicon material lateral wall structure resetting flash memory and making thereof, using method.
Background technology
Flash memory is a storage core flake products with fastest developing speed now, that market potential is arranged most.It in the communications field, consumer field, computer realm be widely used.The structure of flash memory is a lot, and traditional stack architecture (stackgate structure) is arranged, separate gate structure (split gate structure) or the like.Along with the development of technology, more high density, flash memory technology continues to bring out out more cheaply.
The floating grid structure flash memory of existing polycrystalline silicon material is when dwindling below 65nm, the also corresponding attenuate of insulating barrier around the polycrystalline silicon material floating boom, cause the problem (whole floating boom is a conductor) that electronics runs off easily in the floating boom, so the flash cell area is difficult to dwindle downwards.
Summary of the invention
Electronics runs off easily in the existing flash memory floating gate in order to solve in the present invention, the very difficult problem of dwindling downwards of flash cell area, a kind of nanometer silicon material lateral wall structure resetting flash memory is provided,, can have solved the problem that electronics all runs off easily in the floating boom because silicon nanoparticle insulate each other.
For solving the problems of the technologies described above, the present invention has adopted following technical scheme:
A kind of nanometer silicon material lateral wall structure resetting flash memory, comprise that substrate, be positioned at the control gate on the substrate, respectively there is a sidewall control gate both sides, the nanometer silicon layer is arranged on the described sidewall, and described nanometer silicon layer is formed by stacking successively by silicon dioxide, nano-silicon and silicon dioxide.
A kind of manufacture method of nanometer silicon material lateral wall structure resetting flash memory after the making of finishing lightly-doped source/drain region and control gate, also comprises the steps,
3.1, on the control gate side walls deposit nanometer silicon layer;
3.2, on the sidewall of control gate, form lateral wall floating gate by the method for etching;
3.3, carry out source/drain electrode particle again and inject and form transistorized source electrode and drain electrode.
A kind of memory cell wiring method of nanometer silicon material lateral wall structure resetting flash memory is realizing that the right side memory cell writes fashionablely, and the scope of grid voltage Vg is 6V to 30V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
A kind of memory cell wiring method of nanometer silicon material lateral wall structure resetting flash memory, realize the right side memory cell write fashionable, grid voltage Vg=10V, source voltage Vs=0V, drain voltage Vd=6V.
A kind of memory cell wiring method of nanometer silicon material lateral wall structure resetting flash memory is realizing that the left side memory cell writes fashionablely, and the scope of grid voltage Vg is 6V to 30V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
A kind of memory cell wiring method of nanometer silicon material lateral wall structure resetting flash memory, realize the left side memory cell write fashionable, grid voltage Vg=10V, source voltage Vs=6V, drain voltage Vd=0V.
A kind of memory cell of nanometer silicon material lateral wall structure resetting flash memory is read in method, and when realizing that memory cell is read in, the scope of grid voltage Vg is 1V to 20V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
A kind of memory cell of nanometer silicon material lateral wall structure resetting flash memory is read in method, when realizing that memory cell is read in, and grid voltage Vg=3V, source voltage Vs=2V, drain voltage Vd=0.1V.
A kind of memory cell zero clearing method of nanometer silicon material lateral wall structure resetting flash memory, when realizing the memory cell zero clearing, the scope of grid voltage Vg is-10V to 10V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
A kind of memory cell zero clearing method of nanometer silicon material lateral wall structure resetting flash memory, when realizing the memory cell zero clearing, grid voltage Vg=0V, source voltage Vs=drain voltage Vd=10V.
Because the present invention has adopted the nanometer silicon layer as the memory block, has strengthened the miniaturization possibility of flash cell area.
Description of drawings
Fig. 1 is the nanometer silicon material lateral wall structure resetting flash memory structure chart;
Fig. 2 writes schematic diagram for nanometer silicon material lateral wall structure resetting flash memory right side memory cell;
Fig. 3 writes schematic diagram for nanometer silicon material lateral wall structure resetting flash memory left side memory cell;
Fig. 4 reads in schematic diagram for the nanometer silicon material lateral wall structure resetting flash memory memory cell;
Fig. 5 is a nanometer silicon material lateral wall structure resetting flash memory memory cell zero clearing schematic diagram.
Embodiment
Below in conjunction with specific embodiment a kind of nanometer silicon material lateral wall structure resetting flash memory of the present invention (Side WallStructure Multi-Level Flash with Nanocrystal Si Film) is done detailed introduction, as shown in Figure 1, nanometer silicon material lateral wall structure resetting flash memory of the present invention comprises, substrate 1, be positioned at the control gate 4 on the substrate 1, respectively there is a sidewall control gate 4 both sides, left side wall 6, right side wall 5, the left side of substrate 1 is light dope source region 2, draw source electrode, the right side is lightly doped drain region 3, draw drain electrode, on left side wall 6 and the right side wall 5 nanometer silicon layer 7 is arranged all, wherein nanometer silicon layer 7 is by silicon dioxide, nano-silicon and silicon dioxide are formed by stacking successively.
The manufacture method of this nanometer silicon material lateral wall structure resetting flash memory after the making of finishing lightly-doped source/drain region and control gate, also comprises the steps:
2.1, on the control gate side walls deposit nanometer silicon layer;
2.2, on the sidewall of control gate, form lateral wall floating gate by the method for etching;
2.3, carry out source/drain electrode particle again and inject and form transistorized source electrode and drain electrode.
This nano silicon material side wall floating grid structure resetting flash memory, can realize resets writes, memory cell is read in functions such as memory cell zero clearing.
One, resets and write
A, right side memory cell write
As shown in Figure 2, at Vg=10V, Vs=0V, under the condition of Vd=6V, have electronics 100 to flow to drain electrode end from source terminal in the raceway groove, portions of electronics is injected in the right side wall nano-silicon floating boom (being the nanometer silicon layer) by the hot electron injection mode, realizes that the right side memory cell writes.
Wherein realizing that the right side memory cell writes fashionablely, the scope of grid voltage Vg is 6V to 30V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
B, left side memory cell write
As shown in Figure 3, at Vg=10V, Vs=6V under the condition of Vd=0V, has electronics to flow to source terminal from drain electrode end in the raceway groove, and portions of electronics is injected in the left side wall nanometer silicon layer by the hot electron injection mode, realizes that the left side memory cell writes.
Wherein realizing that the left side memory cell writes fashionablely, the scope of grid voltage Vg is 6V to 30V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
Two, memory cell is read in
As shown in Figure 4, at Vg=3V, Vs=2V, under the condition of Vd=0.1V, there is electric current to flow to drain electrode end in the raceway groove from source terminal, the nanometer silicon layer on right side has or not charge storage can influence the channel current size, when the nanometer silicon layer on right side has electric charge, electric current is very little in the raceway groove, otherwise when the nanometer silicon layer on right side did not have electric charge, electric current was very big in the raceway groove, setting the interior little current status of raceway groove is " 0 ", setting the interior current state of raceway groove is " 1 ", and the nanometer silicon layer has or not the state of charge storage to can be used as differentiation storage " 0 " or " 1 " information state like this, realizes the function of information stores.
Wherein when realizing that memory cell is read in, the scope of grid voltage Vg is 1V to 20V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
Same principle, left side nanometer silicon layer have or not the state of charge storage also to can be used as differentiation storage " 0 " or " 1 " information state, realize transistorized resetting (Multi-Level) memory function like this.
Three, memory cell zero clearing
As shown in Figure 5, at Vg=0V, under the condition of Vs=Vd=10V, the electronics that is stored in the nanometer silicon layer is excited to adjacent drain electrode end or source terminal under high electric field, flow away by drain electrode end or source terminal.
Wherein when realizing the memory cell zero clearing, the scope of grid voltage Vg is-10V to 10V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
This structure and general CMOS process compatible, simple in structure, transistorized both sides can be used as a memory cell respectively, and the effective storage unit area is very little, and the manufacturing process that can extend to below the 65nm gets on.
The invention provides a kind of nanometer silicon material lateral wall structure resetting flash memory, it adopts sidewall nanometer silicon layer as the memory block, injects by hot electron to make sidewall nanometer silicon layer iunjected charge, and then influences the transistor channel electric current.Sidewall nanometer silicon layer has or not charge storage to come perception by the size variation of transistor channel electric current like this.Sidewall nanometer silicon layer has or not the state of charge storage to can be used as differentiation storage " 0 " or " 1 " information state, realizes the function of information stores.
Claims (11)
1, a kind of nanometer silicon material lateral wall structure resetting flash memory comprises, substrate, is positioned at the control gate on the substrate, and respectively there is a sidewall control gate both sides, it is characterized in that, the nanometer silicon layer is arranged on the described sidewall.
2, a kind of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 1 is characterized in that, described nanometer silicon layer is formed by stacking successively by silicon dioxide, nano-silicon and silicon dioxide.
3, a kind of manufacture method of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 1 is characterized in that, after the making of finishing lightly-doped source/drain region and control gate, also comprises the steps:
3.1, on the control gate side walls deposit nanometer silicon layer;
3.2, on the sidewall of control gate, form lateral wall floating gate by the method for etching;
3.3, carry out source/drain electrode particle again and inject and form transistorized source electrode and drain electrode.
4, the memory cell wiring method of a kind of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 1, it is characterized in that, memory cell is write fashionable on the realization right side, the scope of grid voltage Vg is 6V to 30V, the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
5, the memory cell wiring method of a kind of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 4 is characterized in that, realize the right side memory cell write fashionable, grid voltage Vg=10V, source voltage Vs=0V, drain voltage Vd=6V.
6, the memory cell wiring method of a kind of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 1, it is characterized in that, memory cell is write fashionable on the left of realizing, the scope of grid voltage Vg is 6V to 30V, the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
7, the memory cell wiring method of a kind of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 6 is characterized in that, realize the left side memory cell write fashionable, grid voltage Vg=10V, source voltage Vs=6V, drain voltage Vd=0V.
8, the memory cell of a kind of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 1 is read in method, it is characterized in that when realizing that memory cell is read in, the scope of grid voltage Vg is 1V to 20V, the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
9, the memory cell of a kind of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 8 is read in method, it is characterized in that, and when realizing that memory cell is read in, grid voltage Vg=3V, source voltage Vs=2V, drain voltage Vd=0.1V.
10, the memory cell zero clearing method of a kind of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 1, it is characterized in that, when realizing the memory cell zero clearing, the scope of grid voltage Vg is-10V to 10V, the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.
11, the memory cell zero clearing method of a kind of nanometer silicon material lateral wall structure resetting flash memory as claimed in claim 10 is characterized in that, when realizing the memory cell zero clearing, and grid voltage Vg=0V, source voltage Vs=drain voltage Vd=10V.
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| CNA2008100351178A CN101257027A (en) | 2008-03-25 | 2008-03-25 | Nanometer silicon material lateral wall structure resetting flash memory and manufacturing and using method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044289B (en) * | 2009-10-20 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Green transistor, nano silicon ferroelectric memory and driving method thereof |
| CN103367452B (en) * | 2009-09-11 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Green transistors, resistance random access memory and driving method thereof |
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- 2008-03-25 CN CNA2008100351178A patent/CN101257027A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367452B (en) * | 2009-09-11 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Green transistors, resistance random access memory and driving method thereof |
| CN102044289B (en) * | 2009-10-20 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Green transistor, nano silicon ferroelectric memory and driving method thereof |
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Application publication date: 20080903 |