CN101295716A

CN101295716A - Channel type side wall floating grid structure flash memory and its use method

Info

Publication number: CN101295716A
Application number: CNA2008100351163A
Authority: CN
Inventors: 张博
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2008-03-25
Filing date: 2008-03-25
Publication date: 2008-10-29

Abstract

The invention relates to a channel type sidewall floating gate structure flash memory which comprises a substrate, a control gate formed inside the substrate leading out the gate, a channel slot formed around periphery of the control gate, a floating gate storing charge, which formed on the sidewall of the channel, a PN junction provided at the left side of the channel, which leads out a drain, and a PN junction provided at the right side of the channel, which leads out a source. The invention can solve the problems of breakover and reduced charge stored by floating gate caused from short channel effect of a traditional flash memory.

Description

Channel type side wall floating grid structure flash memory and using method thereof

Technical field

The present invention relates to memory area, relate in particular to channel type side wall floating grid structure flash memory and reading and writing thereof, zero clearing method.

Background technology

Flash memory is a storage core flake products with fastest developing speed now, that market potential is arranged most.It in the communications field, consumer field, computer realm be widely used.The structure of flash memory is a lot, and traditional stack architecture (stackgate structure) is arranged, separate gate structure (split gate structure) or the like.Along with the development of technology, more high density, flash memory technology continues to bring out out more cheaply.

Traditional stacking-type floating boom (SiO2/SiN/SiO2, being called for short ONO) structure flash memory is as shown in Figure 1, comprise substrate 9, be formed at the depletion layer 7 on the substrate, draw drain electrode, be formed at the PN junction 6 on the substrate 9, draw source electrode, and be formed at tunnel oxidation layer 5 on the substrate 9, be formed at the grid on the tunnel oxidation layer 5, described grid is formed by the deposit from bottom to top of storehouse floating boom 3, storehouse insulating barrier 2, control gate 1, and there are left insulative sidewall 8 and right insulative sidewall 5 in the side of grid.

The flash memory of traditional ONO storehouse floating gate structure is under the manufacturing process below the 0.09um, it is very little that storehouse floating boom live width can be processed, in case storehouse floating boom live width reaches below the 0.1um, but because the existence of short-channel effect, source electrode and drain electrode are easy to conducting (punchthrough), need the junction depth control of source electrode and drain electrode very accurate, difficulty of processing is very big.Because junction depth increases depletion layer with voltage to be increased, the operating voltage of source electrode and drain electrode also is restricted simultaneously.Limited storehouse floating boom live width like this reduces because of short-channel effect.In addition, because the reducing of storehouse floating boom live width, ONO storehouse floating boom charge stored reduces, and the capability of influence of raceway groove is weakened, and the variation that channel current is relative also diminishes, and distinguishes stored message capability simultaneously and reduces.

Summary of the invention

The present invention is for solving in the existing flash memory technology, and the shortcoming owing to short-channel effect causes conducting and floating boom stored charge to reduce provides a kind of channel type side wall floating grid structure flash memory.

A kind of channel type side wall floating grid structure flash memory, comprise, substrate, be formed at the control gate of substrate interior, control gate is drawn grid, is formed at the channel groove of the periphery of control gate, and the floating boom of stored charge is formed on the sidewall of described channel groove, there is a PN junction in the channel groove left side, draw drain electrode, there is a PN junction on the right side of channel groove, draws source electrode.

Wherein said channel groove comprises the insulation oxide that is formed at the control gate periphery, is formed at the storehouse floating boom of insulation oxide periphery, and the tunnel oxide that is formed at storehouse floating boom periphery.

A kind of memory cell wiring method of channel type side wall floating grid structure flash memory is realizing that memory cell writes fashionablely, and the scope of grid voltage Vg is 6V to 30V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.

A kind of memory cell wiring method of channel type side wall floating grid structure flash memory, realize memory cell write fashionable, grid voltage Vg=12V, source voltage Vs=0V, drain voltage Vd=0V.

A kind of memory cell zero clearing method of channel type side wall floating grid structure flash memory, when realizing the memory cell zero clearing, the scope of grid voltage Vg is-6V is to-30V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.

A kind of memory cell zero clearing method of channel type side wall floating grid structure flash memory, when realizing the memory cell zero clearing, grid voltage Vg=-10V, source voltage Vs=5V, drain voltage Vd=5V.

A kind of memory cell of channel type side wall floating grid structure flash memory is read in method, and when realizing that memory cell is read in, the scope of grid voltage Vg is 3V to 10V, and the scope of source voltage Vs is 0 to 10V, and the scope of drain voltage Vd is 0V to 10V.

A kind of memory cell of channel type side wall floating grid structure flash memory is read in method, when realizing that memory cell is read in, and grid voltage Vg=3V, source voltage Vs=0V, drain voltage Vd=3V.

The present invention has adopted channel type side wall floating grid to come store electrons, not only can effectively solve owing to the conducting phenomenon that short-channel effect brought, and can increase the stored charge ability of floating boom.

Description of drawings

Fig. 1 is traditional side wall floating grid structure flash memory schematic diagram;

Fig. 2 is the channel type side wall floating grid structure flash memory schematic diagram;

Fig. 3 writes schematic diagram for the channel type side wall floating grid structure flash memory memory cell;

Fig. 4 is a channel type side wall floating grid structure flash memory memory cell zero clearing schematic diagram;

Fig. 5 reads in schematic diagram for the channel type side wall floating grid structure flash memory memory cell.

Embodiment

Below in conjunction with a specific embodiment channel type side wall floating grid structure flash memory of the present invention is described in detail, as shown in Figure 2, comprise, substrate, be formed at the control gate 101 of substrate interior, control gate 101 is drawn grid, be formed at the channel groove of the periphery of control gate 101, the floating boom of stored charge is formed on the sidewall of described channel groove, there is a PN junction 103 in the channel groove left side, draw drain electrode, there is a PN junction 102 on the right side of channel groove, draws source electrode, and described channel groove comprises the gate oxide 104 that is formed at control gate 101 peripheries, be generally silicon dioxide (SiO2), the periphery of gate oxide 104 forms one deck silicon nitride (SiN) 105, and the periphery of silicon nitride 105 forms one deck tunnel oxidation layer, is generally silicon dioxide (SiO2).

This channel type side wall floating grid structure flash memory can realize that memory cell writes, function such as memory cell zero clearing and memory cell are read in.

One: memory cell writes

As shown in Figure 3, at Vg=12V,, Vs=0V, under the condition of Vd=0V, substrate electron is injected in the lateral wall floating gate of raceway groove by the mode of F-N tunnel break-through, thereby realizes that memory cell writes.

Wherein realizing that memory cell writes fashionablely, the scope of grid voltage Vg is 6V to 30V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.

Two: the memory cell zero clearing

As shown in Figure 4, at Vg=-10V, Vd=5V, under the condition of Vs=5V, the mode of electronics by the break-through of F-N tunnel that is stored in the trench sidewalls floating boom is excited in the raceway groove, flows away by substrate.

Wherein when realizing the memory cell zero clearing, the scope of grid voltage Vg is-6V is to-30V, and the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.

Three: memory cell is read in

As shown in Figure 5, at Vg=3V, Vd=3V, under the condition of Vs=0V, there is electric current to flow to drain electrode end along the channel groove sidewall in the raceway groove from source terminal, when having or not charge storage, the trench sidewalls floating boom can influence the channel current size, when the trench sidewalls floating boom has electric charge, electric current is very little in the raceway groove, otherwise when in the trench sidewalls floating boom during no electric charge, the interior electric current of raceway groove is very big, setting the interior little current status of raceway groove is " 0 ", setting the interior current state of raceway groove is " 1 ", and lateral wall floating gate has or not the state of charge storage to can be used as differentiation storage " 0 " or " 1 " information state like this, realizes the function of information stores.

Wherein when realizing that memory cell is read in, the scope of grid voltage Vg is 3V to 10V, and the scope of source voltage Vs is 0 to 10V, and the scope of drain voltage Vd is 0V to 10V.

Because this structure adopts the channel groove structure, when lateral dimension dwindles (short-channel effect), can increase the channel groove degree of depth, can avoid because the conducting that short-channel effect causes.Certainly, the channel groove degree of depth can not be too dark, otherwise transistor is oversize owing to the sidewall raceway groove, can't conducting.

In addition, because the sidewall raceway groove can not be subjected to laterally to dwindle to influence, keep certain-length, it can avoid the storehouse floating boom to dwindle the difficulty that causes the stored charge area to reduce and bring toward the following technology node of 90nm.

This patent adopts general CMOS technology, and is simple in structure, solved traditional storehouse floating gate structure faces short-channel effect and the minimizing of floating boom stored charge when the following technology node of 90nm dwindles difficulty.

Claims

1, a kind of channel type side wall floating grid structure flash memory, it is characterized in that, comprise that substrate, be formed at the control gate of substrate interior, control gate is drawn grid, be formed at the channel groove of the periphery of control gate, the floating boom of stored charge is formed on the sidewall of described channel groove, and there is a PN junction in the channel groove left side, draws drain electrode, there is a PN junction on the right side of channel groove, draws source electrode.

2, a kind of channel type side wall floating grid structure flash memory as claimed in claim 1, it is characterized in that, described channel groove comprises the insulation oxide that is formed at the control gate periphery, is formed at the storehouse floating boom of insulation oxide periphery, and the tunnel oxide that is formed at storehouse floating boom periphery.

3, the memory cell wiring method of a kind of channel type side wall floating grid structure flash memory as claimed in claim 1, it is characterized in that realizing that memory cell writes fashionablely, the scope of grid voltage Vg is 6V to 30V, the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.

4, the memory cell wiring method of a kind of channel type side wall floating grid structure flash memory as claimed in claim 3 is characterized in that, realize memory cell write fashionable, grid voltage Vg=12V, source voltage Vs=0V, drain voltage Vd=0V.

5, the memory cell zero clearing method of a kind of channel type side wall floating grid structure flash memory as claimed in claim 1, it is characterized in that, when realizing the memory cell zero clearing, the scope of grid voltage Vg is-6V is to-30V, the scope of source voltage Vs is 0 to 20V, and the scope of drain voltage Vd is 0V to 20V.

6, the memory cell zero clearing method of a kind of channel type side wall floating grid structure flash memory as claimed in claim 5 is characterized in that, when realizing the memory cell zero clearing, and grid voltage Vg=-10V, source voltage Vs=5V, drain voltage Vd=5V.

7, the memory cell of a kind of channel type side wall floating grid structure flash memory as claimed in claim 1 is read in method, it is characterized in that when realizing that memory cell is read in, the scope of grid voltage Vg is 3V to 10V, the scope of source voltage Vs is 0 to 10V, and the scope of drain voltage Vd is 0V to 10V.

8, the memory cell of a kind of channel type side wall floating grid structure flash memory as claimed in claim 7 is read in method, it is characterized in that, and when realizing that memory cell is read in, grid voltage Vg=3V, source voltage Vs=0V, drain voltage Vd=3V.