CN101252113A - 具相对应形状芯片座及接脚的导线架 - Google Patents

具相对应形状芯片座及接脚的导线架 Download PDF

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CN101252113A
CN101252113A CN 200810088324 CN200810088324A CN101252113A CN 101252113 A CN101252113 A CN 101252113A CN 200810088324 CN200810088324 CN 200810088324 CN 200810088324 A CN200810088324 A CN 200810088324A CN 101252113 A CN101252113 A CN 101252113A
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CN101252113B (zh
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杨肃泰
周光春
郑文吉
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Advanced Semiconductor Engineering Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

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Abstract

本发明是关于一种具相对应形状芯片座及接脚的导线架,包括:一芯片座及数个接脚。该芯片座用以承载一芯片,该芯片座具有数个侧边,所述侧边具有至少一个凹陷部及至少一突出部。所述接脚的水平高度与该芯片座相同,所述接脚包括数个第一接脚及数个第二接脚,所述第一接脚分别延伸至所述凹陷部内,所述第二接脚对应至所述突出部,所述第一接脚的长度大于所述第二接脚的长度。本发明的导线架利用具有凹陷部及突出部的侧边以及相对应长度的接脚,使得电性连接芯片与接脚或芯片座的导线能弹性调整,以节省成本。

Description

具相对应形状芯片座及接脚的导线架
技术领域
本发明是关于一种导线架,详言之,是关于一种具相对应形状芯片座及接脚的导线架。
背景技术
参考图1所示,习知的导线架10包括一芯片座11、二环形区12或13及数个接脚14、15等。该芯片座11用以承载芯片。二环形区12、13用于提供电源或接地。所述接脚14、15设置于芯片座11或环形区12或13的周边用以与芯片(图未示出)电性连接。
再者,该芯片座11是具有四侧边及四角隅,各侧边是呈平齐状,而各角隅则分别向外延伸形成一连接部16,以连接至该导线架10,且各连接部16在与该芯片座11连接的角隅处皆形成多次弯折再往外延伸。另外,由于该芯片座11的侧边仅呈平齐状,故对应于芯片座11的侧边,所述接脚14、15一般仅为相同的长度。因此,当习知的导线架10打线时,将无法调整连接该芯片及相对于在芯片座11侧边的所述接脚的导线长度,即所述导线具有一统一长度,因此无法减少导线的用量。
因此,有必要提供一种创新且具有进步性的导线架,以解决上述问题。
发明内容
本发明的目的在于提供一种具相对应形状芯片座及接脚的导线架,包括:芯片座及数个接脚。该芯片座用以承载芯片,该芯片座具有数个侧边,所述侧边具有至少一个凹陷部及至少一突出部。所述接脚的水平高度与该芯片座相同,所述接脚包括数个第一接脚及数个第二接脚,所述第一接脚分别延伸至所述凹陷部内,所述第二接脚对应至所述突出部,所述第一接脚的长度大于所述第二接脚的长度。
本发明的导线架利用具有凹陷部及突出部的侧边以及相对应长度的接脚,使得电性连接芯片与接脚或芯片座的导线能弹性调整,以节省成本。
附图说明
图1为习知的导线架的示意图;
图2为本发明的导线架的示意图;及
图3为沿图2的3-3剖面线的本发明具导线架的封装结构的示意图。
具体实施方式
请参阅图2,其显示本发明的导线架的示意图。本发明具相对应形状芯片座及接脚的导线架20包括:一芯片座21及数个接脚22、23。该芯片座21用以承载一芯片30,该芯片座21具有数个侧边,在本实施例中,该芯片座21具有四个侧边。每一侧边具有至少一个凹陷部211及至少一突出部212。
所述接脚22、23包括数个第一接脚22及数个第二接脚23,所述第一接脚22分别延伸至所述凹陷部211内,所述第二接脚23对应至所述突出部212,所述第一接脚22的长度大于所述第二接脚23的长度。在本实施例中,该凹陷部211及该突出部212是间隔设置,并且每一个第一接脚22延伸至一凹陷部211内;且每一第二接脚23对应至一突出部212。在其它应用实施例中,可以数个第一接脚延伸至一凹陷部内;且数个第二接脚对应至一突出部。
在本实施例中,每一个突出部211具有一接点区域213,用以利用一第一导线31电性连接至该芯片30。该接点区域213用以提供该芯片30的接地。所述第一接脚22与该芯片30经由数条第二导线32电性连接,所述第二接脚23与该芯片30经由数条第三导线33电性连接。第三导线33的长度大于第一导线31的长度,且第三导线33的长度大于第二导线32的长度。
本发明的导线架20利用具有凹陷部211及突出部212的侧边以及相对应长度的接脚22、23,使得电性连接芯片与接脚或芯片座的导线能弹性调整,以节省成本。
参考图3,其是沿图2的3-3剖面线的本发明具导线架的封装结构的示意图。配合参考图2及图3,本发明的封装结构40包括:一导线架20、一芯片30、数条导线31、32、33及封胶41。该导线架20包括:一芯片座21及数个接脚22、23。该芯片座21用以承载该芯片30,该芯片座21具有数个侧边,在本实施例中,该芯片座21具有四个侧边。每一侧边具有至少一个凹陷部211及至少一突出部212。另外,在本实施例中,该导线架20的所述接脚23的水平高度与该芯片座21相同。
配合参考图2及图3,所述导线31、32、33区分为:数条第一导线31、数条第二导线32及数条第三导线33。其中,所述第一导线31用以电性连接突出部211的接点区域213与该芯片30;所述第二导线32电性连接所述第一接脚22与该芯片30;所述第三导线33电性连接所述第二接脚23与该芯片30。第三导线33的长度大于第一导线31的长度,且第三导线33的长度大于第二导线32的长度。
因此,本发明的封装结构40利用具有凹陷部211及突出部212的侧边以及相对应长度的接脚22、23,使得电性连接芯片与接脚或芯片座的导线能弹性调整,以节省封装成本。
惟上述实施例仅为说明本发明的原理及其功效,而非限制本发明。本发明所属技术领域中具通常知识者对上述实施例所做的修改及变化仍不违背本发明的精神。本发明的权利范围应如权利要求所列。

Claims (14)

1.一种具相对应形状芯片座及接脚的导线架,包括:
芯片座,用以承载芯片,该芯片座具有数个侧边,所述侧边具有至少一个凹陷部及至少一突出部;及
数个接脚,所述接脚的水平高度与该芯片座相同,所述接脚包括数个第一接脚及数个第二接脚,所述第一接脚分别延伸至所述凹陷部内,所述第二接脚对应至所述突出部,所述第一接脚的长度大于所述第二接脚的长度。
2.如权利要求1所述的导线架,其中该凹陷部及该突出部是间隔设置。
3.如权利要求1所述的导线架,其中每一个第一接脚延伸至一凹陷部内,以及,每一个第二接脚对应至一突出部。
4.如权利要求1所述的导线架,其中数个第一接脚延伸至一凹陷部内。
5.如权利要求1所述的导线架,其中数个第二接脚对应至一突出部。
6.如权利要求1所述的导线架,其中每一个突出部具有一接点区域,用以与第一导线电性连接至该芯片。
7.如权利要求1所述的导线架,其中所述第一接脚与该芯片经由数条第二导线电性连接,所述第二接脚与该芯片经由数条第三导线电性连接,第三导线的长度大于第二导线的长度。
8.一种具导线架的封装结构,包括:
具相对应形状芯片座及接脚的导线架,包括:
芯片座,具有数个侧边,所述侧边具有至少一个凹陷部及至少一突出部;及
数个接脚,所述接脚的水平高度与该芯片座相同,所述接脚包括数个第一接脚及数个第二接脚,所述第一接脚分别延伸至所述凹陷部内,所述第二接脚对应至所述突出部,所述第一接脚的长度大于所述第二接脚的长度;
芯片,设置于该芯片座;及
数条导线,所述导线包括:数条第一导线、数条第二导线及数条第三导线,其中,所述第一导线用以电性连接突出部与该芯片;所述第二导线电性连接所述第一接脚与该芯片;所述第三导线电性连接所述第二接脚与该芯片。
9.如权利要求8所述的封装结构,其中该凹陷部及该突出部是间隔设置。
10.如权利要求8所述的封装结构,其中每一个第一接脚延伸至一凹陷部内,以及每一个第二接脚对应至一突出部。
11.如权利要求8所述的封装结构,其中数个第一接脚延伸至一凹陷部内。
12.如权利要求8所述的封装结构,其中数个第二接脚对应至一突出部。
13.如权利要求8所述的封装结构,其中每一个突出部具有接点区域,该第一导线用以电性连接该接点区域与该芯片。
14.如权利要求8所述的封装结构,其中第三导线的长度大于第一导线的长度,且第三导线的长度大于第二导线的长度。
CN 200810088324 2008-03-26 2008-03-26 具相对应形状芯片座及接脚的导线架以及相应的封装结构 Active CN101252113B (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447609A (zh) * 2019-08-29 2021-03-05 新唐科技股份有限公司 感测器以及集成电路模块

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447609A (zh) * 2019-08-29 2021-03-05 新唐科技股份有限公司 感测器以及集成电路模块
CN112447609B (zh) * 2019-08-29 2024-04-09 新唐科技股份有限公司 感测器以及集成电路模块

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