CN101236939A - 半导体封装装置 - Google Patents

半导体封装装置 Download PDF

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CN101236939A
CN101236939A CNA2008100812901A CN200810081290A CN101236939A CN 101236939 A CN101236939 A CN 101236939A CN A2008100812901 A CNA2008100812901 A CN A2008100812901A CN 200810081290 A CN200810081290 A CN 200810081290A CN 101236939 A CN101236939 A CN 101236939A
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electronic component
semiconductor encapsulation
encapsulation device
layer
substrate
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吴家福
李政颖
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开了一种半导体封装装置，其包含第一封装体、第一重布线层及第二重布线层。第一封装体具有第一基板及第一电子元件。第一电子元件设置于第一基板的第一容置空间中。第一重布线层设置于第一基板及第一电子元件的一表面，而第二重布线层设置于第一基板及第一电子元件的另一表面。本发明能够不增加尺寸即能够增加输入/输出埠的数量，以提高半导体封装装置的效率。

Description

半导体封装装置
技术领域
本发明涉及一种半导体封装装置，特别涉及一种具有重布线层的半导体封装装置。
背景技术
随着电子产品以小型化及高效率为导向，在半导体的技术发展中，通过提高半导体封装装置的容量及性能，以符合使用者的需求。因此，多芯片模块化(multichip module)成为近年来研究焦点之一，其将两个或多个芯片以堆叠方式形成一半导体封装装置。由此，将具有不同功能的芯片整合至半导体封装装置。此外，多芯片模块化可以减少芯片间连接电路的长度，而降低信号延迟时间及存取时间。
请参照图1所示，已知的半导体封装装置1包含一封装体11、一封装体12、多个导电元件13及多个接合垫14。其中，封装体11通过这些导电元件13及这些接合垫14电性连接至封装体12。
封装体11包括一电路板111、一芯片112及一绝缘层113。芯片112的一表面设置多个接合垫115，并通过多条金属导线114将多个接合垫115电性连接至电路板111，以使封装体11与封装体12之间电性连通。此外，绝缘层113用以包覆芯片112及部分的电路板111。
封装体12包括一电路板121、一芯片122及一绝缘层123。芯片122的一表面设置多个接合垫125，并通过多条金属导线124将多个接合垫125电性连接至电路板121。此外，绝缘层123用以包覆芯片122及部分的电路板121。
然而，由于电子产品的功能不断地增加，使得芯片112及芯片122的计算量急遽增加，而芯片112及芯片122内部电路亦日趋复杂。此即意味着芯片的输入/输出埠(I/O port)将需要更多，势必也将会增加芯片112及芯片122或封装体11及封装体12的尺寸。因此，如何在不增加甚至可缩小尺寸之前提下，能够使半导体封装装置具有更强大的功能，以提升半导体封装装置的效率，实属当前重要课题之一。
发明内容
有鉴于上述课题，本发明的目的为提供一种能够不增加尺寸即能够增加输入/输出埠的数量，以提高效率的半导体封装装置。
缘是，为达上述目的，本发明提供一种半导体封装装置包含第一封装体、第一重布线层及第二重布线层。第一封装体具有第一基板及第一电子元件，且第一电子元件设置于第一基板的第一容置空间中。第一重布线层设置于第一基板及第一电子元件的一表面，而第二重布线层设置于第一基板及第一电子元件的另一表面。
承上所述，因依据本发明的半导体封装装置通过配置于基板及封装体表面的重布线层，使得本发明不仅可以在基板及电子元件的一表面处设置接合垫，以增加输入/输出埠的数量；也可以在基板及电子元件的另一表面处设置接合垫，以供堆叠其他封装体于其上。由此，可增加半导体封装装置上下表面的输入/输出埠，以供解决习用基板表面被电子元件占用却无法设置输入/输出埠的问题。
附图说明
图1为显示已知半导体封装装置的一示意图；
图2为显示依据本发明第一实施例的半导体封装装置的一示意图；
图3为显示依据本发明第二实施例的半导体封装装置的一示意图；
图4为显示依据本发明第三实施例的半导体封装装置的一示意图；以及
图5为显示依据本发明第四实施例的半导体封装装置的一示意图。
附图标记说明
1：半导体封装装置
11、12、21、24、31、41：封装体
111、121：电路板
112、122：芯片
113、123：绝缘层
114、124：导线
115、125：接合垫
13、22、25：导电元件
14、23、26：接合垫
2、3、4、5：半导体封装装置
211、241：基板
212、242、312、411：电子元件
213、243：容置空间
214：导电贯孔
L1、L2、L3、L4：重布线层
S21、S23：内壁
S22、S24：侧表面
311：载板
313：封胶
412：绝缘胶
413、L5：散热层
具体实施方式
以下将参照相关图示，说明依据本发明优选实施例的半导体封装装置。
请参照图2所示，本发明第一实施例的一半导体封装装置2包含第一重布线层L1、第二重布线层L2及第一封装体21。
第一封装体21具有第一基板211及第一电子元件212。第一基板211具有至少第一容置空间213，且第一容置空间213的一侧边具有第一内壁S21。第一电子元件212设置于第一容置空间213中，且第一电子元件212具有与第一内壁S21对应的第一侧表面S22。其中，第一基板211为一电路板，其例如是一多层电路板。第一重布线层L1设置于第一基板211及第一电子元件212的一表面，而第二重布线层L2设置于第一基板211及第一电子元件212的另一表面。在本实施例中，半导体封装装置2还包含多个第一导电元件22及多个第一接合垫23。其中，这些第一导电元件22与第一重布线层L1电性连接，而第二重布线路层L2包含这些第一接合垫23。
在本实施例中，第一重布线层L1、第一基板211、第一电子元件212及第二重布线层L2可整合为一超薄基板，而第一容置空间213即为一贯穿孔(through hole)。
以下，将说明以第一封装体21为基础，堆叠与第一封装体21具有相同结构或是不同结构的封装体。请继续参照图2所示，本实施例的半导体封装装置2还包含第二封装体24、第三重布线层L3、第四重布线层L4、多个第二导电元件25及多个第二接合垫26。其中，这些第二导电元件25分别设置于相对应的这些第一接合垫23及第二封装体24之间。
请继续参照图2所示，第二封装体24具有第二基板241及第二电子元件242。第二基板241具有第二容置空间243，且第二容置空间243的一侧边具有第二内壁S23。其中，第二基板241为一电路板，其例如是一多层电路板。第二电子元件242设置于第二容置空间243中，且第二电子元件242具有与该第二内壁S23对应的第二侧表面S24。
此外，为了使第一电子元件212及第二电子元件242能更准确且快速地分别嵌合至第一容置空间213中及第二容置空间243中，因此，第一内壁S21、第一侧表面S22、第二内壁S23及第二侧表面S24可为一斜面。
在本实施例中，第一电子元件212及第二电子元件242可分别为一有源芯片或一整合型无源元件(Integrated Passive Device，IPD)。
请继续参照图2所示，第三重布线层L3设置于第二基板241及第二电子元件242的一表面，且第三重布线层L3与多个第二导电元件25电性连接。此外，上述的各第一导电元件22及各第二导电元件25分别为一导电锡球。
第四重布线层L4设置于第二基板241及第二电子元件242的另一表面，且第四重布线层L4还包含这些第二接合垫26。由此，本发明的半导体封装装置2可以依据使用者的需求，继续堆叠相同结构或不相同结构的封装体。
在本实施例中，第三重布线层L3、第二基板241、第二电子元件242及第四重布线层L4可整合为一超薄基板，而第二容置空间243即为一贯穿孔(through hole)。
此外，在本实施例中，第一重布线层L1与第二重布线层L2之间，以及第三重布线层L3与第四重布线层L4之间设置有多个导电贯孔(via)214，使得上述的重布线层可以相互传递资讯。
请参照图3所示，本发明第二实施例的一半导体封装装置3包含第一封装体21、第二封装体24、第一重布线层L1、第二重布线层L2、第三重布线层L3、一散热层L5、多个第一导电元件22、多个第二导电元件25及多个第一接合垫23。
请同时参照图2所示，在图2及图3中，元件具有相同编号者，具有相同的耦接关系与功能，在此不再赘述。在本实施例中，散热层L5提供半导体封装装置2的一散热路径。此外，在本实施例中，散热层L5及上述实施例中的第四重布线层L4亦可分别形成在第二封装体24的同一表面的不同区域。
请参照图4所示，本发明的第三实施例的一半导体封装装置4包含第一封装体21、第一重布线层L1、第二重布线层L2及第二封装体31。
请同时参照图2所示，在图2及图4中，元件具有相同编号者，具有相同的耦接关系与功能，在此不再赘述。
请继续参照图4所示，第二封装体31包含一载板311、第二电子元件312及一封胶313。
载板311的一表面与这些第二导电元件25电性连接，而载板311的另一表面设置第二电子元件312。
其中，第二电子元件312可以倒装片接合、打线接合或表面安装于载板311。封胶313设置于载板311上，并包覆第二电子元件312。其中，第二电子元件312可为一有源芯片或一整合型无源元件。
请参照图5所示，本发明的第四实施例的一半导体封装装置5包含第一封装体21、第一重布线层L1、第二一重布线层L2及第二封装体41。
请同时参照图2所示，在图2及图5中，元件具有相同编号者，具有相同的耦接关系与功能，在此不再赘述。
请继续参照图5所示，第二封装体41倒装片接合于第一封装体21，第二封装体41优选选自晶片级芯片尺寸封装体(Wafer-Level Chip Scale Package，WLCSP)，且第二封装体41包含一绝缘胶412及第二电子元件411。第二电子元件411通过这些第二导电元件25电性连接至第一封装体21。另外，绝缘胶412设置于第二电子元件411、重布线层L2及这些第二导电元件25之间，以加强其结合强度，并可保护这些第二导电元件25。
在本实施例中，这些第二导电元件25为焊锡凸块，而第二电子元件411可为一有源芯片或一整合型无源元件。此外，为了提高半导体封装装置5的散热效率，本实施例的半导体封装装置5还包含一散热层413，其设置于第二电子元件411的一表面。另外，散热层413亦可以散热鳍片(heat sink)或其他已知的散热元件来替代。
综上所述，因依据本发明的半导体封装装置通过配置于基板及封装体表面的重布线层，使得本发明不仅可以在基板及电子元件的一表面处设置接合垫，以增加输入/输出埠的数量；也可以在基板及电子元件的另一表面处设置接合垫，以供堆叠其他封装体于其上。由此，可增加半导体封装装置上下表面的输入/输出埠，以供解决习用基板表面被电子元件占用却无法设置输入/输出埠的问题。
以上所述仅为举例性，而非为限制性者。任何未脱离本发明的精神与范畴，而对其进行的等效修改或变更，均应包含于所附的权利要求中。

Claims (17)

1、一种半导体封装装置，包含：
第一封装体，具有：
第一基板，具有第一容置空间；
第一电子元件，设置于该第一容置空间中；
第一重布线层，设置于该第一基板及该第一电子元件的一表面；以及
第二重布线层，设置于该第一基板及该第一电子元件的另一表面。
2、如权利要求1所述的半导体封装装置，还包含多个第一导电元件，其与该第一重布线层电性连接。
3、如权利要求1所述的半导体封装装置，其中该第一容置空间的一侧边具有第一内壁，该电子元件具有与该第一内壁对应的第一侧表面，该第一内壁及该第一侧表面分别为一斜面。
4、如权利要求1所述的半导体封装装置，还包含第二封装体，与该第二重布线层电性连接。
5、如权利要求4所述的半导体封装装置，其中该第二重布线路层包含多个第一接合垫，该第二封装体设置于这些第一接合垫上。
6、如权利要求5所述的半导体封装装置，还包含多个第二导电元件，其分别设置于该第二封装体及这些第一接合垫之间。
7、如权利要求6所述的半导体封装装置，其中该第二封装体具有第二基板及第二电子元件，该第二电子元件设置于该第二基板的第二容置空间中。
8、如权利要求7所述的半导体封装装置，还包含第三重布线层，设置于该第二基板及该第二电子元件的一表面，其中这些第二导电元件与该第三重布线层电性连接。
9、如权利要求8所述的半导体封装装置，还包含第四重布线层，设置于该第二基板及该第二电子元件的另一表面。
10、如权利要求9所述的半导体封装装置，其中该第四重布线层还包含多个第二接合垫。
11、如权利要求8所述的半导体封装装置，还包含一散热层，设置于该第二基板及该第二电子元件的另一表面。
12、如权利要求11所述的半导体封装装置，其中该第二容置空间的一侧边具有第二内壁，该第二电子元件的一侧边具有与该第二内壁对应的一第二侧表面，该第二内壁及该第二侧表面分别为一斜面。
13、如权利要求6所述的半导体封装装置，其中该第二封装体具有一载板，其一表面与这些第二导电元件电性连接。
14、如权利要求13所述的半导体封装装置，其中该第二封装体还包含：
第二电子元件，设置于该载板的该表面；以及
一封胶，设置于该载板上，并包覆该第二电子元件。
15、如权利要求6所述的半导体封装装置，其中该第二封装体包含：第二电子元件，与这些第二导电元件电性连接。
16、如权利要求15所述的半导体封装装置，还包含一绝缘胶，设置于该第二电子元件、该第二重布线层及这些第二导电元件之间。
17、如权利要求15所述的半导体封装装置，还包含一散热层，其设置于该第二电子元件的一表面。
CNA2008100812901A 2008-02-26 2008-02-26 半导体封装装置 Pending CN101236939A (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102849674A (zh) * 2011-11-02 2013-01-02 杭州士兰集成电路有限公司 一种垂直传感器的封装方法
CN106163092A (zh) * 2016-08-20 2016-11-23 成都云士达科技有限公司 一种自带散热功能的电路板结构制作方法
WO2022021800A1 (zh) * 2020-07-31 2022-02-03 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102849674A (zh) * 2011-11-02 2013-01-02 杭州士兰集成电路有限公司 一种垂直传感器的封装方法
CN102849674B (zh) * 2011-11-02 2015-04-29 杭州士兰集成电路有限公司 一种垂直传感器的封装方法
CN106163092A (zh) * 2016-08-20 2016-11-23 成都云士达科技有限公司 一种自带散热功能的电路板结构制作方法
CN106163092B (zh) * 2016-08-20 2020-01-14 惠州市纬德电路有限公司 一种自带散热功能的电路板结构制作方法
WO2022021800A1 (zh) * 2020-07-31 2022-02-03 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构

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