CN101232076A - Method for eliminating CuxO resistance memory formation voltage - Google Patents
Method for eliminating CuxO resistance memory formation voltage Download PDFInfo
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- CN101232076A CN101232076A CNA2008100327643A CN200810032764A CN101232076A CN 101232076 A CN101232076 A CN 101232076A CN A2008100327643 A CNA2008100327643 A CN A2008100327643A CN 200810032764 A CN200810032764 A CN 200810032764A CN 101232076 A CN101232076 A CN 101232076A
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Abstract
The invention belongs to the field of microelectronic technology, in particular to a method for eliminating forming voltage of CuxO resistive memory. The method comprises following steps: growing CuxO memory medium, and annealing in oxygen-deficiency environment such as N2, Ar, forming gas or vacuum to reduce the surface CuO to Cu2O, thus eliminating forming voltage of the memory during the first programming, reducing current and voltage of write operation, and preventing CuxO memory medium with resistance switch characteristics below the surface CuO layer from being damaged by high current. The method of the invention has the advantages of simple process, low cost and significantly improved fatigue characteristics of the CuxO resistive memory.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of elimination Cu
xThe O Memister forms voltage method.
Background technology
Memory occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But because the requirement of stored charge, the floating boom of FLASH can not develop unrestricted attenuate with technology generation, and the limit that report prediction FLASH technology is arranged is about 32nm, and this just forces people to seek the more superior nonvolatile memory of future generation of performance.Recently electric resistance transition memory spare (resistive switching memory) is because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to, and employed material has phase-change material
[1], the SrZrO that mixes
3 [2], ferroelectric material PbZrTiO
3 [3], ferromagnetic material Pr
1-xCa
xMnO
3 [4], the binary metal oxide material
[5], organic material etc.For the material more than the ternary, the accurate control of component, to reduce with the compatibility of integrated circuit technology and cost all be difficult point, and binary metal oxide is (as Nb comparatively speaking
2O
5, Al
2O
3, Ta
2O
5, TixO, NixO
[5], Cu
xO etc. are just especially paid close attention to.Cu wherein
xO material and CMOS are perfect compatible, and advantage is more obvious.
Memister is by action of electric signals, but makes storage medium inverse conversion between high resistance state and low resistance state, thereby reaches memory action.Oxidation product Cu with conventional method preparation formation
xO generally is CuO and Cu
2The mixture of O, surface are coated with one deck CuO usually, are the Cu with O concentration gradient below the CuO layer
yO.CuO does not have help to the resistance transfer characteristic, to Cu
xThe Memister of O base is for the first time during write operation, needs with bigger formation voltage top layer CuO film breakdown, and the big electric current of this moment can be to the following Cu that is rich in conversion characteristic
yThe O storage medium produces destruction, causes device performance to descend.Therefore, in the middle of practical application, do not wish the appearance of top layer CuO.
Summary of the invention
The object of the present invention is to provide a kind of technology easy, with low cost, can effectively eliminate Cu
xThe O Memister forms voltage method.
This is bright to provide a kind of elimination Cu
xThe O Memister forms voltage method, the steps include: at the Cu that grown
xBehind O (1＜x≤2) storage medium, at N
2, anneal in the oxygen deficient atmospheres such as Ar, forming gas or vacuum, annealing temperature can be controlled between 100～600 ℃.Top layer CuO can be owing to anoxic is reduced into Cu
2O, thus formation voltage when programming for the first time eliminated, reduce write-operation current, voltage, the Cu below the protection top layer CuO with resistance transfer characteristic
xThe O storage medium is avoided big electric current and is destroyed.
A kind of elimination Cu of the present invention
xThe O Memister forms voltage method, at process N
2, Ar, after the annealing, the formation voltage of the memory of device can significantly reduce in forming gas or the vacuum.
The present invention can be in copper wiring technique specific implementation: in copper wiring technique, behind lower floor's copper lead-in wire, deposition block dielectric layer; On the block dielectric layer, form the through hole that holds the memory top electrode; Containing oxygen plasma, generate Cu then the Cu lead-in wire oxidation that exposes
xO, perhaps heating generates Cu under the oxygen-containing gas atmosphere
xO perhaps generates Cu with wet oxidation
xO; Afterwards at process N
2, Ar anneals in the oxygen deficient atmospheres such as forming gas or vacuum, makes top layer CuO be transformed into Cu
2O; In through hole, deposit upper electrode material then,, realize that the memory top electrode is graphical afterwards with chemico-mechanical polishing or dry etching.After the formation of memory top electrode finished, subsequent technique was traditional copper interconnection process step.
Description of drawings
Fig. 1 forms cross-sectional view after the wiring of ground floor copper forms for dual damascene process.
Fig. 2 is the cross-sectional view behind deposition block dielectric layer above the ground floor copper lead-in wire.
Fig. 3 is the cross-sectional view after forming the through hole that holds the memory top electrode on the block dielectric layer.
Fig. 4 is a cross-sectional view after the Cu lead-in wire place oxidation that exposes forms CuxO.
Fig. 4 is the cross-sectional view after annealed.
Fig. 5 is the cross-sectional view behind the deposit memory upper electrode material.
Fig. 6 a is the cross-sectional view after graphical the memory upper electrode material.
Fig. 6 b is the cross-sectional view after graphical the memory upper electrode material.
Fig. 7 is follow-up standard copper interconnection process step, deposits diffusion impervious layer successively, seed crystal copper, and electroless plating copper forms the cross-sectional view after second layer copper connects up after the chemico-mechanical polishing.
Fig. 8 is annealing front and back, Cu
xOxygen is with the atomic ratio depth profiles of copper in the O film.
Fig. 9 is for before and after the annealing, and memory forms voltage condition.
Number in the figure: 102 second layer layer insulation media, 103 the 3rd layer by layer between dielectric, the 104PMD layer, 201 ground floor etch stop layers, 202 second layer etch stop layers, 205 the 3rd layers of etch stop layer, block layer on the 203 ground floor copper lead-in wire, the through hole of 300 top electrodes, diffusion impervious layer around the 401 ground floor copper lead-in wire, diffusion impervious layer around 402 bronze medal bolts and the second layer copper lead-in wire, 501 do not need to form Cu
xThe ground floor copper lead-in wire of O storage medium, 502 need to form Cu
xThe ground floor copper lead-in wire of O storage medium, 600 is the copper embolism, 601 second layer copper lead-in wire, Cu before 701 annealing
xThe O storage medium layer, 702 annealing back Cu
xThe O storage medium layer, the 800a upper electrode material, 800 memory top electrodes after graphical, 900 is tungsten plug.
Embodiment
Describe the present invention in the reference example more completely in conjunction with being shown in hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, for the clear thickness that has amplified layer and zone, but should not be considered to the proportionate relationship that strictness has reflected physical dimension as schematic diagram.
At this reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
Fig. 8 a is a kind of elimination Cu according to the present invention
xThe part of the profile of the embodiment of O Memister formation voltage method.
With reference to figure 8a, be depicted as and be integrated in the Cu that forms in the layers for dual damascene copper interconnects technology
xO Memister structural representation, pmd layer 104 forms on the MOS device, and it can be dielectric materials such as silica PSG of mixing phosphorus, forms tungsten plug 903 in pmd layer 104, and tungsten plug 903 connects ground floor copper lead-in wire and metal-oxide-semiconductor source electrode or drain electrode.
Form ground floor etch stop layer 201 on the pmd layer 104, can be Si
3N
4, SiON, SiCN; Form ground floor interlayer dielectric layer 101 on the etch stop layer on 104, it can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material.
501 and 502 for being formed at the copper lead-in wire in ground floor dielectric layer 104 grooves, and 501 is that its upper epidermis does not need the figure oxidation to form Cu
xThe copper of O storage medium lead-in wire, 502 need figure oxidation formation Cu for its upper epidermis
xThe copper lead-in wire of O storage medium needs to form Cu
xThe copper lead-in wire 502 of O storage medium forms Cu
xThe metal bottom electrode of O memory; Diffusion impervious layer 401 for preventing that copper from spreading between copper lead-in wire and the ground floor interlayer dielectric layer 101, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Be block layer 203, Cu on the ground floor copper lead-in wire 501,502
xO storage medium layer 702 tops are to be formed at the hole 300 of block layer 203 and to be formed at top electrode 800 among the hole 300, and block layer 203 can be Si
3N
4, dielectric material such as SiON, play the diffusion barrier effect of copper and prevent the effects such as electromigration of copper, work to form hole 300 autoregistrations simultaneously here and form top electrode 800; Cu
xO Memister top electrode 800 and Cu
xThe size and the pattern thereof of O storage medium 702 are identical, and its size is less than the width (also promptly forming the width of ground floor copper cash groove) of ground floor copper lead-in wire 502.
On the top electrode 800 for not needing oxidation to form Cu
xOn the copper lead-in wire 501 of O storage medium is copper embolism 600, the copper embolism of second layer copper lead-in wire 601 on 501 among the groove mainly works to connect ground floor copper lead-in wire and second layer copper goes between 601 in order to be formed on the copper embolism 600, copper embolism on 800 mainly works to connect Memister and second layer copper lead-in wire 601, is formed at the size of the size of the through hole 901 on the top electrode 800 less than hole 302.
102,103 be respectively between the second layer insulating medium layer and the 3rd layer by layer between insulating barrier, can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; Be etch stop layer 202 between 102 and 103, for etching form through hole and groove used, can be Si
3N
4, SiON, SiCN.
What surround copper embolism 600 and copper lead-in wire 601 is expanding barrier layer 402, main rising prevents that copper is diffused in the interlayer insulating film 102,103, also play simultaneously conductor, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Fig. 8 b is a kind of elimination Cu according to the present invention
xThe part of the profile of the embodiment of O Memister formation voltage method.
With reference to figure 8b, be depicted as and be integrated in the Cu that forms in the layers for dual damascene copper interconnects technology
xO Memister structural representation, pmd layer 104 forms on the MOS device, and it can be dielectric materials such as silica PSG of mixing phosphorus, forms tungsten plug 903 in pmd layer 104, and tungsten plug 903 connects ground floor copper lead-in wire and metal-oxide-semiconductor source electrode or drain electrode.
Form ground floor etch stop layer 201 on the pmd layer 104, can be Si
3N
4, SiON, SiCN; Form ground floor interlayer dielectric layer 101 on the etch stop layer on 104, it can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material.
501 and 502 for being formed at the copper lead-in wire in ground floor dielectric layer 104 grooves, and 501 is that its upper epidermis does not need the figure oxidation to form Cu
xThe copper of O storage medium lead-in wire, 502 need figure oxidation formation Cu for its upper epidermis
xThe copper lead-in wire of O storage medium needs to form Cu
xThe copper lead-in wire 502 of O storage medium forms Cu
xThe metal bottom electrode of O memory; Diffusion impervious layer 401 for preventing that copper from spreading between copper lead-in wire and the ground floor interlayer dielectric layer 101, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Be block layer 203, Cu on the ground floor copper lead-in wire 501,502
xO storage medium layer 702 tops are to be formed at the hole 300 of block layer 203 and to be formed at top electrode 800 among the hole 300, and block layer 203 can be Si
3N
4, dielectric material such as SiON, play the diffusion barrier effect of copper and prevent the effects such as electromigration of copper; Cu
xO Memister top electrode 800 is realized graphical by etching.
On the top electrode 800 for not needing oxidation to form Cu
xOn the copper lead-in wire 501 of O storage medium is copper embolism 600, the copper embolism of second layer copper lead-in wire 601 on 501 among the groove mainly works to connect ground floor copper lead-in wire and second layer copper goes between 601 in order to be formed on the copper embolism 600, copper embolism on 800 mainly works to connect Memister and second layer copper lead-in wire 601, is formed at the size of the size of the through hole 901 on the top electrode 800 less than hole 302.
102,103 be respectively between the second layer insulating medium layer and the 3rd layer by layer between insulating barrier, can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; Be etch stop layer 202 between 102 and 103, for etching form through hole and groove used, can be Si
3N
4, SiON, SiCN.
What surround copper embolism 600 and copper lead-in wire 601 is expanding barrier layer 402, main rising prevents that copper is diffused in the interlayer insulating film 102,103, also play simultaneously conductor, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Fig. 1 to Fig. 8 is a profile according to an embodiment of the present invention, and Fig. 1 to Fig. 8 shows Cu
xO Memister and dual damascene process collection also are formed at the ground floor copper lead-in wire process between going between with second layer copper, Cu
xO is formed on the copper lead-in wire first time, under the copper embolism.But the present invention is not limited to present embodiment.
Fig. 1 has showed through conventional layers for dual damascene copper interconnects technology, proceeds to the profile after ground floor copper lead-in wire is made end.104 is pmd layer, is meant the dielectric layer between ground floor copper lead-in wire and the MOS device, and it can be dielectric materials such as silica PSG of mixing phosphorus; 900 is the tungsten bolt, and it connects ground floor copper lead-in wire and MOS device; Pmd layer is illustrated as the CMOS logical device that front-end process forms below 104.501 parts for ground floor copper lead-in wire, the storage medium of not growing above it, 502 another part for ground floor copper lead-in wire, its top will form storage medium; 101 is the layer insulation dielectric layer, and it can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; 201 is etch stop layer, can be Si
3N
4, SiON, SiCN; 401 is diffusion impervious layer, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Fig. 2 is for needing to form Cu
x Deposition block layer 203 on the O storage medium copper cash 502, and the schematic diagram that finishes of the layer segment etching of will block a shot, 300 shrinkage pools for formation behind the etching block layer 203.
Fig. 3 is for forming Cu by methods such as plasma oxidation or thermal oxidations
xGeneralized section behind the O storage medium, 701 is Cu
xO storage medium layer, top layer have covered the CuO layer, are positioned at copper 502 tops that go between.
Fig. 4 is the generalized sections after 400 degree are annealed in the process nitrogen atmosphere, and 702 for eliminating the Cu of surface C uO after the annealing
xThe O medium.
Fig. 5 is deposition Cu
xThe top electrode of the O layer generalized section that finishes, 800a is Cu
xThe upper electrode material of O layer can be single-layer metal materials such as Ta, TaN, Al, Ti, TiN, W, also can be composite materials such as Ta/TaN, Ti/TiN, Cu/Ta/TaN.
Fig. 6 a is the chemico-mechanical polishing top electrode back generalized section that finishes, the top electrode 800 of 800a for forming through pattern autoregistration behind the CMP, and it can avoid technical processs such as interlayer dielectric layer deposition, etching block layer 203, pre-sputter thereafter to directly act on Cu
xO storage medium layer 702, thus play the effect of protective layer.
Fig. 7 a is through the generalized section behind the follow-up standard copper interconnection dual damascene process formation second layer copper interconnecting line, 102,103 be respectively between the second layer insulating medium layer and the 3rd layer by layer between insulating barrier, 202 is to be etch stop layer between 102 and 103,401 is diffusion impervious layer, 600,601 are respectively copper embolism and the wiring of second layer copper.
Fig. 8 is annealing front and back, Cu
xOxygen is with the atomic ratio depth profiles of copper in the O film, and as can be seen, before annealing, top layer copper oxygen atom is rendered as CuO than near 1: 1, and after the annealing, top layer copper oxygen atom is rendered as Cu than near 2: 1
2O.
Fig. 9 is for before and after the annealing, the formation voltage when memory is programmed for the first time, before annealing, the formation voltage of memory after the annealing, forms voltage and significantly is reduced to about 2V about 9V, device performance be improved significantly.
Another embodiment of the present invention,
Shown in Fig. 6 b, top electrode 800 is realized graphical by etching.
List of references
[1]J.Maimon，E.Spall，R.Quinn，S.Schnur，″Chalcogenide-based?nonvolatile?memory?technology″，IEEEProceedings?of?Aerospace?Conference，p.2289，2001.
[2]A.Beck，J.G.Bednorz，Ch.Gerber，C.Rossel，and?D.Widmer，“Reproducible?switching?effect?in?thinoxide?films?for?memory?applications”，Appl.Phys.Lett.Vol.77，p.139，2000；C.Y.Liu，P.H.Wu，A.Wang，W.Y.Jang，J.C.Young，K.Y.Chiu，and?T.Y?Tseng，“Bistable?resistive?switching?of?a?sputter-depositedCr-doped?SrZrO3?memory?film”，IEEE?EDL?vol.26，p.351，2005.
[3]J.R.Contreras，H.Kohlstedt，U.Pooppe，R.Waser，C.Buchal，and?N.A.Pertsev，“Resistive?switching?inmetal-ferroelectric-metal?junctions”，Appl.Phys.Lett.vol.83，p.4595，2003.
[4]A.Asamitsu，Y.Tomioka，H.Kuwahara，and?Y.Tokura，“Current?switching?of?resistive?states?inmagnetoresistive?manganites”，Nature(London)vol.388，p.50，1997.
[5]I.G.Baek，M.S.Lee，S.Seo，M.J.Lee，D.H.Seo，.S.Suh，J.C.Park，S.O.Park，H.S.Kim，I.K.Yoo，U-InChung，and?J.T.Moon，“Highly?scalable?non-volatile?resistive?memory?using?simple?binary?oxide?drivenby?asymmetric?unipolar?voltage?pulses”，IEDM?Tech.Dig.p.587(2004).
Claims (1)
1. eliminate Cu for one kind
xThe O Memister forms voltage method, and it is characterized in that: Cu has grown
xBehind the O storage medium, at N
2, anneal in Ar, forming gas or the vacuum oxygen deficient atmospheres, annealing temperature is controlled between 100～600 ℃, top layer CuO can be owing to anoxic is reduced into Cu
2O, thus formation voltage when programming for the first time eliminated, reduce write-operation current, voltage, the Cu below the protection top layer CuO with resistance transfer characteristic
xThe O storage medium is avoided big electric current and is destroyed; Here 1＜x≤2.
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Cited By (7)
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| CN102254803A (en) * | 2011-08-04 | 2011-11-23 | 江苏畅微电子科技有限公司 | Method for manufacturing resistive type memory |
| CN107045883A (en) * | 2015-11-16 | 2017-08-15 | 台湾积体电路制造股份有限公司 | RRAM circuits and the method for RRAM rows formation |
| CN109698273A (en) * | 2018-12-19 | 2019-04-30 | 北京大学 | A kind of oxide nonvolatile memory and preparation method thereof based on CMOS preparation process |
| CN109728161A (en) * | 2018-12-19 | 2019-05-07 | 北京大学 | A kind of oxide memristor and preparation method thereof based on CMOS technology platform |
| CN109728160A (en) * | 2018-12-19 | 2019-05-07 | 北京大学 | A kind of oxide memristor and its integrated approach |
| CN109994604A (en) * | 2018-12-07 | 2019-07-09 | 北京大学 | A kind of oxide memristor and preparation method thereof based on CMOS technology |
| TWI669716B (en) * | 2018-11-09 | 2019-08-21 | 華邦電子股份有限公司 | Memory storage apparatus and forming method of resistive memory device thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US3976811A (en) * | 1975-03-03 | 1976-08-24 | General Electric Company | Voltage responsive switches and methods of making |
| US4144418A (en) * | 1977-05-27 | 1979-03-13 | General Electric Company | Voltage responsive switch |
| US20050227382A1 (en) * | 2004-04-02 | 2005-10-13 | Hui Angela T | In-situ surface treatment for memory cell formation |
| US7306988B1 (en) * | 2005-02-22 | 2007-12-11 | Advanced Micro Devices, Inc. | Memory cell and method of making the memory cell |
| CN100521278C (en) * | 2007-04-19 | 2009-07-29 | 复旦大学 | Preparing method for RRAM to avoid forming phenomenon using CuxO as storage medium |
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2008
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| CN102254803A (en) * | 2011-08-04 | 2011-11-23 | 江苏畅微电子科技有限公司 | Method for manufacturing resistive type memory |
| CN102254803B (en) * | 2011-08-04 | 2013-05-01 | 江苏畅微电子科技有限公司 | Method for manufacturing resistive type memory |
| CN107045883A (en) * | 2015-11-16 | 2017-08-15 | 台湾积体电路制造股份有限公司 | RRAM circuits and the method for RRAM rows formation |
| CN107045883B (en) * | 2015-11-16 | 2019-05-24 | 台湾积体电路制造股份有限公司 | The method that RRAM circuit and RRAM row are formed |
| TWI669716B (en) * | 2018-11-09 | 2019-08-21 | 華邦電子股份有限公司 | Memory storage apparatus and forming method of resistive memory device thereof |
| CN109994604A (en) * | 2018-12-07 | 2019-07-09 | 北京大学 | A kind of oxide memristor and preparation method thereof based on CMOS technology |
| CN109698273A (en) * | 2018-12-19 | 2019-04-30 | 北京大学 | A kind of oxide nonvolatile memory and preparation method thereof based on CMOS preparation process |
| CN109728161A (en) * | 2018-12-19 | 2019-05-07 | 北京大学 | A kind of oxide memristor and preparation method thereof based on CMOS technology platform |
| CN109728160A (en) * | 2018-12-19 | 2019-05-07 | 北京大学 | A kind of oxide memristor and its integrated approach |
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