CN101231970B - Method for manufacturing integrated diode and CuxO resistance memory - Google Patents
Method for manufacturing integrated diode and CuxO resistance memory Download PDFInfo
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- CN101231970B CN101231970B CN2008100327639A CN200810032763A CN101231970B CN 101231970 B CN101231970 B CN 101231970B CN 2008100327639 A CN2008100327639 A CN 2008100327639A CN 200810032763 A CN200810032763 A CN 200810032763A CN 101231970 B CN101231970 B CN 101231970B
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Abstract
The invention belongs to the microelectronic technology field and relates in particular to a manufacturing method for integrating a CuxO resistance memory with a diode. The CuxO resistance memory is integrated with the metallic oxide diode in the interconnection back-end process of copper. The upper surface layer of the storage medium CuxO is self-aligned and transformed to form a p-type copper oxide semiconductor layer. The integrated manufacturing method has the advantages of simple technological process and reliability of the CuxO resistance memory and the diode.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to the integrated manufacturing approach of a kind of Memister and diode.
Background technology
Memory occupies an important position in semi-conductor market.Because constantly popularizing of portable electric appts, the share of nonvolatile memory in whole storage market is also increasing.Nearest non-volatile resistance memory (Resistive Switching Memory) because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to.But Memister utilizes the resistance of storage medium to come storage signal in the characteristic of inverse conversion under the signal of telecommunication effect, between high resistant and low-resistance, and storage medium can have a variety of, comprises binary or multi-element metal oxide, even organic substance, wherein, and Cu
xO (1＜x≤2) is shown great attention to owing to being easy to not contain characteristics such as the element that can pollute conventional cmos technology, low-power consumption.
The binary metal oxide resistor conversion memory unit of report mainly adopts four kinds of structures at present: first kind of structure that adds a memory resistor (1T1R) for a traditional gating device
[1], second kind is crossed array (cross-point) structure
[2], the third is the structure that a gating device adds two above memory resistor (1TXR)
[3]The 4th kind is the cross array structure that a diode adds a memory resistor (1D1R)
[4]As shown in Figure 1, MOS diode and resistive memory layer are integrated between word line and the bit line, the metal oxide memory resistor of Samsung shown in Figure 2 report and the I-V performance plot of the 1D1R structure of MOS diode formation
[5], wherein the memory resistor layer is NiO, n type metal oxide layer is TiO
x, p type metal oxide layer is NiO
x, NiO memory resistor layer and p type metal oxide layer NiO
xBetween adopt the Pt metal to be connected to form ohmic contact.As shown in Figure 2, NiO memory resistor layer changes between Set and Reset state, and the on/off characteristic of diode exists simultaneously.
Simultaneously, apply for a patent in China
[6]In the 5th kind of resistive memory cell structure (1TkDkR structure) proposed; As shown in Figure 3; Memory cell structure comprises (shown in Figure 1 is 4) memory resistor and the shared same gating device of diode more than 2 or 2; The functional unit of memory resistor and diode can be distributed on the different composite plane, and this resistive memory cell can be under same piece of silicon area situation, the shared gate tube of a plurality of memory resistor; Improve the density of memory, the diode between gate tube and the memory resistor can reduce the cross-interference issue in the storage array simultaneously.Therefore, the characteristics that have low-power consumption, high storage density, unidirectional programming.
Cu
xO can adopt the preparation of plasma oxidation method through adopting thermal oxidation process, therefore based on Cu
xThe Memister of O has easily and copper connects the integrated advantage of backend process, applies for a patent in China
[7]In a kind of Cu has been proposed
xO Memister and manufacturing approach thereof.
Summary of the invention
The objective of the invention is to propose a kind of Cu
xThe manufacturing approach that the technology of O Memister and diode is integrated is so that realize the 4th kind and the 5th kind of structure of metal oxide resistor memory cell.
The Cu that the present invention proposes
xO Memister and MOS diode are integrated in the manufacturing approach in the copper wiring technique of Damascus, comprising:
The cap making that layers for dual damascene copper interconnects technology is proceeded to the copper cash top finishes, and the composition opening exposes required presumptive area copper cash on cap;
Oxidation is carried out in said copper cash zone, preparation Cu
xO storage medium, wherein 1＜x≤2;
To said Cu
xThe upper epidermis of O storage medium, autoregistration changes the semiconductor layer of the oxide of the copper that forms the p type;
Within the said cap opening, on the p type semiconductor layer, form n type metal oxide semiconductor layer;
Within the said cap opening, on the n type semiconductor layer, autoregistration forms top electrode, forms ohmic contact with n type metal oxide semiconductor layer;
Further form another layer copper cash and be connected to said top electrode.
Cu according to the invention
xThe O storage medium can adopt thermal oxidation or plasma oxygen metallization processes to form.
Another aspect disclosed by the invention, the semiconductor layer of the oxide of the copper of said p type can be to be different from Cu
xThe CuO of O storage medium layer composition, perhaps Cu
2O, perhaps CuO and Cu
2The mixture of O; Can use the method for electronation to make upper epidermis Cu
xPortion C uO in the O storage medium is transformed into Cu
2O, thus autoregistration forms p type Cu
2The O semiconductor layer; Perhaps use the method that changes the thermal oxidation technology condition, oxidation makes upper epidermis Cu
xPortion C u in the O storage medium
2O is transformed into CuO, and autoregistration forms the CuO semiconductor layer of p type.
Another aspect disclosed by the invention; The material of the semiconductor layer of the metal oxide of said n type can be WOx, TiOx, ZnOx, ZrOx, HfOx, CoOx, NbOx or IZOx etc., or the material of the doping vario-property of WOx, TiOx, 7nOx, ZrOx, HfOx, CoOx, NbOx or IZOx etc.; The semiconductor layer of the metal oxide of n type can form through the way of reactive sputter-deposition, perhaps through first depositing metal layers, further forms the metal level corresponding metal oxide through plasma or thermal oxidation technology then; The semiconductor layer of the metal oxide of n type can form through the way composition of photoetching or cmp, for the metal oxide materials of the n type that is easy to the chemical machinery mask, preferentially uses the way of chemical machinery mask to form.
Top electrode metal according to the invention can be metal or metal composite layers such as Ta, TaN, Al, W, Ti or TiN, and the way autoregistration through the chemical machinery mask is formed within the said cap opening, on the n type semiconductor layer.
After said top electrode completes; Next further adopt conventional Damascus copper wiring technique to carry out subsequent step; Be included in sample surfaces and make dielectric layer, with the said very protective layer that powers on, be patterned at and leave groove and through hole in the dielectric layer then; Next deposited barrier layer, inculating crystal layer, electrochemical method copper facing, annealing, chemico-mechanical polishing, deposition are blocked a shot, and so far another layer copper cash completes.
Cu provided by the invention
xThe manufacturing approach that O Memister and MOS diode are integrated has been utilized Cu
2O layer or CuO layer are the characteristic of p N-type semiconductor N, at Cu
xAutoregistration p type metal oxide semiconductor layer need not further to increase mask and photoetching composition step on the O storage medium layer; In integrated formation of MOS diode simultaneously and the copper wiring technique, its top electrode can freely be selected; It is simple that this integrated manufacturing method has technical process, and can guarantee Cu
xThe characteristics such as reliability of O Memister and diode.
Manufacture method of the present invention can form array on the different copper cash of same plane layer, also can on the interconnection layer copper cash of Different Plane layer, pile up, and forms three-dimensional structure.
Description of drawings
Fig. 1 is the cross array structure Memister sketch map of 1D1R.Wherein, (a) being cross-section illustration, (b) is three-dimensional icon.
The 1D1R unit I-V characteristic of MOS diode that Fig. 2 has reported and NiOx memory resistor.
Figure 31 TkDkR structural representation.
Fig. 4 Cu
xIntegrated and copper-connection ground floor of O Memister and MOS diode and the structural representation between the copper cash for the second time.
Fig. 5 forms ground floor copper lead-in wire back, deposition cap cross-sectional view before for dual damascene process CMP.
Fig. 6 is a cross-sectional view after the deposition cap.
Fig. 7 is cross-sectional view after the photoetching.
Fig. 8 is for needing to form Cu
xCross-sectional view after cap partial etching on the O storage medium copper lead-in wire finishes.
Fig. 9 is for removing cross-sectional view behind the photoresist.
Figure 10 is for needing to form Cu
xCross-sectional view after the complete etching of cap on the O storage medium copper lead-in wire finishes.
Figure 11 forms Cu for oxidation
xCross-sectional view behind the O storage medium.
Figure 12 is Cu
xCross-sectional view after the O storage medium layer upper epidermis Restore All formation Cu2O p type semiconductor layer.
Figure 13 a is a cross-sectional view behind the deposition n type metal oxide semiconductor layer.
Figure 13 b is a cross-sectional view behind the another instance formation n type metal oxide semiconductor layer.
Figure 14 a is a cross-sectional view behind the deposition top electrode metal.
Figure 14 b is a cross-sectional view behind the another example deposition top electrode metal.
Figure 14 a is that CMP forms Cu
xCross-sectional view after the top electrode of O storage medium.
Figure 15 is for the cap being stop layer CMP cross-sectional view afterwards.
Figure 16 is cross-sectional view after deposition interlayer dielectric layer and the etch stop layer.
Figure 17 opens preceding cross-sectional view for copper lead-in wire cap after etching formation groove and the through hole.
Figure 18 need not form Cu for etching
xCross-sectional view after the cap on the copper lead-in wire of O storage medium.
Figure 19 is a cross-sectional view behind the formation second layer copper lead-in wire CMP.
Symbol description
101 ground floor layer insulation media, 102 second layer layer insulation media, 103 the 3rd layer by layer between dielectric, the 104PMD layer; 201 ground floor etch stop layers, 202 second layer etch stop layers, the cap on the 203 ground floor copper lead-in wire; 203a is the cap after the etching for the first time, and 203b is the cap after the etching for the second time, and 203c is the cap after the etching for the third time; 205 the 3rd layers of etch stop layer, the hole on the 302a cap, the hole on 302 cap; Diffusion impervious layer around the 401 ground floor copper lead-in wire, diffusion impervious layer around 402 bronze medal bolts and the second layer copper lead-in wire, 501 need not form Cu
xThe ground floor copper lead-in wire of O storage medium, 502 need to form Cu
xThe ground floor copper lead-in wire of O storage medium, 600 is the copper embolism, 601 second layer copper lead-in wire, 700 Cu
xThe O storage medium layer, the n type metal oxide semiconductor layer before the oxide semiconductor layer of the copper of 701 n types, 702a composition; N type metal oxide semiconductor layer after 702 compositions, 800a top electrode metal, the upper electrode layer behind the 800CMP; Dielectric layer behind the 801CMP, 901 through holes, 902 form the groove of second layer copper lead-in wire; 903 tungsten plugs, 904 photoresists.
Embodiment
Tie full graphic hereinafter and in the reference implementation example, more fully describe the present invention, the present invention provides preferred embodiment, but should not be considered to the embodiment that only limits in this elaboration.In the drawings, for the sake of clarity, can exaggeration or the length and the thickness in amplification layer and district.
At this reference diagram is the sketch map of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all representes with rectangle, and the expression among the figure is schematically, but this should not be considered to limit scope of the present invention.Reference number similar among the figure can be represented similar structure division.
Fig. 4 is CuxO Memister and the integrated wherein section of structure of an embodiment of diode according to the present invention, and CuxO Memister and diode all are integrated in the copper-connection backend process of dual damascene.With reference to figure 3; CuxO Memister and diode are formed on the ground floor copper cash; Pmd layer 104 forms on the MOS device; It can be dielectric materials such as silica PSG of mixing phosphorus, in pmd layer 104, forms tungsten plug 903, and tungsten plug 903 connects ground floor copper lead-in wire and metal-oxide-semiconductor source electrode or drain electrode.
Form ground floor etch stop layer 201 on the pmd layer 104, can be Si
3N
4, SiON, SiCN; Form ground floor interlayer dielectric layer 101 on the etch stop layer on 104, it can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material.
501 and 502 for being formed at the copper lead-in wire in ground floor dielectric layer 104 grooves, and 501 is that its upper epidermis does not need the figure oxidation to form Cu
xThe copper of O storage medium lead-in wire, 502 need figure oxidation formation Cu for its upper epidermis
xThe copper lead-in wire of O storage medium needs to form Cu
xThe copper lead-in wire 502 of O storage medium forms Cu
xThe metal bottom electrode of O memory; Diffusion impervious layer 401 for preventing that copper from spreading between copper lead-in wire and the ground floor interlayer dielectric layer 101; Can be TaN, Ta/TaN composite bed or Ti/TiN composite bed; Or other plays the electric conducting material of same purpose, like TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
On the ground floor copper lead-in wire 501,502 is cap 203b, and for to be formed at n type metal oxide semiconductor layer 702 and the top electrode 800 in the cap hole, cap 203b can be Si on the p type semiconductor layer 701
3N
4, dielectric material such as SiON, play the diffusion barrier effect of copper and prevent the effects such as electromigration of copper, work to form hole 302 autoregistrations simultaneously here and form top electrode 800 and n type metal oxide semiconductor layer 702; N type metal oxide semiconductor layer 702 mainly works to form the n end of metal oxide heterojunction diode, and 702 and 701 actings in conjunction form heterojunction diode.
On the top electrode 800 or do not need oxidation to form Cu
xOn the copper lead-in wire 501 of O storage medium is through hole 901; Form copper embolism 600 in the through hole 901; Mainly work to connect ground floor copper lead-in wire and go between 601 for being formed at the copper embolism of second layer copper lead-in wire 601 on 501 among the groove on the copper embolism 600 with second layer copper; Copper embolism on 800 mainly works to connect Memister and second layer copper lead-in wire 601, is formed at the size of the size of the through hole 901 on the top electrode 800 less than electrode 800.
102,103 be respectively between the second layer insulating medium layer and the 3rd layer by layer between insulating barrier, can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; Between 102 and 103 etch stop layer, used for etching formation through hole 901 with groove, can be Si
3N
4, SiON, SiCN.
What surround copper embolism 600 and copper lead-in wire 601 is expanding barrier layer 402; Main rising prevents that copper is diffused in the interlayer insulating film 102,103; Also play simultaneously conductor; Can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other play the electric conducting material of same purpose, like TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Fig. 5 to Figure 19 is one a profile according to the embodiment of the present invention, and Fig. 5 to Figure 19 shows Cu
xO memory resistor and diode are integrated and be formed at the dual damascene process copper-connection ground floor copper wiring manufacturing approach between connecting up with the second layer, Cu
xO memory resistor and diode are formed on the copper cash first time, under the copper bolt.But the present invention is not limited to present embodiment.
Fig. 5 has showed through conventional layers for dual damascene copper interconnects technology, proceeds to ground floor copper lead-in wire and makes the profile after finishing.104 is pmd layer, is meant the dielectric layer between ground floor copper lead-in wire and the MOS device, and it can be dielectric materials such as silica PSG of mixing phosphorus; 903 is the tungsten bolt, and it connects ground floor copper lead-in wire and MOS device; Pmd layer is illustrated as the CMOS logical device that front-end process forms below 104.501 parts for ground floor copper lead-in wire, the storage medium of not growing above it, 502 another part for ground floor copper lead-in wire, its top will form storage medium; 101 is the layer insulation dielectric layer, and it can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; 201 is etch stop layer, can be Si
3N
4, SiON, SiCN; 401 is diffusion impervious layer, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, like TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Fig. 6 is for the cap making finishes, photoetching profile before, and 203 is cap (liner), can be Si
3N
4, mainly play the diffusion barrier effect and prevent the effects such as electromigration of copper.
Fig. 7 is profile after the photoetching, and needs are formed Cu
xCap 301 on the copper lead-in wire 502 of O storage medium adopts the way of resist exposure, need not form Cu
xCap 301 on the copper cash 501 of O storage medium adopts the photoresist protection, and 904 is the photoresist that stays after the exposure.
Fig. 8 is for needing to form Cu
xCap partial etching on the O storage medium copper cash 502 sketch map that finishes, cap becomes 203a after etching, and 302a is the shrinkage pool that etching cap 203 forms.
Fig. 9 removes the later sketch map of photoresist 904.
Figure 10 is the further etching erosion cap back generalized section that finishes, and 203b is the etching back cap that finishes, and 302 be through hole, mainly is used for autoregistration to form n type metal oxide semiconductor layer 702 and top electrode 800.
Figure 11 is for forming Cu through methods such as plasma oxidation or thermal oxidations
xGeneralized section behind the O storage medium, 700 is Cu
xThe O storage medium layer is positioned at copper and goes between under 502 tops, the hole 302.
Figure 12 is at Cu
xUpper epidermis among the O storage medium layer 700 forms p type metal oxide semiconductor layer 701 sketch map, and 701 and Cu
xO storage medium layer 700 is combined as a whole, and does not have tangible film interface, and p type metal oxide semiconductor layer 701 can be Cu
2P such as O or CuO type, semiconductor material.
Figure 13 a is a sketch map behind the formation n type metal oxide semiconductor layer 702a, and n type metal oxide semiconductor layer 702a can be metal oxides such as WOx, TiOx, ZnOx, ZrOx, HfOx, CoOx, NbOx, IZOx.N type metal oxide semiconductor layer 702 forms heterojunction diode with p type metal oxide semiconductor layer 701.
Figure 13 b is that another embodiment forms n type metal oxide semiconductor layer 702 back sketch map, can be through methods such as photoetching definition n type metal oxide semiconductor layer 702 figure; N type metal oxide semiconductor layer 702 can be metal oxides such as WOx, TiOx, ZnOx, ZrOx, HfOx, CoOx, NbOx, IZOx, also can be the material of the doping vario-property of materials such as WOx, TiOx, ZnOx, ZrOx, HfOx, CoOx, NbOx, IZOx; N type metal oxide semiconductor layer 702 forms heterojunction diode with p type metal oxide semiconductor layer 701.
Figure 14 a is a sketch map behind the deposition top electrode metal level 800a, and top electrode metal level 800a can be single-layer metal materials such as Ta, TaN, A1, Ti, TiN, W, also can be composite materials such as Ta/TaN, Ti/TiN, Cu/Ta/TaN.
Figure 14 b is that another embodiment deposits sketch map behind the top electrode metal level 800a, and top electrode metal level 800a can be single-layer metal materials such as Ta, TaN, Al, Ti, TiN, W, also can be composite materials such as Ta/TaN, Ti/TiN, Cu/Ta/TaN.
Figure 15 is the chemico-mechanical polishing top electrode back generalized section that finishes, the top electrode 800 of 800a for forming through pattern autoregistration behind the CMP, and the n type metal oxide semiconductor layer 702a among Figure 13 a forms 702 through pattern autoregistration behind the CMP.Top electrode 800 can avoid thereafter interlayer dielectric layer deposition, etching cap 203b, technical process such as sputter directly acts on n type metal oxide semiconductor layer 702 in advance, thereby play the effect of protective layer.
Figure 16 is a generalized section after deposition interlayer insulating film and etch stop layer finish, and 102,103 is the layer insulation dielectric layer, and it can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; 202,205 is etch stop layer, can be Si
3N
4, SiON, SiCN, mainly play etch mask and prevent effect such as copper diffusion.
Figure 17 is a generalized section after through hole and etching groove finish, and 901 is through hole (Via), and 902 is groove (Trench).
Figure 18 is for being that mask etching need not form Cu with top electrode 800
xThe copper of the O storage medium cap of the 501 tops back generalized section that finishes that goes between.
Figure 19 finishes to form the generalized section after second layer copper cash 601 forms for deposition diffusion impervious layer 402 to chemical machinery cuts open light; 402 is diffusion impervious layer; Cu there is barrier effect to the diffusion of dielectric layer; Can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other play the electric conducting material of same purpose, like TiSiN, WNx, WNxCy, TiZr/TiZrN etc.601 is second bronze medal copper lead-in wire, and 600 for connecting the copper embolism of ground floor copper lead-in wire 501 and second layer copper lead-in wire 601.
Next, will explain the concrete technique manufacturing method of this execution mode with Fig. 5 to cross sectional view shown in Figure 19.
With reference to figure 6, through conventional layers for dual damascene copper interconnects technology, after proceeding to ground floor copper lead-in wire CMP and making knot, as the initial step of the manufacturing approach of this embodiment.
Further enforcement of the present invention, with reference to figure 6, PECVD deposition one deck Si
3N
4Cap; Cap 203 thickness ranges are 20～2000nm, and concrete thickness guarantees the thickness condition decision that chemico-mechanical polishing can successfully be carried out by cap 203b layer in top electrode 800 and n type metal oxide semiconductor layer 702 needed thickness and the back processing step.Thickness in this definition cap 203 is d1.
Further enforcement of the present invention with reference to figure 7, forms photoresist pattern 904 through mask 1# photoetching, and the pattern 1# of this mask has determined cap aperture pattern and copper lead-in wire to determine to need to form Cu
xThe zone of O storage medium layer.
Further enforcement of the present invention is with reference to figure 8, through RIE dry etching Si
3N
4Cap 203, the pattern of transfer photoresist 904, cap becomes 203a by 203, forms shrinkage pool 302a on the cap, and the size of shrinkage pool 302a is less than the width of the groove that forms ground floor copper lead-in wire.According to the speed of RIE dry etching condition etching Si3N4 cap, the selective etching time, the degree of depth of shrinkage pool 302a is defined herein as d2.
Further enforcement of the present invention with reference to figure 9, is removed photoresist 904 through conventional dry ashing technology, removes the remaining fluoride residue of RIE etching with wet-cleaned then.
Further enforcement of the present invention with reference to Figure 10, continues RIE etching cap 203a and opens until ground floor copper lead-in wire, and cap becomes 203b by the 203a limit, and the through hole 302 in the cap forms.The degree of depth of through hole 302 also is the thickness of cap 203b, is defined herein as d3.In the common process, need form Cu in order to make all
xThe copper lead-in wire in O zone exposes, and adopts the process conditions of over etching a little.For example, if d1=120nm, d2=80nm, in this step according to RIE dry etching condition etching Si
3N
4The speed of cap, selective etching thickness are etching condition (the over etching 15nm Si of 55nm
3N
4), d3=120-55=65nm so.
Further enforcement of the present invention, with reference to Figure 11, to groove copper lead-in wire 502 the pattern expose portion carry out plasma oxidation, this moment, cap 203b played the mask effect.Through the conditions such as time, power of control plasma oxidation, confirm the Cu that forms
xThe performance of O storage medium layer 700 and thickness thereof.
Further enforcement of the present invention, with reference to Figure 12, select for use certain density hydroxylamine solution under the uniform temperature condition to Cu
xProcessing is reduced on O storage medium layer 700 surfaces, Cu
xThe CuO on O storage medium layer 700 top layers all converts Cu into
2O, the top layer forms pure Cu
2The p type semiconductor films layer 701 of O, its thickness is less than Cu
xThe thickness of O storage medium layer 700, it is by the wet reducing conditional decision, and thickness range is 5-100nm.
Further enforcement of the present invention, with reference to figure 13a, PVD deposition 20nmn N-type semiconductor N TiO2 layer 702a.
In another embodiment, with reference to figure 13b, for the metal oxide layer that is difficult to realize CMP, for example WO3 adopt first PVD deposition 20nm n N-type semiconductor N WO3 layer, and then the chemical wet etching composition forms WO3 layer 702; Perhaps adopt first PVD deposition one deck 20nmW metal level, behind the CMP, the autoregistration of W metal is formed in the through hole 302, further adopts the method for 10min thermal oxidation under 400 ℃ of conditions, and the 20nmW metal level all forms the n type semiconductor layer 702 of WOx.The thickness range of n type metal oxide semiconductor layer 702 is 5-100nm, and it is less than d3.
Further enforcement of the present invention, with reference to figure 14a, CVD deposition TaN layer metal 800a is as top electrode again.
In another embodiment, with reference to figure 14b, CVD deposition TaN layer metal 800a is as top electrode.
Further enforcement of the present invention, with reference to Figure 15, CMP top electrode metal level TaN800a is the CMP stop layer with cap 203b, and the top electrode shape becomes 800 by 800a, and autoregistration forms upper electrode layer.
Further enforcement of the present invention, with reference to Figure 16, insulating barrier 102,103 between CVD sedimentary deposit FSG, and Si
3N
4Etch stop layer 202,205.
Further enforcement of the present invention is with reference to Figure 17, earlier through using mask 2#, chemical wet etching Si
3N
4Layer 205 removes photoresist, then with Si
3N
4Layer 205 is that insulating barrier 103 forms groove 902 between mask etching FSG; Passing through to use mask 3#, chemical wet etching Si
3N
4Layer 202 removes photoresist, then with Si
3N
4Layer 202 is that insulating barrier 102 forms through hole (Via) 901 between mask etching FSG.
Further enforcement of the present invention, with reference to Figure 18, the RIE etching need not form Cu
xThe copper cash 501 top cap 203b of O storage medium make copper lead-in wire 501 exposed, and cap becomes 203c by 203b; Top electrode TaN layer 800a makes mask protection Cu in this process
xO storage medium layer 700 is avoided the injury of RIE etching condition; Carry out wet-cleaned after etching finishes and remove remaining fluoride.
Further enforcement of the present invention is with reference to Figure 19, through Ar
2The go between autoxidation copper on 501 top layers of gas plasma treatment copper, to strengthen the adhesive capacity with diffusion layer, CVD deposition Ta/TaN diffusion impervious layer 402 then; Growth inculating crystal layer Cu, re-plating growth Cu, annealing then; CMP removes unnecessary copper trace layer, forms copper embolism 600 and second layer copper lead-in wire 601.
So far, the wiring of second layer copper reaches and forms, and the copper wiring technique step is not within summary of the invention thereafter.
Cu as stated
xThe integrated manufacturing of O Memister and MOS diode realizes that it can select to form a plurality of Cu on ground floor copper lead-in wire
xO Memister and MOS diode unit also can form Cu on the follow-up second time or more high-rise copper lead-in wire
xO Memister and MOS diode unit.
List of references
[1]I.G.Baek，M.S.Lee，S.Seo，M.J.Lee，D.H.Seo，.S.Suh，J.C.Park，S.O.Park，H.S.Kim，I.K.Yoo，U-InChung，and?J.T.Moon，“Highly?scalable?non-volatile?resistive?memory?using?simple?binary?oxide?drivenby?asymmetric?unipolar?voltage?pulses”，IEDM?Tech.Dig.p.587(2004).
[2]A.Chen，S.Haddad，Y.-C.Wu，”Non-Volatile?Resistive?Switching?for?Advanced?Memory?Applications”in?NVSMW，2006
[3] woods Yin Yin etc., " a kind of resistance random access memory and methods of storage operating thereof ", application number: 200710036818.9
[4] An Chengyan etc. " nonvolatile memory that comprises a resistor and a diode ", application number: 200510120431.2
[5]Myoung-Jae?Lee，Sunae?Seo，et?al.“A?Low-Temperature-Grown?Oxide?Diode?as?a?New?Switch?Elementfor?High-Density，Nonvolatile?Memories”，Adv.Mater.2007，19，p73-76.
[6] woods Yin Yin etc. is " with the Cu of top electrode as protective layer
xO Memister and manufacturing approach thereof ", application number: 200710045407.6.
Claims (5)
1. Cu
xThe manufacturing approach that O Memister and MOS diode are integrated is characterized in that, concrete steps comprise:
The cap making that layers for dual damascene copper interconnects technology is proceeded to the copper cash top finishes, and the composition opening exposes required presumptive area copper cash on cap;
Oxidation is carried out in said copper cash zone, preparation Cu
xO storage medium, wherein 1＜x≤2;
With said Cu
xThe upper epidermis of O storage medium, autoregistration are transformed into p type copper metal oxide semiconductor layer;
Within the said cap opening, on the p type copper metal oxide semiconductor layer, form n type metal oxide semiconductor layer;
Within the said cap opening, on the n type metal oxide semiconductor layer, autoregistration forms top electrode, forms ohmic contact with n type metal oxide semiconductor layer;
Further form another layer copper cash and be connected to said top electrode.
2. Cu according to claim 1
xThe manufacturing approach that O Memister and MOS diode are integrated is characterized in that, said Cu
xThe O storage medium adopts thermal oxidation or plasma oxygen metallization processes to form.
3. Cu according to claim 1
xThe manufacturing approach that O Memister and MOS diode are integrated is characterized in that, said p type copper metal oxide semiconductor layer is to be different from Cu
xThe CuO or the Cu of O storage medium layer composition
2O or CuO and Cu
2The mixture of O.
4. like the said Cu of claim 3
xThe manufacturing approach that O Memister and MOS diode are integrated is characterized in that, uses the method for electronation to make upper epidermis Cu
xPortion C uO in the O storage medium is transformed into said Cu
2O, thus autoregistration forms p type Cu
2The O semiconductor layer.
5. Cu according to claim 1
xThe manufacturing approach that O Memister and MOS diode are integrated; It is characterized in that; Said top electrode metal is Ta, TaN, Al, W, Ti or TiN metal or metal composite layer, and the way autoregistration through cmp is formed within the said cap opening, on the n type metal oxide semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100327639A CN101231970B (en) | 2008-01-17 | 2008-01-17 | Method for manufacturing integrated diode and CuxO resistance memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| WO2011064801A1 (en) | 2009-11-30 | 2011-06-03 | Andrea Redaelli | Memory including a low thermal budget selector switch on a variable resistance memory cell |
| CN102332454B (en) | 2010-07-15 | 2013-04-10 | 复旦大学 | One-time programmable memory cell, memory and preparation method thereof |
| JP6208971B2 (en) * | 2012-09-14 | 2017-10-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN105513949B (en) * | 2015-12-30 | 2019-03-12 | 上海华虹宏力半导体制造有限公司 | The method for forming carbon substrate articulamentum |
| CN105575989B (en) * | 2016-03-24 | 2019-03-12 | 上海华力微电子有限公司 | Stop the method for metallic pollution in cmos image sensor HDP shallow trench filling process |
| TWI619283B (en) * | 2016-05-30 | 2018-03-21 | 旺宏電子股份有限公司 | Resistive memory device method for fabricating the same and applications thereof |
| WO2019218106A1 (en) | 2018-05-14 | 2019-11-21 | 中国科学院微电子研究所 | 1s1r memory integrated structure and method for preparing same |
| CN109728163B (en) * | 2018-12-29 | 2023-05-23 | 中国科学院微电子研究所 | Resistive random access memory and manufacturing method thereof |
| CN112259682A (en) * | 2019-07-22 | 2021-01-22 | 华邦电子股份有限公司 | Memory device and method of manufacturing the same |
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| CN101051670A (en) * | 2007-04-19 | 2007-10-10 | 复旦大学 | Preparing method for RRAM to avoid forming phenomenon using CuxO as storage medium |
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