CN102237309A - Method for integrating manganese-oxide-based resistive memory with copper interconnection rear end process - Google Patents
Method for integrating manganese-oxide-based resistive memory with copper interconnection rear end process Download PDFInfo
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Abstract
The invention belongs to the technical field of semiconductor memories and particularly relates to a method for integrating a manganese-oxide-based resistive memory with a copper interconnection rear end process. In the method for process integration, manganese metal in a cap layer on a copper lead wire is siliconized to form a MnSi compound layer and the MnSi compound layer is oxidized to form a MnSi(x)O(y) storage medium layer; and a manganese silica compound layer is used as a barrier layer of the copper lead wire at a copper interconnection rear end. The method has the advantages of compatibility with the copper interconnection rear end process with process nodes equal to or less than 45 nanometers; and the manganese-oxide-based resistive memory has low preparation cost, high reliability and low power consumption.
Description
Technical field
The invention belongs to the semiconductor memory technologies field, be specifically related to based on MnSixOy storage medium layer (0.001＜x≤2,2＜y≤5) resistor-type memory (Resistive Memory) relates in particular to resistor-type memory and the integrated method of copper-connection backend process based on the MnSixOy storage medium layer.
Background technology
Memory occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH (flash memory).But because the requirement of stored charge, the floating boom of FLASH can not develop unrestricted attenuate with technology generation, and the limit that report prediction FLASH technology is arranged is about 32nm, and this just forces people to seek the more superior nonvolatile memory of future generation of performance.Recently resistor-type transit storage spare (Resistive Switching Memory) is because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to, and employed material has the SrZrO of phase-change material, doping
3, ferroelectric material PbZrTiO
3, ferromagnetic material Pr
1-xCa
xMnO
3, binary metal oxide material, organic material etc.
Resistor-type memory (Resistive Memory) is by action of electric signals, makes storage medium at high resistance state (High Resistance State, HRS) and low resistance (Low Resistance State, LRS) but inverse conversion between the state, thereby realize memory function.The storage medium material that resistor-type memory uses can be various metal oxide semiconductor materials, for example, and cupric oxide, titanium oxide, tungsten oxide etc.
Simultaneously, we notice, manganese oxide (MnOz, 1＜z≤3) a kind of as in two yuan of metal oxides of material, reported the resistance transfer characteristic of MnOz in people's such as SenZhang being entitled as in J.Phys.D:Appl.Phys.42 (2009) " Resistive switchingcharacteristics of MnOz-based ReRAM " the literary composition, so it is as the storage medium of resistor-type memory.And can see that therefrom less than 100 ohm, therefore, it will inevitably cause its electric current when low resistance state bigger based on the low resistance state resistance of the resistor-type memory of MnOz, the low-power consumption that defines this resistor-type storage is used.
Further, along with the development of semiconductor process techniques, critical size constantly reduces, and the resistor-type memory technology must need to extend to after 45 nanometers (nm) process node.Material such as Cu, W is owing to the restriction of crystallite dimension, and its corresponding oxide can cause leakage current bigger when doing storage medium, thereby increases power consumption, can not replace Flash at 45nm and 32nm stage effectively.And at 45 nanometers and 32 nanometer technology nodes, require barrier layer thickness to drop to 4.9nm and 3.6nm respectively, depth-to-width ratio also further strengthens, traditional Ti/TiN, Ta/TaN etc. can't satisfy its requirement, therefore, storage medium such as titanium oxide, tantalum oxide also can be subjected to process technology limit in the application of copper-connection rear end.
And after 45 nanometer technology nodes, copper diffusion barrier material may extensive use manganese silicon oxide compound material, its have resistivity low, effectively copper diffusion barrier, deelectric transferred good, thickness is ultra-thin, the advantage of good reliability.
Comprehensive above prior art, be necessary to propose a kind of can be integrated to prepare the method for manganese oxide based resistor-type memory with 45 nanometers or the following process node copper-connection of 45 nanometers backend process.
Summary of the invention
The technical problem to be solved in the present invention is to propose a kind of manganese oxide based resistor-type memory and the integrated method of copper-connection backend process.
For solving above technical problem, the integrated method of manganese oxide based resistor-type memory provided by the invention and copper-connection backend process may further comprise the steps:
(1) composition forms the copper lead-in wire that the barrier layer is a manganese silicon oxide compound layer;
(2) on described copper lead-in wire, cover deposition block layer;
(3) the described block layer of patterned etch forms hole to expose the copper lead-in wire zone that desire forms the MnSixOy storage medium layer;
(4) in the hole of described block layer, fill the manganese metal level;
(5) described manganese metal level is carried out silicidation to form the MnSi compound layer;
(6) described MnSi compound layer is carried out oxidation processes to form the MnSixOy storage medium layer;
(7) composition forms top electrode on described MnSixOy storage medium layer;
(8) continue the copper-connection backend process to form copper embolism and following layer of copper lead-in wire;
Wherein, 0.001＜x≤2,2＜y≤5.
As preferable embodiment, described copper-connection backend process is 45 nanometer technology node technologies or the following process node technology of 45 nanometers.
As the preferred technique scheme, particularly, described step (1) may further comprise the steps:
(1a) deposited copper manganese alloy inculating crystal layer in described groove;
(1b) electro-coppering then;
(1c) copper and described cupromanganese inculating crystal layer are annealed;
(1d) planarization is to remove the cupric oxide and the manganese oxide of unnecessary copper and copper wire surface.
According to method provided by the present invention, wherein, described silication can be silication in siliceous gas, the ion of silication or silicon injects silication in the silicon plasma.Described oxidation can be that plasma oxidation, thermal oxidation, ion inject a kind of of oxidation.
According to an embodiment of method provided by the present invention, described very TaN, Ta, TiN, Ti, W, Al, Ni, Co or the Mn metal level of powering on perhaps is several composite beds of forming in the above metal level.
Described manganese metal level obtains by sputter, evaporation or electroplating deposition, and described manganese metal layer thickness scope is that about 0.5 nanometer is to about 50 nanometers.
Described MnSixOy storage medium layer can be to mix the storage medium layer that Si forms among the MnOz, wherein, and 1＜z≤3.Perhaps described MnSixOy storage medium layer is the nanometer composite layer of MnOz and silica, wherein, and 1＜z≤3.
According to an embodiment of method provided by the present invention, described copper-connection backend process adopts dual damascene process.
Technique effect of the present invention is, by manganese oxide based resistor-type memory and copper-connection backend process is integrated, the resistor-type memory of MIM (metal-dielectric layer-metal) structure is embedded into behind the copper-connection of logical circuit in the end structure, especially can embed behind the following copper-connection of 45 nanometers or 45 nanometer technology nodes in the end structure.Therefore, can realize that logic process and memory manufacturing process are perfect compatible, it is low to reduce preparation cost.On the other hand, for manganese oxide based resistor-type memory, owing to the technology that adopts manganese metal level elder generation silication rear oxidation, the speed of oxidation is relatively slow, and process controllability is stronger, and the yield of MnSixOy storage medium layer and reliability improve; And because the relative compactness characteristics of MnSi, MnSixOy storage medium layer after the oxidation is the oxide densification more of common relatively manganese also, thereby the resistance of its high-impedance state and low resistance state all is improved (the especially resistance of low resistance state), has lowered the power consumption of memory cell.
Description of drawings
Fig. 1 is the structural representation according to the prepared resistor-type memory of the integrated method of manganese oxide based resistor-type memory provided by the invention and copper-connection backend process.
Fig. 2 is the structural representation that adopts conventional Damascus copper wiring technique, proceeds to ground floor copper wiring making beginning.
Fig. 3 is the structural representation that forms after copper goes between.
Fig. 4 is the structural representation after copper lead-in wire back covers the block layer.
Fig. 5 is the structural representation in expose portion copper lead-in wire zone, patterned etch block layer back.
Fig. 6 is the structural representation behind the filling manganese metal level in the hole of block layer.
Fig. 7 is the structural representation that is formed the MnSi compound layer with the manganese metal level in the hole of block layer by silicidation.
Fig. 8 is the structural representation after the MnSixOy storage medium layer forms.
Fig. 9 is the structural representation after composition on the MnSixOy storage medium layer forms top electrode.
Figure 10 is at the structural representation that covers on the top electrode after forming protective dielectric layer.
Figure 11 is covering the structural representation that forms in order to behind the dielectric layer that forms copper embolism and copper lead-in wire on the described protective medium.
Figure 12 is the structural representation after copper embolism and copper lead-in wire form.
Embodiment
Describe the present invention in the reference example more completely in conjunction with being shown in hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, for the clear thickness that has amplified layer and zone, but should not be considered to the proportionate relationship that strictness has reflected physical dimension as schematic diagram.
At this reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
Figure 1 shows that structural representation according to the prepared resistor-type memory of the integrated method of manganese oxide based resistor-type memory provided by the invention and copper-connection backend process.As shown in Figure 1, in the integrated copper interconnection structure of manganese oxide based resistor-type device, thereby can realize memory and the integrated making of CMOS logical circuit.This manganese oxide based resistor-type memory adopts MnSixOy as storage medium layer, and wherein x, y have reacted the stoichiometric proportion between Mn, Si and the O, 0.001＜x≤2,2＜y≤5.Therefore, MnSixOy storage medium layer 503 also can be understood as the manganese oxide based storage medium layer that comprises silicon doping.In this embodiment, MnSixOy storage medium layer 503 is on the copper lead-in wire 203a that is formed in the copper interconnection structure, under the copper embolism 303a, and has formed optional top electrode 209 between copper embolism 303a and MnSixOy storage medium layer 503.Preferably, copper interconnection structure shown in the figure is based on 45 nanometer technology nodes or the following formed copper interconnection structure of 45 nanometer technology nodes, wherein, diffusion impervious layer all adopts manganese silica (MnSiO) compound film layer, this manganese silicon oxide compound thin layer is mainly used to stop copper to spread in dielectric layer, and its concrete material structure or composition ratio are different from MnSixOy storage medium layer 503.
As shown in Figure 1, pmd layer 100 forms on the MOS device, and it can be dielectric materials such as silica PSG of mixing phosphorus, forms tungsten plug 102a and 102b in pmd layer 100, and tungsten plug connects metal-oxide-semiconductor source electrode or the drain electrode on ground floor Cu lead-in wire and the substrate 000.Diffusion impervious layer 101 for preventing that tungsten from spreading between tungsten plug and the PMD dielectric layer 100, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, Ru, TiZr/TiZrN etc.Tungsten 102 tops that go between are Cu lead-in wire 203.Diffusion impervious layer for preventing that Cu from spreading between Cu lead-in wire and the W lead-in wire.In the embodiment shown in fig. 1, copper lead-in wire 503a is the bottom electrode of resistor-type memory.
MnSixOy storage medium layer 503 is to form by the technology to manganese metal level elder generation silication rear oxidation, and the thickness range of MnSixOy storage medium layer 503 is 0.5nm～50nm, for example can be 1nm.By MnSi compound layer 502 is exposed in the oxygen atmosphere, perhaps be exposed in the oxygen plasma, continuous and the O reaction generation MnOz compound (1＜z≤3) of Mn meeting in the MnSi compound layer, original Si element is present in formation MnSixOy storage medium in the MnOz compound-material with the form of silicon or silica, also promptly comprises the manganese oxide based storage medium layer 503 of silicon doping.In the MnSixOy storage medium layer 503, according to the existence form of Si, its manganese oxide based storage medium that comprises silicon doping can be a storage medium of mixing Si in the MnOz material, also is appreciated that it is the nanometer composite layer of MnOz and silica.The mass percentage content scope of the element silicon in the MnSixOy storage medium layer is 0.001%-60%, specifically relevant with the technological parameter of the stoichiometric proportion of MnSi layer and oxidation, preferably, the mass percentage content scope of the element silicon in the MnSixOy storage medium layer is 0.1%, 1%; And it might not be uniform that the mass percent of Si in MnSixOy storage medium layer 503 distributes.For example, might be to be distributed in the MnSixOy storage medium 503 from the form that upper surface successively decreases with the mass percent gradient to lower surface Si element; Also might be that the Si element is concentrated a physical layer zone between the upper surface be distributed in MnSixOy storage medium 503 and the lower surface relatively, for example, the upper epidermis of MnSixOy storage medium 503 is that MnOz, the following top layer that there are a silicon-containing layer in MnOz, intermediate layer is MnOz, but not having clear and definite physical boundaries between its upper epidermis, intermediate layer, the following top layer, all is to be all MnSixOy storage medium layer 503 therefore.The concrete distribution form of element silicon in MnSixOy storage medium layer 503 do not limited by the present invention.Further need to prove, in the MnSixOy storage medium layer 503 except comprising the Si element, can also comprise other doped chemicals, for example, if in oxidizing process, also feed other active gasess outside the deoxygenation in the gas of oxidation as containing the gas of F, then except that containing Si, also be mixed with F in the MnOz base storage medium, other doping composition of concrete MnSixOy storage medium layer 503 is not limited by the embodiment of the invention, and its process conditions with oxidation are relevant.
Fig. 2 to shown in Figure 12 with the structural representation illustrative manganese oxide based resistor-type memory and the integrated method of copper-connection backend process.Below specifically the method for this invention is specifically described in conjunction with Fig. 2 to Figure 12.
Step S10 provides the structure of preparing to make the copper lead-in wire in Damascus copper wiring technique of routine.
As shown in Figure 2, Figure 2 shows that the structural representation that adopts conventional Damascus copper wiring technique, proceeds to ground floor copper wiring making beginning.In this embodiment, preferably, adopt conventional dual damascene process.After etch stop layer 201 and inter-level dielectric (IMD) 202 depositions finished, patterned etch was formed for forming the groove 2021 of copper lead-in wire in etch stop layer 201 and interlayer dielectric layer (IMD) 202.As shown in Figure 2,100 is pmd layer, is meant the dielectric layer between ground floor wiring and the MOS device, and it can be dielectric materials such as silica of mixing phosphorus; Form tungsten plug 102a and 102b in pmd layer 100, tungsten plug 102a is used to be connected ground floor Cu lead-in wire and metal-oxide-semiconductor source electrode or drain electrode with 102b.Diffusion impervious layer 101 for preventing that tungsten from spreading between tungsten plug and the PMD dielectric layer 100, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, Ru, TiZr/TiZrN etc.; Tungsten lead-in wire top covers sealant or etch stop layer 201, can be SiN, SiC, or play the other materials of same purpose; The etch stop layer top is the interconnection line dielectric layer, can be low k materials such as FSG, USG, also can play the material of same purpose for other.
Step S20, composition form the copper lead-in wire that the barrier layer is the manganese silicon oxide compound.
With reference to shown in Figure 3, Figure 3 shows that the structural representation that forms after copper goes between.In this step, preferably, adopt following method step to form the copper lead-in wire (203a, 203b) that barrier layer (204a, 204b) is the manganese silicon oxide compound:
S201, deposited copper manganese alloy inculating crystal layer in groove;
Deposition CuMn alloy inculating crystal layer can be undertaken by technology modes such as sputter, electron beam evaporation, atomic layer deposition or plating; The purpose of deposition CuMn alloy inculating crystal layer is to form ultra-thin manganese silicon oxide compound to be used as the barrier layer for SiO reaction that Mn in the annealing process of back is diffused into sidewall and sidewall, and this layer can also be induced the electro-coppering crystallization simultaneously; The thickness range of CuMn alloy inculating crystal layer be 5 nanometers to 100 nanometers, preferably, be about 10nm; The atom content of Mn is 0.05% to 20% in the cupromanganese.
S202, electro-coppering;
S203 anneals to copper and cupromanganese layer;
In this embodiment, the effect of annealing process has three aspects: first aspect, can eliminate the defective in CuMn alloy inculating crystal layer and the electro-coppering, and reduce the resistivity of copper lead-in wire; Second aspect, the SiO reaction that can impel manganese atom in the CuMn alloy inculating crystal layer to be diffused into sidewall and sidewall forms ultra-thin manganese silicon oxide compound, thereby forms the barrier layer (204a and 204b) of MnSiO compound; The third aspect can be impelled not the Mn atom diffusion with sidewall SiO reaction to form MnOz (1＜z≤3) to the Cu surface, thereby remove unnecessary Mn atom in the copper lead-in wire.
The more existing Ta/TaN of the MnSiO compound layer barrier layer, barrier layer that above method forms is thinner, preparation technology is simple, uniformity is better, can increase the ratio of Cu in groove, effectively reduces interconnection resistance, thereby reduces interconnect delay; Be very suitable for the copper wiring technique of 40 nanometers or the following process node of 45 nanometers.
S204, planarization is to remove the cupric oxide and the manganese oxide of unnecessary copper and copper wire surface.
Step S30 covers deposition block layer on the copper lead-in wire.
With reference to shown in Figure 4, Figure 4 shows that the structural representation after copper lead-in wire back covers the block layer.Cover one deck block layer 205 on copper embolism 230a and 203b, block layer 205 can or comprise one of them composite bed for Si3N4, SiON, SiCN, SiC, SiO2.In this embodiment, the copper that has lead-in wire is only as logical circuit and do not form memory, copper lead-in wire 203b for example, and form memory simultaneously on the copper that the has lead-in wire, and for example, 203a.In follow-up step, block layer 205 can be used for protecting the Cu embolism 203b that does not need to form the MnSixOy storage medium layer.
Step S40, patterned etch block layer form hole to expose the copper lead-in wire zone that desire forms the MnSixOy storage medium layer.
With reference to shown in Figure 5, Figure 5 shows that the structural representation in expose portion copper lead-in wire zone, patterned etch block layer back.In this embodiment, hole 103 exposes copper lead-in wire 203a, prepares for next step forms storage medium layer, and the area size of hole 103 is consistent with the area size of the MnSixOy storage medium layer that figure and desire form.
Step S50 fills the manganese metal level in the hole of described block layer.
With reference to shown in Figure 6, Figure 6 shows that the structural representation behind the filling manganese metal level in the hole of block layer.Wherein, at first cover the Mn metal, it can adopt sputter, evaporation, modes such as plating; Adopt flatening process to remove the block layer then and go up a unnecessary Mn metal and form a Mn metal level 501, for example, adopt the flatening process of cmp (CMP), wherein with the block layer as the grinding stop layer.The thickness of Mn metal level 501 is relevant with the thickness of block layer, and its thickness range can be preferably about 5nm for about 0.5nm about 50nm extremely.
Step S60 carries out silicidation to form the MnSi compound layer to described manganese metal level.
With reference to shown in Figure 7, Figure 7 shows that the structural representation that is formed MnSi compound layer 502 with the manganese metal level in the hole of block layer by silicidation.MnSi compound layer 502 is to form by the manganese metal level 501 that exposes is carried out silicidation.The method of its silication mainly contains: the method silication that the ion of silication (3) silicon injects under silication (2) the high temperature silicon plasma in the silicon-containing gas of (1) high temperature.Planting silicification method with (1) is example, and by under certain high temperature (200 degrees centigrade one 600 degrees centigrade), Mn metal level 501 is exposed in the siliceous gas, Mn metal and gas generation chemical reaction, and silication generates the MnSi compound layer.In this embodiment, siliceous gas can be gases such as SiH4, SiH2Cl2, Si (CH3) 4, and the constant air pressure of chemical reaction is less than 20Torr (holder).Can carry out under silane (SiH4) atmosphere under the condition of heating, temperature can be 100-500 ℃, and silane concentration can be 0.01%-30%.In (3) kind method, when the ion of silicon injected, block layer 205 played mask layer simultaneously, did not need to form the copper lead-in wire 203b of MnSixOy storage medium layer thereon with protection.
Step S70 carries out oxidation processes to form the MnSixOy storage medium layer to described MnSi compound layer.
With reference to figure 8, Figure 8 shows that the structural representation after the MnSixOy storage medium layer forms.
MnSi compound layer shown in Figure 7 502 is carried out oxidation processes, form MnSixOy storage medium layer 503.In this embodiment, the method for oxidation processes has plasma oxidation, thermal oxidation or ion to inject oxidation.When oxidation processes, block layer 205 plays mask layer simultaneously, does not need to form the copper lead-in wire 203b of MnSixOy storage medium layer thereon with protection.The thickness range of MnSixOy storage medium layer 503 is 0.5nm～50nm, for example can be 1nm.This method for oxidation has self aligned characteristics (figure of MnSixOy storage medium layer is aimed at MnSi compound layer 502).By MnSi compound layer 502 is exposed in the oxygen atmosphere, perhaps be exposed in the oxygen plasma, continuous and the O reaction generation MnOz compound (1＜z≤3) of Mn meeting in the MnSi compound layer, original Si element is present in formation MnSixOy storage medium in the MnOz compound-material with the form of silicon or silica, also promptly comprises the manganese oxide based storage medium layer 503 of silicon doping.In the MnSixOy storage medium layer 503, according to the existence form of Si, its manganese oxide based storage medium that comprises silicon doping can be a storage medium of mixing Si in the MnOz material, also is appreciated that it is the nanometer composite layer of MnOz and silica.The mass percentage content scope of the element silicon in the MnSixOy storage medium layer is 0.001%-60%, specifically relevant with the technological parameter of the stoichiometric proportion of MnSi layer and oxidation, preferably, the mass percentage content scope of the element silicon in the MnSixOy storage medium layer is 0.1%, 1%; And it might not be uniform that the mass percent of Si in MnSixOy storage medium layer 503 distributes.For example, might be to be distributed in the MnSixOy storage medium 503 from the form that upper surface successively decreases with the mass percent gradient to lower surface Si element; Also might be that the Si element is concentrated a physical layer zone between the upper surface be distributed in MnSixOy storage medium 503 and the lower surface relatively, for example, the upper epidermis of MnSixOy storage medium 503 is that MnOz, the following top layer that there are a silicon-containing layer in MnOz, intermediate layer is MnOz, but not having clear and definite physical boundaries between its upper epidermis, intermediate layer, the following top layer, all is to be all MnSixOy storage medium layer 503 therefore.The concrete distribution form of element silicon in MnSixOy storage medium layer 503 do not limited by the present invention.Further need to prove, in the MnSixOy storage medium layer 503 except comprising the Si element, can also comprise other doped chemicals, for example, if in oxidizing process, also feed other active gasess outside the deoxygenation in the gas of oxidation as containing the gas of F, then except that containing Si, also be mixed with F in the MnOz base storage medium, other doping composition of concrete MnSixOy storage medium layer 503 is not limited by the embodiment of the invention, and its process conditions with oxidation are relevant.
Step S80, composition forms top electrode on the MnSixOy storage medium layer.
With reference to figure 9, Figure 9 shows that the structural representation after composition on the MnSixOy storage medium layer forms top electrode.Composition forms top electrode 207 after depositing the metal level that powers on, and the upper electrode material kind can be electric conducting materials such as TaN, Ta, TiN, Ti, W, Al, Ni, Co or Mn, the perhaps lamination layer structure of forming for above electric conducting material.Depositing the metal level that powers on can realize by modes such as reactive sputtering, PECVD, electron beam evaporations, and patterning process can be realized by the method for photoetching.
Step S90 covers on described top electrode and forms protective dielectric layer.
With reference to Figure 10, Figure 10 shows that at the structural representation that covers on the top electrode after forming protective dielectric layer.Protective dielectric layer 208 covers top electrode 207 and block layer 205 simultaneously.Protective dielectric layer 208 can avoid top electrode 207 oxidized etc. in follow-up cvd dielectric layer process.
Step S100 forms copper embolism and other layer of copper lead-in wire by Damascus technics.
With reference to Figure 11 and Figure 12, Figure 11 shows that covering the structural representation that forms in order to behind the dielectric layer that forms copper embolism and copper lead-in wire on the described protective medium, Figure 12 shows that the structural representation after copper embolism and copper lead-in wire forms.In this step; at first on protective dielectric layer 208, deposit the interlayer dielectric layer 301 and the second block layer 302; and then pass through conventional dual damascene process formation in order to form the through hole (Via) and the groove of copper embolism, then, form copper embolism and other layer of copper lead-in wire.In the process that forms copper embolism and copper lead-in wire, can adopt the method for similar the above step S201 to 204.
Carry out conventional Damascus technics, it is to be noted, when making diffusion impervious layer, identical with Fig. 3 institute adopting process step, promptly deposit one deck CuMn alloy inculating crystal layer, electro-coppering, then in air or contain in the oxygen atmosphere and anneal, eliminate the Cu internal flaw and not with the remaining Mn atom of sidewall SiO reaction, carry out chemico-mechanical polishing then, remove the copper line surface oxide
So far, finish substantially based on the integrated method of the resistor-type memory of MnSixOy storage medium layer and copper-connection backend process.Need to prove, just schematically illustrate in the above procedure on ground floor copper lead-in wire and form manganese oxide based resistor-type memory, but, manganese oxide based resistor-type memory is not limited on ground floor copper goes between or is not limited to only form on ground floor copper lead-in wire, for example can also form on second layer copper lead-in wire, the 3rd layer of copper lead-in wire, those skilled in the art can select according to specific requirement.In addition, during the quantity of integrated manganese oxide based resistor-type memory also is not limited to illustrate in the copper interconnection structure one specifically can select according to the needs of circuit design.
Need to prove, in the copper-connection backend process of above embodiment, preferably adopted dual damascene process.But the of the present invention and integrated approach copper-connection backend process is not limited to dual damascene process, for example, also can be single Damascus technics.
In the above procedure, by manganese oxide based resistor-type memory and copper-connection backend process is integrated, the resistor-type memory of MIM (metal-dielectric layer-metal) structure is embedded into behind the copper-connection of logical circuit in the end structure, especially can embed in the following structure of 45 nanometers or 45 nanometer technology nodes.Thereby realize that logic process and memory manufacturing process are perfect compatible, it is low to reduce preparation cost.On the other hand, for manganese oxide based resistor-type memory, owing to the technology that adopts manganese metal level elder generation silication rear oxidation, the speed of oxidation is relatively slow, and process controllability is stronger, and the yield of MnSixOy storage medium layer and reliability improve; And because the relative compactness characteristics of MnSi, MnSixOy storage medium layer after the oxidation is the oxide densification more of common relatively manganese also, therefore, the resistance of its high-impedance state and low resistance state all is improved (the especially resistance of low resistance state), has lowered the power consumption of memory cell.
Above example has mainly illustrated the method that technology of the present invention is integrated.Although only the some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be in not departing from its purport and scope implements with many other forms.Therefore, example of being showed and execution mode are regarded as illustrative and not restrictive, and under situation about not breaking away from as defined spirit of the present invention of appended each claim and scope, the present invention may be contained various modifications and replacement.
Claims (10)
1. manganese oxide based resistor-type memory and the integrated method of copper-connection backend process is characterized in that, may further comprise the steps:
(1) composition forms the copper lead-in wire that the barrier layer is a manganese silicon oxide compound layer;
(2) on described copper lead-in wire, cover deposition block layer;
(3) the described block layer of patterned etch forms hole to expose the copper lead-in wire zone that desire forms the MnSixOy storage medium layer;
(4) in the hole of described block layer, fill the manganese metal level;
(5) described manganese metal level is carried out silicidation to form the MnSi compound layer;
(6) described MnSi compound layer is carried out oxidation processes to form the MnSixOy storage medium layer;
(7) composition forms top electrode on described MnSixOy storage medium layer;
(8) continue the copper-connection backend process to form copper embolism and following layer of copper lead-in wire;
Wherein, 0.001＜x≤2,2＜y≤5.
2. method according to claim 1 is characterized in that, described copper-connection backend process is 45 nanometer technology node technologies or the following process node technology of 45 nanometers.
3. method according to claim 1 is characterized in that, described step (1) may further comprise the steps:
(1a) deposited copper manganese alloy inculating crystal layer in described groove;
(1b) electro-coppering then;
(1c) copper and described cupromanganese inculating crystal layer are annealed;
(1d) planarization is to remove the cupric oxide and the manganese oxide of unnecessary copper and copper wire surface.
4. method according to claim 1 is characterized in that, described silication is silication in siliceous gas, the ion of silication or silicon injects silication in the silicon plasma.
5. method according to claim 1 is characterized in that, described oxidation is that plasma oxidation, thermal oxidation, ion inject a kind of of oxidation.
6. method according to claim 1 is characterized in that, described very TaN, Ta, TiN, Ti, W, Al, Ni, Co or Mn metal level, the perhaps composite bed of forming for above metal level of powering on.
7. method according to claim 1 is characterized in that, described manganese metal level obtains by sputter, evaporation, atomic layer deposition or electroplating deposition, and described manganese metal layer thickness scope is that about 0.5 nanometer is to about 50 nanometers.
8. method according to claim 1 is characterized in that, described MnSixOy storage medium layer is to mix the storage medium layer that Si forms among the MnOz, wherein, and 1＜z≤3.
9. method according to claim 1 is characterized in that, described MnSixOy storage medium layer is the nanometer composite layer of MnOz and silica, wherein, and 1＜z≤3.
10. method according to claim 1 is characterized in that, described copper-connection backend process adopts dual damascene process.
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| WO2013003979A1 (en) * | 2011-07-06 | 2013-01-10 | 复旦大学 | Method for integrating manganese-oxide-based resistive memory with copper interconnection rear end process |
| WO2019138280A1 (en) * | 2018-01-12 | 2019-07-18 | International Business Machines Corporation | Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers |
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| CN111933796A (en) * | 2020-09-29 | 2020-11-13 | 杭州未名信科科技有限公司 | Resistive random access memory and manufacturing method thereof |
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| CN111916394A (en) * | 2020-08-11 | 2020-11-10 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN111933796A (en) * | 2020-09-29 | 2020-11-13 | 杭州未名信科科技有限公司 | Resistive random access memory and manufacturing method thereof |
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| CN102237309B (en) | 2013-06-12 |
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