CN1976082A - CuxO-based resistance random access memory and producing method thereof - Google Patents
CuxO-based resistance random access memory and producing method thereof Download PDFInfo
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- CN1976082A CN1976082A CNA2006101476699A CN200610147669A CN1976082A CN 1976082 A CN1976082 A CN 1976082A CN A2006101476699 A CNA2006101476699 A CN A2006101476699A CN 200610147669 A CN200610147669 A CN 200610147669A CN 1976082 A CN1976082 A CN 1976082A
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Abstract
A random access storage of resistance based on CuxO is prepared as setting storage media CuxO right below through hole and leading said media into internal of bottom-layer copper lead wire being used as bottom electrode, connecting top of CuxO to top-layer copper lead wire through copper cork in through hole, using top-layer copper lead wire as top electrode and forming said storage media CuxO by plasma oxidation process.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of with Cu
xThe O film is as resistance random access memory of storage medium and preparation method thereof.
Background technology
Memory occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But because the requirement of stored charge, the floating boom of FLASH can not develop unrestricted attenuate with technology generation, and the limit that report prediction FLASH technology is arranged is about 32nm, and this just forces people to seek the more superior nonvolatile memory of future generation of performance.Recently resistance random access memory device (RRAM, resistive random access memory) is because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to, and employed material has phase-change material
[1], the SrZrO that mixes
3 [2], ferroelectric material PbZrTiO
3 [3], ferromagnetic material Pr
1-xCa
xMnO
3 [4], the binary metal oxide material
[5], organic material
[6]Deng.For the material more than the ternary, the accurate control of component, to reduce with the compatibility of integrated circuit technology and cost all be difficult point, and binary metal oxide is (as Nb comparatively speaking
2O
5, Al
2O
3, Ta
2O
5, TixO, NixO
[5], Cu
xO etc.) just especially paid close attention to.This wherein, Cu
xA kind of as in two yuan of metal oxides of O (1＜x＜2), its storage characteristics is proved by experiment
[7]
Present report based on Cu
xThe structure of the memory cell of the resistance memory of O as shown in Figure 1
[5], the device on the substrate links to each other with the copper lead-in wire 3-of lower floor by W embolism 8, and the 3-top is the copper embolism that is arranged in through hole 7, and the copper embolism plays the effect that connects upper copper lead-in wire 3+ and the copper lead-in wire 3-of lower floor, Cu
xO storage medium 4 is positioned at the top of through hole 7 and the below of upper copper lead-in wire 3+, around lower floor copper lead-in wire 3-, through hole 7, the upper copper lead-in wire 3+ is respectively insulating medium layer 1a, 1b and 1c, between 1a and the 1b, be respectively to be used to suppress block layer medium (cap layer) 5a and the 5b that electromigration improves reliability between 1b and the 1c.This structure is difficult to traditional layers for dual damascene copper interconnects technology integrated, and must adopt the copper wiring technique preparation of single Damascus.Just can not be earlier with after through hole and the whole formation of groove, the disposable copper formation copper of inserting goes between and the copper embolism, and necessary elder generation formation through hole is inserted copper formation embolism, forms groove again, inserts copper formation and goes between.
In the said structure, when the signal of telecommunication is applied to Cu
xO resistance two ends, Cu
xThe transformation that O resistance can take place in high resistant and low-resistance, thus 0 and 1 state can be stored.
The Cu that is used for RRAM of present report
xO adopts the thermal oxidation technology preparation, and the speed of thermal oxidation is slow, can produce following problem: 1) if the reaction time is long, the photoresist that does not participate in oxidation reaction as the local copper of mask protection can come to harm, even is removed fully, does not have protective effect; 2) present low k dielectric as main flow contains C usually, and in oxidizing atmosphere, C can sustain damage, and causes k to rise; 3) if reduce the time of oxidation reaction, the defective in the very thin film that can cause again forming in the short time is less, owing to also have high-temperature step in the follow-up technology, defective can further reduce, and causes the decreased performance of memory.
Summary of the invention
The object of the present invention is to provide a kind of based on Cu
xMemory device structures of O and preparation method thereof is to overcome the above-mentioned deficiency of existing similar device.
The Cu that the present invention proposes
xThe memory device of O is a kind of memory device of resistance random access, and its structure is as follows: as the Cu of storage medium
xO is positioned at the through hole below and is deep into lower floor's copper lead-in wire inner, and lower floor's copper lead-in wire is a bottom electrode, Cu
xThe O top then links to each other with the upper copper lead-in wire by the copper embolism that is arranged in through hole, and the upper copper lead-in wire is a top electrode.Cu
xAmong the O, 1＜x≤2.
In the above-mentioned device, also comprise the insulating medium layer and the insulating medium layer that holds groove of receiving opening, copper embolism and (upper and lower layer) copper lead-in wire lay respectively in through hole and the groove, and through hole and groove have run through insulating medium layer; The insulating medium layer of receiving opening and hold between the insulating medium layer of groove etch stop layer is arranged.
In the above-mentioned device, between copper embolism and (upper and lower layer) copper lead-in wire and the insulating medium layer diffusion impervious layer metal is arranged.
In the above-mentioned device, between lower floor's copper lead-in wire and substrate following dielectric layer is arranged, through hole runs through this time dielectric layer, and following embolism is arranged in through hole and contacts with the presumptive area of substrate, and the top surface of following embolism is connected to lower floor's copper lead-in wire.
In the above-mentioned device, lower floor's copper lead-in wire is coupled with first address wire; The upper copper lead-in wire is coupled with second address wire.
The invention provides following method and form above-mentioned memory device: on substrate, form lower floor's copper lead-in wire, form the through hole that holds the copper embolism then and hold the groove that upper copper goes between, below through hole, form then and go deep into the inner Cu of lower floor's copper lead-in wire
xThe O storage medium forms copper embolism and upper copper lead-in wire then.
Further enforcement of the present invention also comprises: dielectric layer under forming on the substrate, dielectric layer formed the diffusion impervious layer medium then with the following embolism of contact substrate presumptive area under formation connected on the surface.
Form lower floor's copper lead-in wire, comprise: at the insulating medium layer that forms embolism under the covering on the substrate, presumptive area at insulating medium layer connects the groove that lower floor's copper lead-in wire is held in this layer formation then, next at trench sidewall deposition barrier layer and inculating crystal layer, deposited copper in groove then, copper and barrier layer that worn then surface is unnecessary form lower floor's copper lead-in wire, then deposition block dielectric layer.
Formation is held the through hole of copper embolism and is held the groove of upper copper lead-in wire, comprise: order forms insulating medium layer, the etch stop layer that holds the copper embolism, the insulating medium layer that holds the upper copper lead-in wire, next on the presumptive area of substrate, constitute the figure of through hole and groove in proper order, order connect receiving opening insulating medium layer, etch stop layer, hold the insulating medium layer of groove, form through hole of filling the copper embolism and the groove of filling the upper copper lead-in wire;
Cu
xThe O storage medium is to adopt the plasma oxidation method to form, and promptly adopts oxygen, oxygenous mist or contains other gas of oxygen element, produces the plasma of O, O plasma and metallic copper reaction generation Cu
xThe O storage medium film.
Form copper embolism and upper copper lead-in wire, comprising: on through hole and trenched side-wall, form diffusion impervious layer and copper seed layer; And filling copper forms copper embolism and upper copper lead-in wire in groove and through hole; And unnecessary copper and the diffusion impervious layer in worn surface; And formation block dielectric layer.
The present invention also provides a kind of system that comprises the desirable memory device of resistor random-access of the present invention, and it comprises a processor, and with the input and output of described processor communication, and the memory that is coupled to this processor; Said memory by the memory device of resistance random access of the present invention as its memory cell.The structure of this memory cell comprises: as the Cu of storage medium
xO is positioned under the through hole and is deep into lower floor copper lead-in wire inside, and lower floor's copper goes between as bottom electrode, Cu
xThe O top then is connected with the upper copper lead-in wire by the copper embolism that is arranged in through hole, and upper copper goes between as top electrode or the like.
The system that is provided can also comprise the wave point that is coupled to this processor.
Description of drawings
Fig. 1 at present report based on Cu
xThe memory cell structure of the RRAM memory device of O storage medium is as the Cu of storage medium
xO is positioned at through hole top, and upper copper lead-in wire below adopts single Damascus technics integrated, Cu
xO adopts the thermal oxidation technique preparation
Fig. 2 the present invention propose based on Cu
xThe RRAM device of O storage medium is as the Cu of storage medium
xO is positioned at the positive bottom of through hole, and it is inner to be embedded in lower floor's copper lead-in wire, can be integrated with dual damascene process, and Cu
xO adopts the preparation of plasma oxidation technology
Fig. 3 to Fig. 9 illustrates some embodiment according to the present invention and forms based on Cu
xThe method of the resistance random access memory of O storage medium.
Figure 10 illustrates the part of system according to an embodiment of the invention.
Figure 11 illustrates the part of system according to still another embodiment of the invention.
Number in the figure: 1a is following dielectric layer, and 1b is an insulating medium layer, and 1c is another insulating medium layer, 1d is another insulating medium layer, and 2a is a diffusion impervious layer, and 2b is a diffusion impervious layer, 3+ is the upper copper lead-in wire, and 3-is lower floor's copper lead-in wire, and 3b+ is a groove, 3b-is a through hole, and 4 is storage medium, and 5a is the block layer, 5b is the block layer, and 5c is a diffusion impervious layer, and 6 is etch stop layer, 7 is the copper embolism, and 7b is a through hole, and 8 are following embolism, 8a is a diffusion impervious layer, and 8b is a through hole, and 9 is substrate, 101 is controller, 102 is wave point, and 103 is memory, and 104 is I/O, 105 is bus, and 1000 is system.
Embodiment
Knot is shown in and describes the present invention in the reference example more completely hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, for the clear thickness that has amplified layer and zone, but should not be considered to the proportionate relationship that strictness has reflected physical dimension as schematic diagram.
At this, reference diagram is the schematic diagram of embodiments of the invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
Should be appreciated that when claiming an element when " on another element " or " on another element, extending ", this element can be directly at " on another element " or directly " on another element, extending ", or also may have insertion element.On the contrary, when claiming an element, there is not insertion element directly at " on another element " or directly when " on another element, extending ".When claiming an element with " another element is connected " or " coupling " with another element, this element can directly connect or be couple to another element, or also can there be insertion element, on the contrary, when claiming an element, there is not insertion element directly with " another element is connected " or direct " coupling " with another element.
Fig. 2 is a profile according to an embodiment of the invention.Wherein:
Following dielectric layer 1a goes up in Semiconductor substrate 9 (hereinafter to be referred as substrate) and forms, through hole 8b be by composition on 1a then etching until running through 1a, exposing the presumptive area of substrate 100, following embolism 8 is formed among the through hole 8b, the presumptive area of following embolism contact substrate 100, it is the impurity diffusion layer (not shown), impurity diffusion layer can be the source or the drain region of field-effect transistor, also can be an element of diode or bipolar transistor.
Following dielectric layer 1a can be the silicon oxide layer that mixes, for example the silica of Doping Phosphorus or boron (BPSG) or mix the silica (PSG) of phosphorus.
Following embolism 8 can be an electric conducting material, W for example, and heavily doped polysilicon contains the electric conducting material of N, as TiN.
Diffusion impervious layer 8a is the electric conducting material that embolism 8 spreads in dielectric layer under stopping, is under the situation of W at following embolism 8, and 8a can be the Ti/TiN composite bed.
Plane above following embolism has covered diffusion impervious layer 5c, be insulating medium layer 1d above 5c, through hole 3b-connects 1d and 5c, is forming the groove 3b-that holds lower floor's copper lead-in wire above the embolism down, be diffusion impervious layer 2a on the trenched side-wall, the copper lead-in wire 3-of lower floor is contained among the groove 3b-.The top surface of following embolism contacts with diffusion impervious layer 2a.
Diffusion impervious layer 5c can be the silicon nitride of silicon nitride or doping, or other diffusion to Cu has the dielectric material of obvious barrier effect.
Insulating medium layer 1d can be a silica, maybe can be the silica through the low-k of overdoping, for example mix C or mix the silica of F, and maybe can be the dielectric of the low-k of other type.
Diffusion impervious layer 2a has the electric conducting material of barrier effect to Cu to the diffusion of dielectric layer, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Under through hole 7b, be Cu
xO storage medium 4 is deep among the copper lead-in wire 3-of lower floor.
On the sidewall of through hole 7b and groove 3b+, covered diffusion impervious layer 2b, Cu
xThe top surface of O storage medium 4 contacts with diffusion impervious layer 2b.
Copper embolism 7 and upper copper lead-in wire 3+ are contained in respectively among through hole 7b and the groove 3b+.
Covered block layer 5b on the surface on the upper copper lead-in wire 3+, held the through hole (not shown) that connects 5b among the block layer medium 5b, further upper copper is drawn.
Insulating medium layer 1b can be a silica, maybe can be the silica through the low-k of overdoping, for example mix C or mix the silica of F, and maybe can be the dielectric of the low-k of other type.
Insulating medium layer 1c can be a silica, maybe can be the silica through the low-k of overdoping, for example mix C or mix the silica of F, and maybe can be the dielectric of the low-k of other type.
Cu
xHaving a part in the composition of O storage medium 4 at least is Cu
xO (x is less than 2) can be Cu
xO (x is less than 2) and Cu
xO (x equals 2) coexistence or pure Cu
xO (x is less than 2).
Diffusion impervious layer 2b has the electric conducting material of barrier effect to Cu to the diffusion of dielectric layer, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Cu
xO storage medium 4 lower surfaces contact with the copper lead-in wire 3-of lower floor, and top surface is connected with upper copper lead-in wire 3+, and the copper lead-in wire 3-of lower floor, upper copper lead-in wire 3+ are respectively as Cu
xThe bottom electrode of O storage medium and top electrode, the copper lead-in wire 3-of lower floor and first address wire are coupled, and the upper copper lead-in wire 3+ and second address wire are coupled (not shown).
Next, the method that forms the resistance random device among some embodiment of the present invention will be explained.Fig. 3 illustrates the profile of the method for the resistance random device that forms embodiment to Fig. 9.
With reference to figure 3, dielectric layer 1a under forming on the substrate 9,1a can be the silicon oxide layers that mixes, and for example the silica of Doping Phosphorus or boron (BPSG) or mix the silica (PSG) of phosphorus can adopt the method preparation of chemical vapour deposition (CVD) and matching surface planarization.Before dielectric layer 1a under the formation, can be in the presumptive area telogenesis impurity diffusion zone (not shown) of substrate 9, impurity diffusion zone can be source, the drain region of field-effect transistor, can be an element of diode, bipolar transistor.
At the presumptive area composition of following dielectric layer, to form the figure of the through hole 8b that can expose the substrate presumptive area, dielectric layer formed through hole 8b under the conventional anisotropic etch process of employing connected, and exposed the presumptive area of substrate.Embolism 8 under in through hole, forming then.Among some embodiment of the present invention, adopt the method for physical sputtering to form the Ti/TiN layer, and then adopt chemical gaseous phase depositing process to form one deck TiN layer, adopt chemical gaseous phase depositing process filling vias 8b to form the W embolism then, adopt worn redundant W and the Ti/TiN in surface of chemico-mechanical polishing, and planarized surface, adopt chemical gaseous phase depositing process deposition one deck barrier layer dielectric layer 5c then.5c can be the silicon nitride of silicon nitride or doping.
With reference to figure 4, the plane above following embolism has covered diffusion impervious layer 5c, can silicon nitride or the silicon nitride of doping, or other diffusion to Cu has the dielectric material of obvious barrier effect.Being insulating medium layer 1d above 5c, can be silica, maybe can be the silica through the low-k of overdoping, for example mix C or mix the silica of F, and maybe can be the dielectric of the low-k of other type.In certain embodiments of the present invention, 5c and 1d adopt the method preparation of chemical vapour deposition (CVD).
Presumptive area composition at insulating medium layer 1d, the figure of the groove of lower floor's copper lead-in wire is held in formation, adopt etching technics to connect 1d and 5c then, form groove 3b-, adopt conventional anisotropic dry etch process to connect 1d and 5c in certain embodiments of the present invention.
Next deposition diffusion impervious layer 2a on trenched side-wall can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.In certain embodiments of the present invention, adopt the method deposition Ta/TaN composite bed of physical sputtering as the barrier layer.The method deposition TaN that adopts ald among other embodiment is as the barrier layer.
Next deposition Cu forms lower floor's copper lead-in wire in groove.In certain embodiments of the present invention, the method that at first adopts physical sputtering to deposit deposits layer of copper and approaches as seed crystal on diffusion impervious layer 2a, adopt the method for electrochemical deposition (ECP) to fill copper then in groove, and annealing is fully grown up the crystal grain of copper then.Adopt unnecessary copper and barrier material on the worn surface of method of chemico-mechanical polishing then, form the upper copper lead-in wire.Deposit a block layer 5a then from the teeth outwards, can be the silicon nitride medium or the silicon nitride medium of doping, for example mix O or mix C, or other diffusion to Cu have obvious barrier effect, electromigration to copper has obvious inhibiting dielectric material, for example CoWP.In certain embodiments, adopt chemical gaseous phase depositing process preparation block layer 5a.
With reference to figure 5, among some embodiment, above block layer 5a, form insulating medium layer 1b, etch stop layer 6, insulating medium layer 1c, etch stop layer 7 successively, in certain embodiments, above block layer 5a, form insulating medium layer 1b, etch stop layer 6, insulating medium layer 1c successively.Available chemical gaseous phase depositing process forms.1b and 1c can be silica, maybe can be the silica through the low-k of overdoping, for example mix C or mix the silica of F, and maybe can be the dielectric of the low-k of other type.Etch stop layer 6 and 7 can be the silicon nitride medium or the silicon nitride medium of doping, for example mix C or mix O, or other etch rate and insulating medium layer 1c has the dielectric material of notable difference.
With reference to figure 6, further enforcement of the present invention, presumptive area composition from the teeth outwards, in certain embodiments, at first form the figure of through hole 7b, connect successively then etch stop layer 7, insulating medium layer 1c,, etch stop layer 6, insulating medium layer 1b, form through hole 7b; Next once more at surperficial presumptive area composition, form the figure of groove 3b+, connect etch stop layer 7, insulating medium layer 1c, form groove 3b+.In some embodiments of the invention, connect the anisotropic dry etch process that adopts routine.
Further enforcement of the present invention, in further embodiments, at first composition and breakthrough form become groove 3b+, and then composition and perforation formation through hole 7b.
Further enforcement of the present invention, in some embodiment again, after forming insulating medium layer 1b, etch stop layer 6 successively above the block layer 5a, composition and connect 6 figures that form through holes above 6 at first, further form insulating medium layer 1c, etch stop layer 7 again, form the figure of groove then in surface patterning, and then disposable each layer of perforation medium forms groove 3b+ and through hole 7b.
Should be noted that the sequencing that forms through hole and groove, is not limitation of the present invention.
Next further enforcement of the present invention cleaned and removed etch residue, in certain embodiments, adopts at first and clean the common process of using the chemical solution wet-cleaned again with plasma reaction.Gently open block layer 5a with the method for dry etching then, expose the copper lead-in wire 3-of lower floor.
Should be noted that employing based on traditional layers for dual damascene copper interconnects technology, form the figure of through hole and groove, and expose lower floor's copper lead-in wire, change to some extent on formation method and order and adjust, is not limitation of the present invention.
Further enforcement of the present invention with reference to figure 7, forms Cu with the plasma oxidation technology
xO storage medium 4.Adopt oxygen, or the mist of employing oxygen and other gas, for example oxidation mixes with argon gas or nitrogen, or adopt other gas that contains oxygen element as source of the gas, flow into the sample room that plasma produces equipment with certain flow rate, produce the O plasma, the copper reaction during the O plasma goes between with the lower floor's copper that exposes forms Cu
xThe O storage medium.Formed Cu
xThe O storage medium, 1＜x≤2.Plasma apparatus for example has PECVD (plasma enhanced chemical vapor deposition), high-density plasma CVD (chemical vapour deposition (CVD)), resist remover, etching machine equipment etc.In the some embodiments of the invention, adopt the plasma reaction etching apparatus, oxygen and argon gas volume ratio are respectively from 1: 1 to 1: 20, range of flow is from 5sccm to 60sccm, oxidation is advanced time range from 2min to 120min, the underlayer temperature scope is in room temperature to 200 degree, and power bracket all obtains having the Cu of storage characteristics from 50w to 300w
xThe O storage medium.Should be noted that oxidizing condition is that the concrete parameter of distinct device is relevant with design, therefore be not limited to the process parameters range of the embodiment of the invention.
Further enforcement of the present invention with reference to figure 8, forms copper embolism 7 and upper copper lead-in wire 3+ in groove 3b+ and through hole 7b.In the some embodiments of the present invention, at first adopt the physical sputtering method on the sidewall of groove 3b+ and through hole 7b, to form diffusion impervious layer 2b and seed crystal copper, adopt electrochemical deposition method then disposable through hole and groove formation copper embolism 7 and the upper copper lead-in wire 3+ of inserting of copper.Diffusion impervious layer 2b and Cu
xThe top surface contact of O storage medium 4.Diffusion impervious layer 2b has the electric conducting material of barrier effect to Cu to the diffusion of dielectric layer, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Further enforcement of the present invention with reference to figure 9, is adopted unnecessary copper, barrier material and the etch stop layer material in the worn surface of method of chemico-mechanical polishing.Form block layer material 5b then on the surface and form memory shown in Figure 2, held the through hole (not shown) that connects 5b among the block layer medium 5b, further upper copper is drawn.Cu
xO storage medium 4 lower surfaces contact with the copper lead-in wire 3-of lower floor, and top surface is connected with upper copper lead-in wire 3+, and the copper lead-in wire 3-of lower floor, upper copper lead-in wire 3+ are respectively as Cu
xThe bottom electrode of O storage medium and top electrode, the copper lead-in wire 3-of lower floor and first address wire are coupled, and the upper copper lead-in wire 3+ and second address wire are coupled (not shown).
Memory device of the present invention and preparation method can with the layers for dual damascene copper interconnects process compatible of routine, promptly after through hole and groove have all formed, disposable copper is inserted, form copper embolism and lead-in wire simultaneously.In addition, adopt the plasma oxygen metallization processes to form Cu
xThe O storage medium has following remarkable advantage: what oxidation rate can be than 200 ℃ of left and right sides thermal oxidations is fast more than 4 times, and oxidation can at room temperature be carried out, and is easy to and other processing step low-k processing step compatibility particularly.
With reference to Figure 10, an embodiment of system provided by the invention, system 1000 can comprise a controller 101, input and output (I/O) device 104, memory 103, bus 105.
With reference to Figure 11, another embodiment of system provided by the invention, system 1000 can comprise a controller 101, input and output (I/O) device 104, memory 103, bus 105 also comprise by bus 105 wave point 102 coupled to each other.Should be noted that the embodiment that scope of the present invention is not limited to have any of these parts or has all these parts.
Controller 101 can comprise one or more microprocessors, digital signal processor, microcontroller etc.The information that memory 103 storage availability are transferred to system 1000 or are transmitted by system 1000 also can be used for store instruction.Memory 103 can be made up of one or more dissimilar memories, flash memory and/or comprise a kind of memory device illustrated for example as the present invention, and its architectural feature is: as the Cu of storage medium
xO is positioned under the through hole and is deep into lower floor copper lead-in wire inside, and lower floor's copper goes between as bottom electrode, Cu
xThe O top then links to each other with the upper copper lead-in wire by the copper embolism that is arranged in through hole, and upper copper goes between as top electrode.
System can use I/O device 104 generation information.
Can utilize wave point 102 usefulness radiofrequency signals that information is sent to wireless communication networks and receive information from wireless communication networks.The example of wave point 102 can comprise antenna or transceiver, but scope of the present invention is not limited to these structures.
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Claims (10)
1, a kind of resistance random access memory device is characterized in that: as the Cu of storage medium
xO is positioned under the through hole and is deep into lower floor copper lead-in wire inside, and lower floor's copper goes between as bottom electrode, Cu
xThe O top then is connected with the upper copper lead-in wire by the copper embolism that is arranged in through hole, and the upper copper lead-in wire is a top electrode; Cu
xAmong the O, 1＜x≤2.
2, resistance random access memory device according to claim 1 is characterized in that also comprising the insulating medium layer of receiving opening, and the insulating medium layer that holds groove, and copper embolism and upper and lower copper lead-in wire lay respectively in through hole and the groove; The insulating medium layer of receiving opening and hold between the insulating medium layer of groove etch stop layer is arranged.
3, resistance random access memory device according to claim 1, it is characterized in that also comprising the diffusion impervious layer metal that reaches between copper embolism and the insulating medium layer between copper lead-in wire and the insulating medium layer, and following dielectric layer between lower floor's copper lead-in wire and substrate and the through hole that has connected this time dielectric layer, following embolism is arranged in through hole and contacts with the presumptive area of substrate, and the top surface of following embolism is connected to lower floor's copper lead-in wire.
4, resistance random access memory device according to claim 1 is characterized in that lower floor's copper lead-in wire is coupled with first address wire; The upper copper lead-in wire is coupled with second address wire.
5, a kind of preparation method of resistance random access memory device as claimed in claim 1 comprises: form lower floor's copper lead-in wire on substrate, form the through hole that holds the copper embolism then and hold the groove that upper copper goes between; Below through hole, form again and go deep into the inner Cu of lower floor's copper lead-in wire
xThe O storage medium forms copper embolism and upper copper lead-in wire at last.
6, method according to claim 5 also comprises: dielectric layer under forming on the substrate, and formation connects down, and dielectric layer forms the diffusion layer medium then with the following embolism of contact substrate presumptive area on the surface.
7, method according to claim 5, wherein, form lower floor's copper lead-in wire, comprise: at the insulating medium layer that forms embolism under the covering on the substrate, connect the groove that lower floor's copper lead-in wire is held in this layer formation in the presumptive area of insulating medium layer then, then and at trench sidewall deposition barrier layer and inculating crystal layer; Deposited copper in groove then; Copper that worn surface is unnecessary and barrier layer form lower floor's copper lead-in wire, then deposition block dielectric layer.
8, method according to claim 5 wherein, forms the through hole that holds the copper embolism and holds the groove that upper copper goes between, and comprising: order forms insulating medium layer, the etch stop layer that holds the copper embolism, the insulating medium layer that holds the upper copper lead-in wire successively; Order constitutes the figure of through hole and groove on the presumptive area of substrate then, order connect receiving opening insulating medium layer, etch stop layer, hold the insulating medium layer of groove, form through hole of filling the copper embolism and the groove of filling the upper copper lead-in wire;
9, method according to claim 5 wherein, forms copper embolism and upper copper lead-in wire, comprising: form diffusion impervious layer and copper seed layer on through hole and trenched side-wall; And filling copper forms copper embolism and upper copper lead-in wire in groove and through hole; And unnecessary copper and the diffusion impervious layer in worn surface; And formation block dielectric layer.
10, a kind of metal is made the system of the memory device of the described resistance random access of claim 1, comprising: a processor, and with the input and output of described processor communication, and the memory that is coupled to this processor; Said memory by the memory device of the described resistance random access of claim 1 as its memory cell.
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