CN101145598B - Method for improving CuxO electric resistance memory fatigue property - Google Patents
Method for improving CuxO electric resistance memory fatigue property Download PDFInfo
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- CN101145598B CN101145598B CN2007100454057A CN200710045405A CN101145598B CN 101145598 B CN101145598 B CN 101145598B CN 2007100454057 A CN2007100454057 A CN 2007100454057A CN 200710045405 A CN200710045405 A CN 200710045405A CN 101145598 B CN101145598 B CN 101145598B
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Abstract
The invention belongs to the field of microelectronic technique and specifically relates to a method for improving the fatigue property of a CuxO memistor. The method removes a superficial CuO layer by means of plasma bombardment, or increases the electrical conductivity thereof, so that the method can reduce the current and voltage of the first-time write operation, protect the CuxO storage medium with resistance conversion property below the CuO layer from the damage of heavy current, and improve the fatigue property of the device.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of Cu of improvement
xThe method of O Memister fatigue properties.
Background technology
Memory occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But because the requirement of stored charge, FLASH can not expand with the technology generation development is unrestricted, runs into serious challenge in the following technology generation of 45nm, and this just forces people to seek the more superior nonvolatile memory of future generation of performance.Recently electric resistance transition memory spare (resistive switching memory) is because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to, and employed material has phase-change material
[1], the SrZrO that mixes
3 [2], ferroelectric material PbZrTiO
3 [3], ferromagnetic material Pr
1-xCa
xMnO
3 [4], the binary metal oxide material
[5], organic material etc.For the material more than the ternary, the accurate control of component, to reduce with the compatibility of integrated circuit technology and cost all be difficult point, and binary metal oxide is (as Nb comparatively speaking
2O
5, Al
2O
3, Ta
2O
5, TixO, NixO
[5], Cu
xO etc.) just especially paid close attention to.Wherein CuxO material and CMOS have superior compatibility, cause and show great attention to.
Memister is by action of electric signals, but makes storage medium inverse conversion between high resistance state and low resistance state, thereby reaches memory action.Present report based on Cu
xThe fatigue properties of O Memister generally not high (less than 1000 times).
[6,7]With the plasma oxidation of routine or the Cu of thermal oxidation process generation
xThe general surface coverage of O (1＜x≤2) film one deck CuO, for the first time during write operation, need add the big voltage higher than normal working voltage to memory, and the big electric current of this moment can be to following Cu
xThe O storage medium produces destruction, causes the erasable number of times of device to descend, and storage characteristics worsens.
Summary of the invention
The object of the present invention is to provide a kind of raising Cu
xThe erasable number of times of O Memister, improve the method for storage characteristics.
The invention provides a kind of Cu of improvement
xThe method of the fatigue properties of O Memister the steps include: at the Cu that grown
xBehind the O storage medium, the using plasma physical bombardment is removed and is covered in Cu
xThe CuO on O top layer, or increase its conductivity, its conductivity increases by one more than the order of magnitude than original, thereby reduces write-operation current, voltage for the first time, the Cu with resistance transfer characteristic below the protection top layer CuO
xThe O storage medium is avoided big electric current and is destroyed.
Cu of the present invention
xO and be covered in its surperficial CuO and adopt plasma oxidation or thermal oxidation process to form simultaneously.
The physical bombardment effect of plasma of the present invention can be adopted physical sputtering, also can adopt dry etching.
The step of the physical bombardment of plasma of the present invention can be at Cu
xAfter O forms, adopt the dry etching when removing the block layer; Or the pre-sputter of employing before the deposition diffusion impervious layer; Or extra step plasma physics bombardment technology
A kind of Cu that improves of the present invention
xThe method of the fatigue properties of O Memister, through after the physical bombardment, it is loose that top layer CuO becomes, and is easy to puncture its breakdown current 1～3 order of magnitude that can descend.
A kind of Cu that improves of the present invention
xThe method of the fatigue properties of O Memister, in the process physical bombardment, the fatigue properties of device can significantly be improved, and erasable operand can improve one more than the order of magnitude.
Description of drawings
Fig. 1 forms the preceding cross-sectional view of second layer copper wiring beginning for dual damascene process.
Fig. 2 is that groove and via hole image etching form cross-sectional view.
Fig. 3 need form cross-sectional view behind the block layer photoetching on the memory cell for etching.
Fig. 4 need form Cu for etching
xCross-sectional view after block layer on the O storage medium copper cash finishes.
Fig. 5 is for removing cross-sectional view behind the photoresist.
Fig. 6 forms CuO layer and Cu for oxidation on the ground floor copper cash
2Cross-sectional view during O layer lamination layer structure.
Fig. 7 does not need to form Cu for relying on to remove
xEtching process during block layer on the O storage medium copper cash is bombarded top layer CuO, the cross-sectional view after perhaps relying on pre-sputter procedure before the deposition diffusion impervious layer top layer CuO being bombarded.
Fig. 8 is a cross-sectional view behind the deposition diffusion impervious layer.
Fig. 9 is a cross-sectional view after deposition inculating crystal layer, electro-coppering, the annealing.
Figure 10 is a cross-sectional view behind the block layer on CMP, the deposition second layer copper cash.
Figure 11 begins preceding cross-sectional view for the copper bolt that forms in the wiring of ground floor copper for single Damascus technics.
Figure 12 forms cross-sectional view for the via hole image etching.
Figure 13 is a cross-sectional view after copper bolt and upper cap layer thereof form.
Figure 14 forms cross-sectional view for the groove figure etching.
Figure 15 need form cross-sectional view after the block layer photoetching on the memory cell for etching.
Figure 16 need form Cu for etching
xCross-sectional view after block layer on the O storage medium copper bolt finishes.
Figure 17 is for removing cross-sectional view behind the photoresist.
Figure 18 forms CuO layer and Cu for oxidation on the copper bolt
2Cross-sectional view during O layer lamination layer structure.
Figure 19 does not need to form Cu for relying on to remove
xEtching process during block layer on the O storage medium copper cash is bombarded top layer CuO, the cross-sectional view after perhaps relying on pre-sputter procedure before the deposition diffusion impervious layer top layer CuO being bombarded.
Figure 20 is a cross-sectional view behind the deposition diffusion impervious layer.
Figure 21 is a cross-sectional view after deposition inculating crystal layer, electro-coppering, annealing, CMP form to the block layer on the second layer copper cash.
Figure 22 is that CuO punctures required electric current, voltage relationship figure before and after the physical bombardment.
Figure 23 is a device fatigue properties resolution chart before and after the physical bombardment.
Number in the figure: 101 ground floor layer insulation media, 102 second layer layer insulation media, 103 the 3rd layer by layer between dielectric, 201 ground floor etch stop layers, 202 second layer etch stop layers, 203 the 3rd layers of etch stop layer, 301 ground floor copper cash upper cap layers, 302 second layer copper cash upper cap layers, diffusion impervious layer around the 303 bronze medal bolt upper cap layers, 401 ground floor copper cash, diffusion impervious layer around the 402 bronze medal bolts, diffusion impervious layer around 403 second layer copper cash, the wiring of 500 ground floor copper, 501 do not need to form Cu
xThe ground floor copper wiring of O storage medium, 502 need to form Cu
xThe ground floor copper wiring of O storage medium, 600 is the copper bolt, 601 do not need to form Cu
xThe copper bolt of O storage medium, 602 need to form Cu
xThe copper bolt of O storage medium, 603 second layer copper wirings, 800 through the Ar plasma bombardment or with the top layer CuO of fluorine-containing plasma etching, and 801 have the Cu of transfer characteristic
xO, 802 through the Ar plasma bombardments or with the top layer CuO of fluorine-containing plasma etching, 901 grooves and through hole, 901a through hole, 901b groove, 902PMD layer, 903 tungsten bolts, 904 photoresists.
Embodiment
Describe the present invention in the reference example more completely below in conjunction with being shown in, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, for the clear thickness that has amplified layer and zone.
At this reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
Fig. 1 to Figure 11 is that Fig. 1 to Figure 11 shows Cu according to the profile of embodiments of the invention 1
xO Memister and dual damascene process collection also are formed at the ground floor copper wiring process between connecting up with the second layer, Cu
xO is formed on the copper cash first time, under the copper bolt.But the present invention is not limited to present embodiment.
Fig. 1 has showed through conventional layers for dual damascene copper interconnects technology, proceeds to the wiring of ground floor copper and makes end, the profile after block layer, inter-level dielectric (IMD), etch stop layer deposition finish.902 is pmd layer, is meant the dielectric layer between ground floor wiring and the MOS device, and it can be dielectric materials such as silica PSG of mixing phosphorus; 903 is the tungsten bolt, and it connects ground floor wiring and MOS device; Pmd layer is illustrated as the CMOS logical device that front-end process forms below 902.501 parts for the wiring of ground floor copper, the storage medium of not growing above it, 502 another part for the wiring of ground floor copper, its top will form storage medium; 101,102,103 is the layer insulation dielectric layer, and it can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; 201,202,203 is etch stop layer, can be Si
3N
4, SiON, SiCN; 301 for block layer (liner), can be Si
3N
4Deng dielectric material, the main effects such as electromigration that play the diffusion barrier effect of copper and prevent copper, 401 be diffusion barrier once, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Fig. 2 is that groove and the making of via hole image etching finish, the profile before the block layer (liner) of copper top is opened; 901 groove and through holes for etching formation.
Fig. 3 is profile after the photoetching, and needs are formed Cu
xBlock layer 301 on the copper cash 502 of O storage medium adopts the way of resist exposure, does not need to form Cu
xBlock layer 301 on the copper cash 501 of O storage medium adopts the photoresist protection, and 904 is the photoresist that stays after the exposure.
Fig. 4 need form Cu for etching
xBlock layer (liner) on the O storage medium copper cash 502 schematic diagram that finishes by dry etching, removes the block layer on 502 layers, and block layer 301 changes.
Fig. 5 removes the later schematic diagram of photoresist 904.
Fig. 6 is for forming Cu by methods such as plasma oxidation or thermal oxidations
xO storage medium schematic diagram, 800 is the CuO layer, 700 is Cu
2The O layer; Fig. 6 a forms CuO layer 800 and Cu after plasma oxidation or the thermal oxidation
2The lamination layer structure of O layer 700, Fig. 6 b are the single layer structure that forms Cu2O layer 700 after plasma oxidation or the thermal oxidation; Copper cash 501 is done the mask protective effect by the block layer 301 on it, and not oxidized.
Fig. 7 does not need to form Cu for etching
xBlock layer (liner) on the O storage medium copper cash 501 schematic diagram that finishes; Fig. 7 a is etching block layer 301 o'clock because the CuO layer 800 on the copper cash 502 has etching selection with block layer 301, with CuO layer 800 as the mask layer schematic diagram; Fig. 7 a is etching block layer 301 o'clock, because the Cu on the copper cash 502
2O layer 700 has etching selection with block layer 301, uses Cu
2O layer 700 is as the mask layer schematic diagram.
Fig. 8 becomes Cu for Fig. 7 a structure C uO layer 800 carries out the surface reduction treatment conversion
2Schematic diagram behind the O layer, CuO layer 800 all is converted to the Cu with storage medium characteristic
2O layer 700.
Fig. 9 is a schematic diagram behind the deposition diffusion impervious layer, 402 is diffusion impervious layer, and Cu is had barrier effect to the diffusion of dielectric layer, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Figure 10 is deposition inculating crystal layer, plating growth copper and annealing back schematic diagram, and 603 is the wiring of the second bronze medal copper, and 600 is the copper bolts that connect ground floor copper cash 501 and second layer copper cash 603.
Figure 11 is a deposition block layer back schematic diagram behind the CMP, and 302 for block layer (liner), can be Si
3N
4Deng dielectric material, mainly play the diffusion barrier effect of copper and prevent the effects such as electromigration of copper.
Next, will explain the integrated step of concrete technology of present embodiment with Fig. 1 to cross sectional view shown in Figure 11.
With reference to figure 1, through conventional layers for dual damascene copper interconnects technology, proceed to ground floor copper wiring and make and finish, after block layer 301, inter-level dielectric (IMD) 103, etch stop layer 203 depositions finish, as the initial step of the integrated step of technology of this embodiment.
Further enforcement of the present invention, with reference to figure 2, by with two different masks, successively chemical wet etching forms groove and through hole 901, and the formation of through hole 901 is not limited to the priority etching order of dielectric layer 102 and 103 among the present invention.
Further enforcement of the present invention with reference to figure 3, with another mask photoetching, exposure, forms photoresist 904 diagrammatic sketch cases.
Further enforcement of the present invention, with reference to figure 4, the Si in the dry etching ground floor copper wiring 502
3N
4Block layer 301, thus the ground floor copper cash 501 that will form the CuxO storage medium is exposed.
Further enforcement of the present invention with reference to figure 5, adopts conventional wet method or dry ashing to remove photoresist 904.
Further enforcement of the present invention with reference to figure 6, is carried out plasma oxidation to pattern exposed surface copper cash 501, generates Cu
2O layer 801 and top layer CuO layer 800;
Further enforcement of the present invention, with reference to figure 7, dry etching will not need to form the block layer 301 in the ground floor copper wiring 501 of storage medium, block layer 301 is silicon nitride or other silicon base medium materials, the general employing contains F base gas, CuO layer 800 is bombarded, make it to become high electricity and lead CuO 802, simultaneously etching is removed the block layer 301 in the ground floor copper wiring 501 that does not need to form storage medium;
In another embodiment, behind the block layer of removing through dry etching in the ground floor copper wiring 501 do not need to form storage medium 301, carry out backwash with Ar gas plasma, remove the natural oxidizing layer on copper cash 501 surfaces, bombard top layer CuO 800 simultaneously, make it to become high electricity and lead CuO 802.
In another embodiment, can additionally increase by one implant steps: radio-frequency power is more than 300 watts, and underlayer temperature 0～250 is spent the Ar plasma.Make top layer CuO 800 become high electricity and lead CuO 802.
Further enforcement of the present invention, with reference to figure 8, deposition diffusion impervious layer TaN/Ta 402;
Further enforcement of the present invention, with reference to figure 9, growth inculating crystal layer Cu, re-plating growth Cu forms copper bolt 600 and second layer copper cash 603, then annealing;
Further enforcement of the present invention, with reference to Figure 10, CMP, CVD deposition Si then
3N
4Block layer 302.
So far, wiring of second layer copper and cuprous oxide memory cell form, and the copper wiring technique step no longer describes in detail not within summary of the invention thereafter.
Figure 22 is that CuO punctures required electric current, voltage relationship figure before and after the physical bombardment, handles through the Ar plasma bombardment, and the puncture voltage of CuO drops to 2V from 18V, and breakdown current drops to 0.2mA from 40mA.
Figure 23 is device fatigue properties resolution charts before and after the physical bombardment, handles through the Ar plasma bombardment, and the erasable number of operations of device is increased to 8000 times from 350 times, and fatigue properties significantly improve.
Figure 11 to Figure 21 is two a profile according to the embodiment of the present invention, and Figure 12 to Figure 21 shows Cu
xO Memister and single Damascus technics collection also are formed at the ground floor copper wiring process between connecting up with the second layer, Cu
xO is formed under the copper cash second time, on the copper bolt.But the present invention is not limited to present embodiment.
Figure 11 has showed through conventional single Damascus copper wiring technique, proceeds to the wiring of ground floor copper and makes end, the profile after block layer 301, inter-level dielectric (IMD) 101 depositions finish.902 is pmd layer, is meant the dielectric layer between ground floor wiring and the MOS device, and it can be dielectric materials such as silica PSG of mixing phosphorus; 903 is the tungsten plug, and it connects ground floor wiring and MOS device; Pmd layer is illustrated as the CMOS logical device that front-end process forms below 902.500 are the wiring of ground floor copper; 101,102 is the layer insulation dielectric layer, and it can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; 201 is etch stop layer, can be Si
3N
4, SiON, SiCN; 301 for block layer (liner), can be Si
3N
4Deng dielectric material, the main effects such as electromigration that play the diffusion barrier effect of copper and prevent copper, 401 be diffusion barrier once, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WNx, WNxCy, TiZr/TiZrN etc.
Figure 12 makes for the via hole image etching and finishes the profile that ground floor copper cash 500 is opened; 901a is the through hole that etching forms.
Figure 13 is that copper bolt, block layer are made the schematic diagram after finishing, and 402 is diffusion impervious layer, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WN
x, WN
xC
y, TiZr/TiZrN etc.; 601 for not needing to form Cu
xThe copper bolt of O storage medium, 602 for needing to form Cu
xThe copper bolt of O storage medium.
Schematic diagram after Figure 14 finishes for the etching inter-level dielectric forms groove 901b, 103 is the layer insulation dielectric layer, it can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; The 901b groove is mainly used to form second layer copper cash.
Figure 15 is profile after the photoetching, and needs are formed Cu
xBlock layer 303 on the copper cash 602 of O storage medium adopts the way of resist exposure, does not need to form Cu
xBlock layer 303 on the copper cash 601 of O storage medium adopts the photoresist protection, and 904 is the photoresist that stays after the exposure.
Figure 16 need form Cu for etching
xBlock layer (liner) on the O storage medium copper bolt 602 schematic diagram that finishes by dry etching, removes the block layer on 502 layers, and block layer 303 changes.
Figure 17 removes the later schematic diagram of photoresist 904.
Figure 18 is for forming Cu by methods such as plasma oxidation or thermal oxidations
xO storage medium schematic diagram, 800 is the CuO layer, 801 is Cu
2The O layer because the mask of block layer 303 is protected, does not have oxidized on the copper bolt 601.
Figure 19 will not need to form the block layer 303 on the copper bolt 601 of storage medium for dry etching, block layer 303 is silicon nitride or other silicon base medium materials, the general employing contains F base gas, CuO layer 800 is bombarded, form high electricity and lead CuO 802, simultaneously etching is removed the block layer 303 on the copper bolt 601 that does not need to form storage medium;
In another embodiment, behind the block layer of removing through dry etching on the copper bolt 601 do not need to form storage medium 303, carry out backwash with Ar gas plasma, remove the natural oxidizing layer on copper bolt 601 surfaces, bombard top layer CuO 800 simultaneously, make it to become high electricity and lead CuO 802.
In another embodiment, can additionally increase by one implant steps: radio-frequency power is more than 300 watts, and underlayer temperature 0～250 is spent the Ar plasma.Make top layer CuO 800 become high electricity and lead CuO 802.
Figure 20 is for being schematic diagram behind the deposition diffusion impervious layer, and 403 is diffusion impervious layer, and Cu is had barrier effect to the diffusion of dielectric layer, can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WN
x, WN
xC
y, TiZr/TiZrN etc.
Figure 21 deposits block layer back schematic diagram after depositing inculating crystal layer, electroplating growth copper, annealing, CMP, 603 is the wiring of the second bronze medal copper, and 302 is block layer (liner), can be Si
3N
4Deng dielectric material, mainly play the diffusion barrier effect of copper and prevent the effects such as electromigration of copper.
Next, will explain the integrated step of concrete technology of present embodiment with Figure 11 to cross sectional view shown in Figure 21.
With reference to Figure 11, through conventional single Damascus copper wiring technique, proceed to the wiring of ground floor copper and make and finish, after block layer 301, inter-level dielectric 102 depositions finish, as the initial step of the integrated step of technology of this embodiment.
Further enforcement of the present invention with reference to Figure 12, forms through hole 901a by photoetching, etching block layer 301 and inter-level dielectric (IMD) 102.
Further enforcement of the present invention, with reference to Figure 13, CVD deposition Ta/TaN diffusion impervious layer 402, long inculating crystal layer Cu, re-plating growth Cu forms copper bolt 601 and 602, and CVD deposited Si after CMP ground off unnecessary copper
3N
4Block layer 303.
Further enforcement of the present invention, with reference to Figure 14, CVD deposits interlayer dielectric layer 103, forms groove 901b by photoetching, etching interlayer dielectric layer 103 then.
Further enforcement of the present invention with reference to Figure 15, with another mask photoetching, exposure, forms photoresist 904 diagrammatic sketch cases.
Further enforcement of the present invention, with reference to Figure 16, the Si on the dry etching copper bolt 602
3N
4Block layer 303, thus make formation Cu
xThe copper bolt 602 of O storage medium exposes.
Further enforcement of the present invention with reference to Figure 17, adopts conventional wet method or dry ashing to remove photoresist 904.
Further enforcement of the present invention with reference to Figure 18, is carried out plasma oxidation to pattern exposed copper layer 602, generates Cu
xO;
Further enforcement of the present invention, with reference to Figure 19, dry etching will not need to form the block layer 303 on the copper bolt 601 of storage medium, block layer 303 is silicon nitride or other silicon base medium materials, the general employing contains F base gas, bombard top layer CuO 800 simultaneously, make it to become high electricity and lead CuO 802, simultaneously etching is removed the block layer 303 on the copper bolt 601 that does not need to form storage medium;
In another embodiment, behind the block layer of removing through dry etching on the copper bolt 601 do not need to form storage medium 303, carry out backwash with Ar gas plasma, remove the natural oxidizing layer on copper bolt 601 surfaces, bombard top layer CuO 800 simultaneously, make it to become high electricity and lead CuO 802.
In another embodiment, can additionally increase by one implant steps: radio-frequency power is more than 300 watts, and underlayer temperature 0～250 is spent the Ar plasma.Make top layer CuO 800 become high electricity and lead CuO 802.
Further enforcement of the present invention, with reference to Figure 20, growth inculating crystal layer Cu, re-plating growth Cu, annealing then, CMP removes unnecessary Cu, then CVD deposition Si
3N
4Block layer 302, second layer copper cash 603 forms.
Further enforcement of the present invention, with reference to Figure 21, so far, wiring of second layer copper and cuprous oxide memory cell form, and the copper wiring technique step no longer describes in detail not within summary of the invention thereafter.
Figure 22 is that CuO punctures required electric current, voltage relationship figure before and after the physical bombardment, handles through the Ar plasma bombardment, and the puncture voltage of CuO drops to 2V from 18V, and breakdown current drops to 0.2mA from 40mA.
Figure 23 is device fatigue properties resolution charts before and after the physical bombardment, handles through the Ar plasma bombardment, and the erasable number of operations of device is increased to 8000 times from 350 times, and fatigue properties significantly improve.
List of references
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Claims (4)
1. one kind is improved Cu
xThe method of O Memister fatigue properties is characterized in that: at the Cu that grown
xBehind the O storage medium, the physical bombardment of using plasma is removed and is covered in Cu
xO surface C uO layer, or increase the conductivity of CuO layer, the conductance of CuO layer must increase by one more than the order of magnitude, thereby reduces write-operation current, voltage for the first time, the Cu with resistance transfer characteristic below the protection top layer CuO
xThe O storage medium is avoided big electric current and is destroyed, here 1＜x≤2.
2. method according to claim 1 is characterized in that described Cu
xO and be covered in its surperficial CuO and adopt plasma oxidation or thermal oxidation process to form simultaneously.
3. method according to claim 1 is characterized in that the physical bombardment of described plasma, adopts physical sputtering, perhaps adopts dry etching;
4. method according to claim 1 is characterized in that the physical bombardment of described plasma, is at Cu
xAfter O forms, adopt the dry etching when removing the block layer; Perhaps adopt the pre-sputter before the deposition diffusion impervious layer; Perhaps adopt the additional plasma physical bombardment.
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| CN102479924B (en) * | 2010-11-30 | 2014-01-01 | 中芯国际集成电路制造(北京)有限公司 | Manufacture method of phase change memory |
| CN102569647B (en) * | 2010-12-22 | 2014-02-05 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for phase change memory |
| CN109728161B (en) * | 2018-12-19 | 2020-10-09 | 北京大学 | Oxide memristor based on CMOS (complementary Metal oxide semiconductor) process platform and preparation method thereof |
| CN113053942B (en) * | 2021-03-15 | 2021-11-23 | 中国电子科技集团公司第五十八研究所 | High-radiation-resistance magnetic random access memory device and preparation method thereof |
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| CN1976082A (en) * | 2006-12-21 | 2007-06-06 | 复旦大学 | CuxO-based resistance random access memory and producing method thereof |
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| CN1167338A (en) * | 1996-03-25 | 1997-12-10 | 东芝株式会社 | Method for making semiconductor device |
| CN1976082A (en) * | 2006-12-21 | 2007-06-06 | 复旦大学 | CuxO-based resistance random access memory and producing method thereof |
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