CN102569647B - Manufacturing method for phase change memory - Google Patents
Manufacturing method for phase change memory Download PDFInfo
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- CN102569647B CN102569647B CN201010601802.XA CN201010601802A CN102569647B CN 102569647 B CN102569647 B CN 102569647B CN 201010601802 A CN201010601802 A CN 201010601802A CN 102569647 B CN102569647 B CN 102569647B
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Abstract
The invention provides a manufacturing method for a phase change memory. The manufacturing method comprises the following steps of: providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate, an interconnection structure and a bottom electrode are formed in the interlayer dielectric layer, the interconnection structure is flush with the interlayer dielectric layer, and a part of the interlayer dielectric layer covers the bottom electrode; forming a protective layer above the interlayer dielectric layer; forming an opening for exposing the bottom electrode in the protective layer and the interlayer dielectric layer; cleaning the side wall and the bottom of the opening by using a plasma etching process; forming a phase change layer in the opening; and removing the protective layer on the surface of the interlayer dielectric layer. According to the manufacturing method, the yield of the phase change memory is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the manufacture method of phase transition storage.
Background technology
Phase transition storage (Phase Change Random Access Memory, PCRAM) technology is that the conception that can be applied to phase change memory medium at late 1960s proposition phase-change thin film based on S.R.Ovshinsky is set up.As a kind of emerging nonvolatile storage technologies, phase transition storage all has larger superiority in all many-sides such as read or write speed, read-write number of times, data hold time, cellar area, many-valued realizations to flash memory, has become the focus of current non-volatile memory technologies research.
In phase transition storage, can be by heat-treating having recorded the phase change layer of data, change the value of the store status of memory, particularly, the phase-change material that forms phase change layer can enter due to the heating effect of applied electric current crystalline state or noncrystalline state.When phase change layer is during in crystalline state, the resistance of PCRAM is lower, and now memory assignment is " 0 ".When phase change layer is during in noncrystalline state, the resistance of PCRAM is higher, and now memory assignment is " 1 ".Therefore, PCRAM utilizes the nonvolatile memory that carrys out writing/reading data when the resistance difference of phase change layer during in crystalline state or noncrystalline state.
The manufacture method of existing phase transition storage please refer to Fig. 1～Fig. 4.First, please refer to Fig. 1, Semiconductor substrate 100 is provided, in described Semiconductor substrate 100, form first medium layer 101, interior formation the first bottom electrode 102 of described first medium layer 101 and conductive plunger 103, described the first bottom electrode 102 and conductive plunger 103 flush with described first medium layer 101.In described Semiconductor substrate 100, be also formed with transistor, described transistor is for driving the phase change layer of follow-up formation, and described conductive plunger 103 is as a part for described transistorized interconnection structure, for being electrically connected to the interconnection line of follow-up formation.
Then, still with reference to figure 1, on described first medium layer 101, form second medium layer 104, in described second medium layer 104, be formed with the second bottom electrode 105 flushing with described second medium layer 104, described the second bottom electrode 105 is positioned on described the first bottom electrode 102, and described the second bottom electrode 105 forms bottom electrode with described the first bottom electrode 102.
Then, please refer to Fig. 2, above described second medium layer 104, form the 3rd dielectric layer 107.Then, the 3rd dielectric layer 107 and second medium layer 104 described in etching, at described the 3rd dielectric layer 107 and the interior formation groove of second medium layer 104, described groove exposes the conductive plunger 103 of below.Then, depositing metal layers in described groove, forms interconnection line 106, and described interconnection line is electrically connected to the conductive plunger 103 of below, the interconnection structure of both transistor formeds.
Then, please refer to Fig. 3, the 3rd dielectric layer 107 described in etching, at the interior formation opening of described the 3rd dielectric layer 107, described opening exposes the second bottom electrode 105 of below.
Then, please refer to Fig. 4, in described opening, fill phase-change material, form phase change layer 108.
In the Chinese patent application that is CN101728492A at publication number, can find more information about existing phase transition storage.
Find in practice, the yield that existing method is made phase transition storage is lower.
Summary of the invention
The problem that the present invention solves has been to provide a kind of manufacture method of phase transition storage, has improved the yield of phase transition storage.
For addressing the above problem, the invention provides a kind of manufacture method of phase transition storage, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, be formed with interlayer dielectric layer, in described interlayer dielectric layer, be formed with interconnection structure and bottom electrode, described interconnection structure flushes with described interlayer dielectric layer, and described bottom electrode top is coated with the described interlayer dielectric layer of part;
Above described interlayer dielectric layer, form protective layer;
In described protective layer and interlayer dielectric layer, form the opening that exposes described bottom electrode;
Utilize plasma etch process, the sidewall of described opening and bottom are carried out to cleaning;
In opening, form phase change layer;
Remove the protective layer on described interlayer dielectric layer surface.
Alternatively, the thickness range of described protective layer is 30～500 dusts.
Alternatively, the material of described protective layer is silica, silicon nitride, silicon oxynitride, carborundum, tantalum oxide, aluminium oxide, hafnium oxide, zirconia or tungsten oxide.
Alternatively, the manufacture method of described protective layer is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.
Alternatively, the ion of ion, nitrogen containing plasma or inert gas and mixing of nitrogen containing plasma that the ion that described plasma etch process adopts is inert gas.
Alternatively, the ion of described inert gas is one or both in argon ion, helium ion; Described nitrogen containing plasma is one or both in nitrogen ion, ammonium ion.
Alternatively, the power bracket of described plasma etching is 100～1000W.
Alternatively, the material of described interlayer dielectric layer is silica, silicon nitride, carborundum or silicon oxynitride.
Compared with prior art, the present invention has the following advantages:
The manufacture method of phase transition storage provided by the invention, first in Semiconductor substrate, form interlayer dielectric layer, in described interlayer dielectric layer, be formed with interconnection structure and bottom electrode, described bottom electrode top is coated with the described interlayer dielectric layer of part, then on described interlayer dielectric layer, form protective layer, then in described protective layer and interlayer dielectric layer, form opening, then, described opening is carried out to clean plasma etch step, because described interlayer dielectric layer surface has protective layer, described protective layer can prevent that the accumulation that produces in described plasma etch process is on the surface of described interconnection structure, thereby avoided electric discharge (arcing) phenomenon between described bottom electrode and described opening, thereby protected the transistor that is positioned at Semiconductor substrate, make described transistor avoid receiving the impact of described discharging current, improved the yield of phase transition storage, and described cleaning is by the pollutant removal of the sidewall of described opening and bottom, improved the adhesiveness between phase change layer and described interlayer dielectric layer and bottom electrode.
Accompanying drawing explanation
Fig. 1～Fig. 4 is the phase transition storage manufacture method cross-sectional view of prior art;
Fig. 5 is phase transition storage manufacture method schematic flow sheet of the present invention;
Fig. 6～Figure 11 is the manufacture method cross-sectional view of the phase transition storage of one embodiment of the invention.
Embodiment
The yield of the phase transition storage that existing method is made is low.Through inventor, study discovery, the low reason of yield that causes existing phase transition storage is owing to having pollutant film or a natural oxidizing layer between phase change layer and the bottom electrode of below, thereby described phase change layer is easy and the bottom electrode of below disconnects (open), has affected the yield of phase transition storage.
Particularly, incorporated by reference to Fig. 3, after the interior formation opening of described the 3rd dielectric layer 107, described the second bottom electrode 105 exposes, described the second bottom electrode 105 is owing to being exposed in air, and therefore described the second bottom electrode 105 easily oxidation occurs and forms natural oxidizing layer.And come from the particle in clean room, the pollution that the pollutant such as water and organic substance and inorganic matter can make the second bottom electrode 105 that described opening exposes and part second medium layer 104 surface be subject to described pollutant, described pollutant can form pollutant film at described the second bottom electrode 105 and part second medium layer 104 surface, between the phase change layer that this pollutant film can affect follow-up formation and described the second bottom electrode 105, be electrically connected to disconnection, make described phase change layer cannot accept the phase change current from the second bottom electrode 105, thereby phase change layer cannot carry out phase transformation operation.
Therefore, need to remove described pollutant film, inventor considers to utilize the technique of plasma etching to remove described pollutant.When carrying out plasma etch process, the surface of the part second medium layer 104 that described in a large amount of plasma bombardments, the surface of the 3rd dielectric layer 107, described opening expose and the surface of the second bottom electrode 105, thereby the pollutant film on described second medium layer 104 surface and the second bottom electrode 105 surfaces is removed, make the comparatively cleaning of surface of described second medium layer 104 surface and the second bottom electrode 105, be conducive to improve the reliability being electrically connected between phase change layer and the second bottom electrode 105.
But when carrying out the technique of described plasma etching, a large amount of electrons that produce in plasma etching industrial process are gathered in the surface of described the second bottom electrode 105 and interconnection line 106.Due in order to reduce the required electric current of phase change layer phase transformation, need to reduce the contact area between phase change layer and described the second bottom electrode 105, the area of described the second bottom electrode 105 is conventionally very little.And in order to reduce the resistance of interconnection structure, the area of described interconnection line 106 is conventionally larger, this makes the area of described the second bottom electrode 105 be far smaller than the area of described interconnection line 106, thereby the number of the electronics of the surface distributed of described the second bottom electrode 105 is far less than the number of the electronics of described interconnection line 106 surface distributed, this makes to produce between described the second bottom electrode 105 and interconnection line 106 surfaces the difference of number of electrons, the number of the electronics on the second bottom electrode 105 surfaces is far smaller than the number of the electronics on interconnection line 106 surfaces, thereby produce electrical potential difference between described the second bottom electrode 105 and described interconnection line 106, this electrical potential difference make described electronics from more interconnection line 106 surfaces of number towards the second less bottom electrode 105 apparent motions of number of electrons, until described the second bottom electrode 105 is zero with the surface potential difference of described interconnection line 106.At described electronics from the more interconnection line 106 of number during towards described the second bottom electrode 105 apparent motion, can be through described Semiconductor substrate 100, conductive plunger 103, at the interior formation electric current of described Semiconductor substrate 100, the process of above-mentioned electron motion is called discharge process (arcing).Electric current through described Semiconductor substrate in this discharge process will damage or burn out the interior transistor of described Semiconductor substrate 100, and this cannot work described transistor, thereby has affected the yield of phase transition storage.
In order to solve above-mentioned topic, the present invention proposes a kind of manufacture method of phase transition storage.Incorporated by reference to the manufacture method schematic flow sheet of the phase transition storage of the present invention shown in Fig. 5, described method comprises:
Step S1, Semiconductor substrate is provided, in described Semiconductor substrate, is formed with interlayer dielectric layer, in described interlayer dielectric layer, be formed with interconnection structure and bottom electrode, described interconnection structure flushes with described interlayer dielectric layer, and described bottom electrode top is coated with the described interlayer dielectric layer of part;
Step S2 forms protective layer above described interlayer dielectric layer;
Step S3 forms the opening that exposes described bottom electrode in described protective layer and interlayer dielectric layer;
Step S4, utilizes plasma etch process, and the sidewall of described opening and bottom are carried out to cleaning;
Step S5 forms phase change layer in opening;
Step S6, removes the protective layer on described interlayer dielectric layer surface.
Below in conjunction with specific embodiments technical scheme of the present invention is described in detail.
For technical scheme of the present invention is described better, please refer to the manufacture method cross-sectional view of the phase transition storage of the one embodiment of the invention shown in Fig. 6～Figure 11.
First, please refer to Fig. 6, Semiconductor substrate 200 is provided, in described Semiconductor substrate 200, be formed with first medium layer 201, in described first medium layer 201, be formed with the first bottom electrode 202 and conductive plunger 203.Described the first bottom electrode 202 and conductive plunger 203 flush with described first medium layer 201.Between described the first bottom electrode 202 and described first medium layer 201 and between described conductive plunger 203 and described first medium layer 201, be also formed with contact metal layer 211.
As an embodiment, in described Semiconductor substrate 200, be also formed with transistor, described transistor is for driving the phase change layer of follow-up formation.Described transistor is electrically connected to the interconnection line of follow-up formation by described conductive plunger 203.
In the present embodiment, the material of described Semiconductor substrate 200 is silicon.In other embodiment, the material of described Semiconductor substrate 200 can also be germanium silicon or silicon-on-insulator.
The material of described first medium layer 201 is insulation material.The material of described first medium layer 201 can be silica, silicon nitride, carborundum or silicon oxynitride.The thickness range of described first medium layer 201 is 500～8000 dusts, and for example the thickness of described first medium layer 201 can be 500 dusts, 3000 dusts, 500 dusts or 8000 dusts.In one embodiment of the invention, the material silicon nitride of described first medium layer 201, its thickness is 5000 dusts, described first medium layer 201 can utilize chemical vapor deposition method to make.Utilize described chemical vapor deposition method to make the method for described silicon nitride same as the prior art, the known technology as those skilled in the art, does not explain at this.
As an embodiment, the material of described conductive plunger 203 is tungsten.In other embodiment, the material of described conductive plunger 203 can also be other metals such as copper, aluminium.The interconnection line that described conductive plunger 203 forms for the processing step with follow-up forms interconnection structure.
Described the first bottom electrode 202 by with subsequent process steps in the second bottom electrode of forming form bottom electrode, described bottom electrode provides phase change current for the phase change layer forming to subsequent process steps.
As one embodiment of the present of invention, the material of described the first bottom electrode 202 is identical with the material of described conductive plunger 203, the material that is described the first bottom electrode 202 is tungsten, thereby described the first bottom electrode 202 and described conductive plunger 203 can adopting process step be made, thereby save processing step.
In other embodiments of the invention, the material of described the first bottom electrode 202 can also be polysilicon.
The thickness range of described the first contact metal layer 211 is 10～100 dusts, and described the first contact metal layer 211 is for improving the adhesiveness between described the first bottom electrode 202 and described first medium layer 201 and between described conductive plunger 203 and described first medium layer 201.As an embodiment, described the first contact metal layer 211 consists of titanium layer and titanium nitride layer, and wherein said titanium nitride layer is adjacent with described the first bottom electrode 201, and described titanium layer is adjacent with described interlayer dielectric layer.
As another embodiment of the present invention, described the first contact metal layer 211 can also consist of tantalum layer and tantalum nitride layer, and wherein said tantalum nitride layer is adjacent with described the first bottom electrode 201, and described tantalum layer is adjacent with described interlayer dielectric layer.
Then, please refer to Fig. 7, on described first medium layer 201, form second medium layer 204, be formed with the second bottom electrode 205 in described second medium layer 204, described the second bottom electrode 205 flushes with described second medium layer 204.
As preferred embodiment, between described the second bottom electrode 205 and described second medium layer 204, be also formed with the second contact metal layer 210.The thickness range of described the second contact metal layer 210 is 10～100 dusts.
Described the second contact metal layer 210 is for improving the adhesiveness between described the second bottom electrode 205 and described second medium layer 204.Described the second contact metal layer 210 consists of titanium layer and tantalum nitride layer or described the second contact metal layer 210 consists of tantalum layer and tantalum nitride layer.Described titanium layer or tantalum layer are near described the second bottom electrode 205, and described tantalum nitride layer is near described second medium layer 204.The manufacture method of described titanium layer, tantalum layer, tantalum nitride layer and titanium nitride layer is same as the prior art, and the known technology as those skilled in the art, does not explain at this.
As an embodiment, the material of described the second bottom electrode 210 is tungsten.Described the second bottom electrode 210 forms bottom electrode with described the first bottom electrode 202.Described the second bottom electrode 210 provides phase change current for the phase change layer to follow-up formation, in order to reduce the required phase change current of phase change layer, need to improve the contact area of described the second bottom electrode 210 and described phase change layer, therefore the area of described the second bottom electrode 210 is unsuitable excessive, and described area is generally 1/10～2/3 of phase change layer area.
The material of described second medium layer 204 is insulation material.Particularly, the material of described second medium layer 204 can be silica, carborundum, carborundum or silicon oxynitride.As one embodiment of the present of invention, the material of described second medium layer 204 is selected the material identical with described first medium layer 201, and the material of described second medium layer 204 is silicon nitride.The thickness range of described second medium layer 204 is 500～8000 dusts, and for example the thickness of described second medium layer 204 can be 500 dusts, 3000 dusts, 5000 dusts or 8000 dusts.The manufacture method of described second medium layer 204 can be chemical vapor deposition method.
Then, please refer to Fig. 8, on described second medium layer 204 surface, form the 3rd dielectric layer 207.The thickness range of described the 3rd dielectric layer 207 is 300～8000 dusts, for example, be 300 dusts, 1000 dusts, 5000 dusts or 8000 dusts.The material of described the 3rd dielectric layer 207 is insulation material.Particularly, the material of described the 3rd dielectric layer 207 can be silica, silicon nitride, carborundum or silicon oxynitride.In the present embodiment, the material of described the 3rd dielectric layer 207 is silicon nitride, and it can utilize chemical vapor deposition method to make.
Described the 3rd dielectric layer 207 forms interlayer dielectric layer with second medium layer 204, the first medium layer 201 of below.
Then,, please continue to refer to Fig. 8, at described the 3rd dielectric layer 207 and the interior formation groove of second medium layer 204, described groove exposes the conductive plunger 203 of below.Then, at described trenched side-wall, form the 3rd contact metal layer 212, the material of described the 3rd contact metal layer 212 is titanium/titanium nitride or tantalum/tantalum nitride; Then, make interconnection line 206 in described opening, described interconnection line 206 flushes with described the 3rd dielectric layer 207.Described the 3rd contact metal layer 212 is for increasing the adhesiveness between described interconnection line 206 and described interlayer dielectric layer.
Described interconnection line 206 is electrically connected to described conductive plunger 203, and both form interconnection structure.Described interconnection structure is for being electrically connected between the transistor in Semiconductor substrate 200 and described transistor AND gate external circuit is electrically connected to.
Then; please continue to refer to Fig. 8; on described the 3rd dielectric layer 207 surfaces, form protective layer 213; described protective layer 213; described protective layer is for the protection of described interconnection structure; prevent surface stored charge in follow-up plasma etch process of the interconnection line 206 of described interconnection structure, prevent because electric discharge between described interconnection structure and bottom electrode 202 causes damage to the device in described Semiconductor substrate 200.
The thickness range of described protective layer 213 is 30～500 dusts.The material of described protective layer 213 is silica, silicon nitride, silicon oxynitride, carborundum, tantalum oxide, aluminium oxide, hafnium oxide, zirconia or tungsten oxide.The manufacture method of described protective layer 213 is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.
Then, please refer to Fig. 9, at described protective layer 213 and the interior formation opening of the 3rd dielectric layer 207, described opening exposes the second bottom electrode 205 and second contact metal layer 210 of below.The formation method of described opening is etching technics, and described etching technics can be plasma etch process or wet-etching technology.
As an embodiment, described etching technics is wet-etching technology, and the solution that described wet-etching technology utilization contains hydrofluoric acid carries out.As another embodiment, described etching technics is plasma etch process, the ion of described plasma etch process utilization be contain fluorine ion plasma as etching ion.
Described opening is for sediment phase change layer, before carrying out phase change layer deposition step, the sidewall of described opening and bottom will be exposed in clean room, therefore described opening can be subject to the pollutant effects from clean room, described pollutant comprises steam, organic substance, inorganic matter and particle etc., this pollutant is assembled in sidewall and the bottom of described opening, form pollutant film, this pollutant film can affect the adhesiveness between phase change layer and described interlayer dielectric layer, and described the second bottom electrode 205 is exposed in clean room, can be subject to oxidation, on described the second bottom electrode 205 surfaces, form natural oxide film, this natural oxide film not only affects the adhesiveness between described the second bottom electrode 205 and described phase change layer, and can affect the reliability being electrically connected between described the second bottom electrode 205 and described phase change layer.Therefore before carrying out phase change layer depositing operation, need to carry out clean step to the sidewall of described opening and bottom, to remove described pollutant film and natural oxide film.
Inventor considers, utilizes etching technics can remove described pollutant film and natural oxide film, and described etching technics can be plasma etching or wet-etching technology.Because plasma etch process has, technology stability is good, the etching selection ratio advantages of higher of etch rate soon, to described natural oxide film and interlayer dielectric layer, pollutant film and interlayer dielectric layer, therefore, as the preferred embodiments of the present invention, utilize plasma etch process to clean the sidewall of described opening and bottom.
The ion of ion, nitrogen containing plasma or inert gas and mixing of nitrogen containing plasma that the etching ion that plasma etch process of the present invention adopts is inert gas.Wherein, the ion of described inert gas is one or both in argon ion, helium ion; Described nitrogen containing plasma is one or both in nitrogen ion, ammonium ion.
As preferred embodiment, the ion that described plasma etching can utilize inert gas mixes as etching ion with nitrogenous ion, and the ion of described inert gas can be nitrogen ion for argon ion, described nitrogenous ion.The ion of described inert gas can be at the pollutant film of removing opening sidewalls and bottom, thereby is conducive to improve the adhesiveness of phase change layer and described second bottom electrode 205 of follow-up formation; Tantalum layer or the titanium layer of described the second contact metal layer 210 that described nitrogen containing plasma can expose with described opening are combined, form tantalum nitride layer or titanium nitride layer, thereby the character that can prevent described tantalum layer or titanium layer is comparatively active, react with the phase change layer of follow-up formation, and cause consuming described phase change layer.
As an embodiment, the power bracket of described plasma etching is 100～1000W.
Owing to can producing electronics in described plasma etch process process, this electronics will be gathered in the surface of described the second bottom electrode 205, insulating effect due to described protective layer 213, the interconnection line of described interconnection structure 206 is insulated, thereby prevent described interconnection line 206 surface accumulation electronics, therefore, prevented the charge generation charge differences on described interconnection line 206 surfaces and described the second bottom electrode 205 surfaces, thereby eliminated described the second bottom electrode 205 causing due to this charge differences, Semiconductor substrate 200, between interconnection structure, form discharge channel, electric discharge phenomena have been eliminated, thereby protected the transistor that is positioned at Semiconductor substrate 200, improved the yield of phase transition storage.
Then, please refer to Figure 11, in described opening, form phase change layers 208 with protective layer 213 surfaces, described phase change layer 208 is filled full described opening.The manufacture method of described phase change layer 208 is same as the prior art, and the known technology as those skilled in the art, does not explain at this.
The material of described phase change layer 208 is chalcogenide alloy.Described chalcogenide alloy is Si-Sb-Te, Ge-Sb-Te, Ag-In-Te or Ge-Bi-Te.
Then, please continue to refer to Figure 11, remove and be positioned at the protective layer 213 on described the 3rd dielectric layer 207 surfaces and the unnecessary phase change layer 208 beyond described opening.As an embodiment, the method that the removal method of described protective layer 213 and phase change layer 208 is cmp.As another embodiment, the place to go method of described protective layer 213 and phase change layer 208 can also be plasma etch process or wet-etching technology.
To sum up, the manufacture method of phase transition storage provided by the invention, first in Semiconductor substrate, form interlayer dielectric layer, in described interlayer dielectric layer, be formed with interconnection structure and bottom electrode, described bottom electrode top is coated with the described interlayer dielectric layer of part, then on described interlayer dielectric layer, form protective layer, then in described protective layer and interlayer dielectric layer, form opening, then, described opening is carried out to clean plasma etch step, because described interlayer dielectric layer surface has protective layer, described protective layer can prevent that the accumulation that produces in described plasma etch process is on the surface of described interconnection structure, thereby avoided electric discharge (arcing) phenomenon between described bottom electrode and described opening, thereby protected the transistor that is positioned at Semiconductor substrate, make described transistor avoid receiving the impact of described discharging current, improved the yield of phase transition storage, and described cleaning is by the pollutant removal of the sidewall of described opening and bottom, improved the adhesiveness between phase change layer and described interlayer dielectric layer and bottom electrode.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (8)
1. a manufacture method for phase transition storage, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, be formed with interlayer dielectric layer, in described interlayer dielectric layer, be formed with interconnection structure and bottom electrode, described interconnection structure flushes with described interlayer dielectric layer, described bottom electrode top is coated with the described interlayer dielectric layer of part, and is also formed with contact metal layer between described bottom electrode and interlayer dielectric layer and between interconnection structure and interlayer dielectric layer;
Above described interlayer dielectric layer, form protective layer;
In described protective layer and interlayer dielectric layer, form the opening that exposes described bottom electrode;
Utilize plasma etch process, the bottom electrode of the sidewall of described opening and bottom is carried out to cleaning;
After above-mentioned cleaning completes, the bottom electrode surface deposition in described opening forms phase change layer;
Remove the protective layer on described interlayer dielectric layer surface.
2. phase transition storage manufacture method as claimed in claim 1, is characterized in that, the thickness range of described protective layer is 30～500 dusts.
3. the manufacture method of phase transition storage as claimed in claim 1, is characterized in that, the material of described protective layer is silica, silicon nitride, silicon oxynitride, carborundum, tantalum oxide, aluminium oxide, hafnium oxide, zirconia or tungsten oxide.
4. the manufacture method of phase transition storage as claimed in claim 1, is characterized in that, the manufacture method of described protective layer is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.
5. the manufacture method of phase transition storage as claimed in claim 1, is characterized in that, the ion of ion, nitrogen containing plasma or inert gas and mixing of nitrogen containing plasma that the ion that described plasma etch process adopts is inert gas.
6. the manufacture method of phase transition storage as claimed in claim 5, is characterized in that, the ion of described inert gas is one or both in argon ion, helium ion; Described nitrogen containing plasma is one or both in nitrogen ion, ammonium ion.
7. the manufacture method of the phase transition storage as described in arbitrary claim in claim 1,5,6, is characterized in that, the power bracket of described plasma etching is 100～1000W.
8. the manufacture method of phase transition storage as claimed in claim 1, is characterized in that, the material of described interlayer dielectric layer is silica, silicon nitride, carborundum or silicon oxynitride.
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| EP1710840A2 (en) * | 2005-04-06 | 2006-10-11 | Samsung Electronics Co., Ltd. | Multi-bit memory device having resistive material layers as storage node and methods of manufacturing and operating the same |
| CN101145598A (en) * | 2007-08-30 | 2008-03-19 | 复旦大学 | Method for improving CuxO electric resistance memory fatigue property |
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| EP1710840A2 (en) * | 2005-04-06 | 2006-10-11 | Samsung Electronics Co., Ltd. | Multi-bit memory device having resistive material layers as storage node and methods of manufacturing and operating the same |
| CN101145598A (en) * | 2007-08-30 | 2008-03-19 | 复旦大学 | Method for improving CuxO electric resistance memory fatigue property |
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