CN102468434A - Manufacturing method of phase change memory - Google Patents
Manufacturing method of phase change memory Download PDFInfo
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- CN102468434A CN102468434A CN2010105486107A CN201010548610A CN102468434A CN 102468434 A CN102468434 A CN 102468434A CN 2010105486107 A CN2010105486107 A CN 2010105486107A CN 201010548610 A CN201010548610 A CN 201010548610A CN 102468434 A CN102468434 A CN 102468434A
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Abstract
The invention provides a manufacturing method of a phase change memory. The method comprises the following steps of: providing a semiconductor substrate; forming an interlayer medium layer and a polycrystalline silicon layer which is flush with the interlayer medium layer on the semiconductor substrate, wherein the interlayer medium layer surrounds the polycrystalline silicon layer; partially etching the polycrystalline silicon layer, and forming a groove above the remaining polycrystalline silicon layer; forming a sticky metal layer at the bottom of the groove, wherein the sticky metal layer is made of a metal silicide; and forming a phase change layer above a contact metal layer, wherein the groove is filled with the phase change layer. According to the invention, the manufacturing yield of the phase change memory is increased.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the manufacture method of phase transition storage.
Background technology
(Phase Change Random Access Memory, PCRAM) technology is based on S.R.Ovshinsky and proposes in late 1960s that conception that phase-change thin film can be applied to the phase change memory medium sets up phase transition storage.As a kind of emerging nonvolatile storage technologies; Phase transition storage all has bigger superiority to flash memory in read or write speed, read-write number of times, data hold time, cellar area, many-valued realization etc. aspect many, has become the focus of present non-volatile memory technologies research.
In phase transition storage, can change the value of memory through the phase change layer that has write down data is heat-treated.The phase-change material that constitutes phase change layer can get into crystalline state or noncrystalline state owing to the heats of applying electric current.When phase change layer was in crystalline state, the resistance of PCRAM was lower, and this moment, the memory assignment was " 0 ".When phase change layer was in noncrystalline state, the resistance of PCRAM was higher, and this moment, the memory assignment was " 1 ".Therefore, PCRAM utilizes resistance difference when phase change layer is in crystalline state or noncrystalline state to write/nonvolatile memory of reading of data.
The manufacture method of existing phase transition storage please refer to Fig. 1～Fig. 3, and said method comprises:
At first, please refer to Fig. 1, Semiconductor substrate 100 is provided, on said Semiconductor substrate 100, form interlayer dielectric layer 102, be formed with opening in the said interlayer dielectric layer 102, said opening exposes the Semiconductor substrate 100 of below.
Then, still with reference to figure 1, carry out chemical vapor deposition method, in said opening, fill polysilicon layer 101, said polysilicon layer 101 flushes with said interlayer dielectric layer 102.
Then, please refer to Fig. 2, along the said polysilicon layer 101 of thickness direction etching of said polysilicon layer 101, on remaining polysilicon layer 101, form groove 103, said remaining polysilicon layer 101 is exposed in said groove 103 bottoms.
Then, please refer to Fig. 3, in said groove 103, form phase change layer 106.Said phase change layer 106 is filled full said groove 103.
, publication number can find more information in being the one Chinese patent application of CN101728492A about existing phase transition storage.
Find that in reality the yield of the phase transition storage of the making of prior art is low, the reliability of work is low.
Summary of the invention
The problem that the present invention solves has provided a kind of manufacture method of phase transition storage, and said method has improved the yield of the phase transition storage of making.
For addressing the above problem, the invention provides a kind of manufacture method of phase transition storage, said method comprises:
Semiconductor substrate is provided;
The polysilicon layer that on said Semiconductor substrate, forms interlayer dielectric layer and flush with said interlayer dielectric layer, said interlayer dielectric layer is around said polysilicon layer;
The said polysilicon layer of partial etching forms groove above remaining polysilicon layer;
Form the adhesiving metal layer at said channel bottom, the material of said adhesiving metal layer is a metal silicide;
Above said contact metal layer, form phase change layer, said phase change layer is filled full said groove.
Alternatively, said adhesiving metal layer manufacturing method thereof comprises:
In said inter-level dielectric laminar surface and groove, form metal level, said metal level covers the sidewall and the bottom of said groove;
Said metal level is annealed, make said metal level combine with the polysilicon of channel bottom, form metal silicide at said channel bottom, said metal silicide is as said adhesiving metal layer;
Remove the said metal level of said inter-level dielectric laminar surface and trenched side-wall.
Alternatively, said metal level is titanium or cobalt, and said adhesiving metal layer is titanium-silicon compound or cobalt and silicon compound.
Alternatively, the said rapid thermal annealing that is annealed into, the temperature range of said rapid thermal annealing is 300～600 degrees centigrade.
Alternatively, said annealing utilizes nitrogen to carry out.
Alternatively, the manufacture method of said adhesiving metal layer comprises:
In said inter-level dielectric laminar surface and groove, form the adhesiving metal layer, said adhesiving metal layer covers the sidewall and the bottom of said groove;
Removal is positioned at the adhesiving metal layer of said inter-level dielectric laminar surface and trenched side-wall, keeps the adhesiving metal layer that is positioned at channel bottom.
Alternatively, said adhesiving metal layer is titanium-silicon compound or cobalt and silicon compound.
Alternatively, the thickness range of said adhesiving metal layer is 30～500 dusts.
Alternatively, the degree of depth of said groove is 400～1400 dusts.
Alternatively, the manufacture method of said interlayer dielectric layer and polysilicon layer comprises:
On said Semiconductor substrate, form polysilicon layer;
The said polysilicon layer of etching forms opening in said polysilicon layer, said split ring is around said polysilicon layer;
Deposition insulation material forms said interlayer dielectric layer in said opening;
The said interlayer dielectric layer of planarization makes said interlayer dielectric layer flush with said polysilicon layer.
Alternatively, said polysilicon layer utilizes chemical vapor deposition method or epitaxial deposition process to make.
Alternatively, the thickness range of said polysilicon layer is 550～8000 dusts.
Alternatively, said insulation material is silica, carborundum, carborundum or silicon oxynitride.
Alternatively, said insulation material utilizes the high density plasma CVD method to make.
Compared with prior art, the present invention has the following advantages:
The polysilicon layer of the present invention through on Semiconductor substrate, forming interlayer dielectric layer and flush with said interlayer dielectric layer forms groove then on said polysilicon layer, form the adhesiving metal layer at said channel bottom, on said adhesiving metal layer, forms phase change layer.Owing to increased the adhesiving metal layer between said phase change layer and the polysilicon layer; The adhesiving metal layer is a metal silicide; Thereby improved the adhesiveness between phase change layer and the polysilicon layer; Thereby the problem of having avoided phase change layer to peel off from said polysilicon layer has improved the yield of phase transition storage, makes follow-up technology to carry out smoothly;
Further optimally, the manufacture method of said interlayer dielectric layer and polysilicon layer comprises: on Semiconductor substrate, form polysilicon layer, in said polysilicon layer, form the opening around said polysilicon layer; Deposition insulation material forms said interlayer dielectric layer in said opening, the present invention elder generation manufacturing polycrystalline silicon layer; Make interlayer dielectric layer again; With the interlayer dielectric layer of making earlier of prior art, the method for back manufacturing polycrystalline silicon layer is compared, and the polysilicon layer inside of formation does not have the cavity; Improve the quality of the polysilicon layer that forms, improved the performance of device.
Description of drawings
Fig. 1～Fig. 3 is the manufacture method cross-sectional view of the phase transition storage of prior art;
The manufacture method schematic flow sheet of Fig. 4 phase transition storage of the present invention;
Fig. 5～Figure 11 is the manufacture method cross-sectional view of the phase transition storage of one embodiment of the invention.
Embodiment
The yield of existing phase transition storage is low.Discover through the inventor; In existing phase transition storage manufacturing process, phase change layer comes off (peeling) from polysilicon layer, makes phase transition storage to work; Thereby influenced the yield of phase transition storage, and made follow-up processing step to carry out.Because the material of phase change layer is different with the material of polysilicon layer, adhesiveness between the two is relatively poor, thereby makes phase change layer come off from polysilicon layer easily.
And prior art is at first made interlayer dielectric layer usually, and then the manufacturing polycrystalline silicon layer, and promptly prior art forms opening in interlayer dielectric layer, carries out chemical vapor deposition method then, in said opening, fills polysilicon layer.In carrying out said chemical vapor deposition method process, be positioned at the sidewall of opening and the polysilicon layer of bottom and form the cavity easily, influenced the quality of conformal polysilicon layer, influenced the performance of device.
In order to address the above problem, the inventor has proposed a kind of manufacture method of phase transition storage, please combine the manufacture method schematic flow sheet of the phase transition storage of the present invention shown in the accompanying drawing 4.Said method comprises:
Step S1 provides Semiconductor substrate;
Step S2, the polysilicon layer that on said Semiconductor substrate, forms interlayer dielectric layer and flush with said interlayer dielectric layer, said interlayer dielectric layer is around said polysilicon layer;
Step S3, the said polysilicon layer of partial etching forms groove above remaining polysilicon layer;
Step S4 forms the adhesiving metal layer at said channel bottom, and the material of said adhesiving metal layer is a metal silicide;
Step S5 forms phase change layer above said contact metal layer, said phase change layer is filled full said groove.
Below in conjunction with concrete embodiment technical scheme of the present invention is at length explained.
For technical scheme of the present invention is described better, please refer to the manufacture method cross-sectional view of phase transition storage of the one embodiment of the invention of Fig. 5～shown in Figure 11.
At first, please refer to Fig. 5, Semiconductor substrate 200 is provided.Be formed with the transistor (not shown) in the said Semiconductor substrate 200, said transistor is used for the polysilicon layer through follow-up formation, drives the phase change layer of follow-up formation.Said transistorized structure is identical with prior art with manufacture method, as those skilled in the art's known technology, does not do explanation at length at this.
In the present embodiment, the material of said Semiconductor substrate 200 is a silicon, and in other embodiment, the material of said Semiconductor substrate 200 can also be germanium silicon.
Then, continue with reference to figure 5, on said Semiconductor substrate 200, form polysilicon layer 201, said polysilicon layer 201 can utilize chemical vapor deposition method or epitaxial deposition process to make.
Because polysilicon layer 201 of the present invention is prior to the interlayer dielectric layer of follow-up formation; When thereby said polysilicon layer 201 deposits; Having an even surface of Semiconductor substrate 200 do not exist opening or groove, thus when having avoided chemical vapor deposition method in the sidewall of groove or opening and the bad problem of spreadability of bottom; Thereby avoided in polysilicon layer 201, forming the problem in cavity, improved the quality of said polysilicon layer 201.
As an embodiment, the thickness range of said polysilicon layer 201 is 500～8000 dusts.
Then, please refer to Fig. 6, the said polysilicon layer 201 of etching forms opening in said polysilicon layer 201, and said split ring is around said polysilicon layer 201.Said opening is used to fill interlayer dielectric layer, with adjacent polysilicon layer 201 electrical insulation.
As an embodiment, the lithographic method of said polycrystal layer 201 comprises: form photoresist layer on said polysilicon layer 201 surfaces, defined the photoresist opening in the said photoresist layer, said photoresist opening exposes the polysilicon layer 201 that need carry out etching;
With said photoresist layer is mask, carries out etching technics along said photoresist opening, in said polysilicon layer 201, forms opening, and said opening exposes the Semiconductor substrate 200 of below, and said etching technics can be wet-etching technology;
Utilize plasma etch process or wet-etching technology, remove said photoresist layer.
Then, please refer to Fig. 7, deposition insulation material in said opening, said insulation material is surrounded said polysilicon layer 201, and said insulation material forms said interlayer dielectric layer 202.Said insulation material can be insulation materials such as silica, silicon nitride, silicon oxynitride, carborundum.As an embodiment, said insulation material is a silica.
As preferred embodiment; Said insulation material utilizes high density plasma CVD technology to be filled in the said opening; The insulation material-structure that utilizes said high density plasma CVD technology to form is fine and close, has the good insulation performance performance.
Mode through chemico-mechanical polishing is ground to interlayer dielectric layer with polysilicon and flushes then.
Then, please refer to Fig. 8, the said polysilicon layer 201 of partial etching, said etching is the thickness direction etching along said polysilicon layer 201, above remaining polysilicon layer 202, forms groove 203.Said remaining polysilicon layer 201 is exposed in the bottom of said groove 203.The method of said etching is the method for wet etching.
The degree of depth of said groove 203 should be provided with according to the thickness of the phase change layer that will form.As an embodiment, the depth bounds of said groove 203 is 400～1400 dusts.
Adhesiving metal layer and phase-change metal layer will be formed in follow-up processing step successively on the bottom of said groove 203.Adhesiving metal layer according to the invention is used to improve the adhesiveness between said phase change layer and the polysilicon layer 201, thereby prevents that phase change layer from peeling off from polysilicon layer 201.
The inventor finds, the material of adhesiving metal layer can influence the adhesiveness between 201 layers of phase change layer and the polysilicons.Particularly; The inventor tests; Utilize metallic aluminium, Titanium, metal tantalum, aluminium oxide, titanium oxide, tantalum oxide etc. as the adhesiving metal layer; But the adhering effect of improving between phase change layer and the polysilicon layer 201 is all undesirable, shows as phase change layer and still can peel off from polysilicon layer 201, and utilize titanium-silicon compound (Ti
xSi
y, x+y=1) or cobalt and silicon compound (Co
uSi
v, u+v=1) making adhesiving metal layer can obviously improve the adhesiveness between phase change layer and the polysilicon layer 201, shows as between phase change layer and the polysilicon layer 201 to adhere to well, has eliminated the problem that phase change layer is peeled off from polysilicon layer 201.
Therefore, in follow-up processing step, the present invention will form titanium-silicon compound or cobalt and silicon compound in the bottom of said groove 203.
Then, please refer to Fig. 9, in the surface of said interlayer dielectric layer 202 and groove 203, form metal level 204, said metal level 204 covers the sidewall and the bottom of said groove 203.
The thickness of said metal level 204 depends on the thickness of the adhesiving metal layer that will form, and as an embodiment, the thickness range of said metal level 204 is 30～500 dusts.
As an embodiment, the material of said metal level 204 is a titanium.Titanium can be under the situation of low temperature (300～600 degrees centigrade) heating; Combine with the silicon of polysilicon layer 201; Form titanium-silicon compound, the silica of Titanium and interlayer dielectric layer 202 (or silicon nitride, carborundum, silicon oxynitride) can not react, therefore; Said metal level 204 in follow-up processing step, carry out low-temperature heat the time; The metal level 204 that is positioned at the bottom of said groove 203 will react with polycrystal layer 201, form titanium-silicon compound, and said titanium-silicon compound is as the adhesiving metal layer; And the sidewall and the interlayer dielectric layer 202 surperficial silicon that are positioned at said groove 203 do not react, and still are Titanium.The inventor finds that Titanium and titanium-silicon compound have etching selection ratio when etching, and both etching selection ratio can not be damaged titanium-silicon compound, thereby can not influence adhesiving metal layer quality more than or equal to 8 when removing Titanium.
As another embodiment of the present invention, the material of said metal level 204 can also be cobalt.The similar performance of metallic cobalt and Titanium; Be that metallic cobalt is under the situation of low temperature (300～600 degrees centigrade) heating; Can combine with the silicon of polysilicon layer 201; Form cobalt and silicon compound, and the silica of metallic cobalt and interlayer dielectric layer 202 (or silicon nitride, carborundum, silicon oxynitride) can not react, still is metallic cobalt.Therefore, based on the principle similar with Titanium, utilize metal level 204 to form cobalt and silicon compound in the bottom of said groove 203, said cobalt and silicon compound is as the adhesiving metal layer.
Then, please continue with reference to figure 9, said metal level 204 is annealed, make said metal level 204 combine with the polysilicon of groove 203 bottoms, form metal silicide in said groove 203 bottoms, said metal silicide is as said adhesiving metal layer.And the metal level 204 that is positioned at groove 202 sidewalls and interlayer dielectric layer 202 surfaces does not react with the silica of interlayer dielectric layer 202 (or silicon nitride, carborundum, silicon oxynitride).
The said rapid thermal annealing that is annealed into.The temperature range of said annealing is 300～600 degrees centigrade, and for example the temperature of said annealing can be 300 degrees centigrade, 450 degrees centigrade or 600 degrees centigrade.
Said annealing utilizes nitrogen to carry out, and annealing helps Semiconductor substrate 200 surfaces and is heated evenly under the environment of nitrogen, thereby the polysilicon that helps said metal level 204 and groove 203 bottoms reacts, and forms the uniform adhesiving metal layer of thickness.
Then, please refer to Figure 10, carry out etching technics, remove the sidewall of said groove 203 and the metal level 204 (combination Fig. 9) on said interlayer dielectric layer 203 surfaces, keep the adhesiving metal layer 205 that is positioned at groove 203 bottoms.The thickness range of said adhesiving metal layer 205 is 30～500 dusts,
Said etching technics is a wet-etching technology.Because the metal level 204 on the sidewall of said groove 203 and said interlayer dielectric layer 203 surfaces does not react with interlayer dielectric layer 203 when annealing; And be positioned at groove 203 bottoms metal level 204 since when annealing with the polysilicon reaction of polysilicon layer 202, formation adhesiving metal layer 205.Under the situation of identical etching solution, said adhesiving metal layer 205 has etching selection ratio with metal level 204, and etching selection ratio is greater than 8.Therefore, carrying out wet-etching technology when removing said metal level 204, can not cause damage to said adhesiving metal layer 205.
As an embodiment, the solution of said wet etching is H
2O
2And ammoniacal liquor) mixed solution, the time range of said wet etching are 2～20min.
Need to prove that adhesiving metal layer 205 of the present invention can also utilize other method to make.As an embodiment, the manufacture method of said adhesiving metal layer can also for:
In said groove with on the interlayer dielectric layer, form the adhesiving metal layer, said adhesiving metal layer covers the sidewall and the bottom of said groove;
Removal is positioned at the adhesiving metal layer of said inter-level dielectric laminar surface and trenched side-wall, keeps the adhesiving metal layer that is positioned at channel bottom.
Wherein, the material of said adhesiving metal layer is titanium-silicon compound or cobalt and silicon compound, and said adhesiving metal layer can utilize physical vapour deposition (PVD) or chemical vapor deposition method to make.The thickness range of said adhesiving metal layer is 30～500 dusts.
Then, please refer to Figure 11, in said groove 203 (combination Figure 10), fill phase change layer 206.Said phase change layer 206 can utilize chemical vapor deposition method to make, and the material of said phase change layer 206 is a chalcogenide alloy, and said chalcogenide alloy can be Si-Sb-Te, Ge-Sb-Te, Ag-In-Te or Ge-Bi-Te.
To sum up; The manufacture method of phase transition storage provided by the invention forms the adhesiving metal layer between phase change layer and polysilicon layer, improved the adhesiveness between phase change layer and the polysilicon layer; Prevent the problem that phase change layer is peeled off from polysilicon layer, improved the yield of the phase transition storage of making.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (14)
1. the manufacture method of a phase transition storage is characterized in that, comprising:
Semiconductor substrate is provided;
The polysilicon layer that on said Semiconductor substrate, forms interlayer dielectric layer and flush with said interlayer dielectric layer, said interlayer dielectric layer is around said polysilicon layer;
The said polysilicon layer of partial etching forms groove above remaining polysilicon layer;
Form the adhesiving metal layer at said channel bottom, the material of said adhesiving metal layer is a metal silicide;
Above said contact metal layer, form phase change layer, said phase change layer is filled full said groove.
2. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, said adhesiving metal layer manufacturing method thereof comprises:
In said inter-level dielectric laminar surface and groove, form metal level, said metal level covers the sidewall and the bottom of said groove;
Said metal level is annealed, make said metal level combine with the polysilicon of channel bottom, form metal silicide at said channel bottom, said metal silicide is as said adhesiving metal layer; Remove the said metal level of said inter-level dielectric laminar surface and trenched side-wall.
3. the manufacture method of phase transition storage as claimed in claim 2 is characterized in that, said metal level is titanium or cobalt, and said adhesiving metal layer is titanium-silicon compound or cobalt and silicon compound.
4. the manufacture method of phase transition storage as claimed in claim 2 is characterized in that, the said rapid thermal annealing that is annealed into, and the temperature range of said rapid thermal annealing is 300～600 degrees centigrade.
5. the manufacture method of phase transition storage as claimed in claim 4 is characterized in that, said annealing utilizes nitrogen to carry out.
6. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, the manufacture method of said adhesiving metal layer comprises:
In said inter-level dielectric laminar surface and groove, form the adhesiving metal layer, said adhesiving metal layer covers the sidewall and the bottom of said groove;
Removal is positioned at the adhesiving metal layer of said inter-level dielectric laminar surface and trenched side-wall, keeps the adhesiving metal layer that is positioned at channel bottom.
7. the manufacture method of phase transition storage as claimed in claim 6 is characterized in that, said adhesiving metal layer is titanium-silicon compound or cobalt and silicon compound.
8. like the manufacture method of the described phase transition storage of arbitrary claim in the claim 1～7, it is characterized in that the thickness range of said adhesiving metal layer is 30～500 dusts.
9. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, the degree of depth of said groove is 400～1400 dusts.
10. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, the manufacture method of said interlayer dielectric layer and polysilicon layer comprises:
On said Semiconductor substrate, form polysilicon layer;
The said polysilicon layer of etching forms opening in said polysilicon layer, said split ring is around said polysilicon layer;
Deposition insulation material forms said interlayer dielectric layer in said opening;
The said interlayer dielectric layer of planarization makes said interlayer dielectric layer flush with said polysilicon layer.
11. the manufacture method of phase transition storage as claimed in claim 10 is characterized in that, said polysilicon layer utilizes chemical vapor deposition method or epitaxial deposition process to make.
12. the manufacture method of phase transition storage as claimed in claim 10 is characterized in that, the thickness range of said polysilicon layer is 550～8000 dusts.
13. the manufacture method of phase transition storage as claimed in claim 10 is characterized in that, said insulation material is silica, carborundum, carborundum or silicon oxynitride.
14. the manufacture method of phase transition storage as claimed in claim 10 is characterized in that, said insulation material utilizes the high density plasma CVD method to make.
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| US10840087B2 (en) | 2018-07-20 | 2020-11-17 | Lam Research Corporation | Remote plasma based deposition of boron nitride, boron carbide, and boron carbonitride films |
| US11848199B2 (en) | 2018-10-19 | 2023-12-19 | Lam Research Corporation | Doped or undoped silicon carbide deposition and remote hydrogen plasma exposure for gapfill |
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