CN107045883B - The method that RRAM circuit and RRAM row are formed - Google Patents

The method that RRAM circuit and RRAM row are formed Download PDF

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Publication number
CN107045883B
CN107045883B CN201611020974.1A CN201611020974A CN107045883B CN 107045883 B CN107045883 B CN 107045883B CN 201611020974 A CN201611020974 A CN 201611020974A CN 107045883 B CN107045883 B CN 107045883B
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rram
bit lines
current
transistor
formation
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CN107045883A (en
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李嘉富
池育德
林弘璋
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0088—Write with the simultaneous writing of a plurality of cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Abstract

Embodiment of the disclosure is related to a kind of RRAM circuit with and related methods, which includes the current limiting element for being configured as improving the formation time of RRAM unit.In some embodiments, RRAM circuit is with wherein with the RRAM array of multiple RRAM devices.Bit line decoder is configured as forming signal to applying simultaneously with two or more more bit lines connecting in multiple RRAM devices in the row of RRAM array.Current limiting element is configured as during the formation operation of the conductive filament formed in RRAM device simultaneously by the current limit on more bit lines below formation value.By limiting the electric current on bit line during formation operation, signal can will be formed simultaneously and be applied to multiple RRAM devices, while keep relatively low total power consumption, to allow quick execution formation operation.

Description

The method that RRAM circuit and RRAM row are formed
Cross reference to related applications
This application claims 62/255, No. 733 priority of the U.S. Provisional Application No. submitted on November 16th, 2015, Full content is hereby expressly incorporated by reference.
Technical field
The embodiment of the present invention relates in general to semiconductor field, more particularly, to resistive random access memory (RRAM) circuit and its related forming method.
Background technique
Many modern electronic devices include the electronic memory for being configured as storing data.Electronic memory can be volatile Property memory or nonvolatile memory.Volatile memory storing data when it is powered, and nonvolatile memory energy Enough storing datas during power down.Resistive random access memory (RRAM) is one of next-generation non-volatile memory technologies Promising candidate.RRAM structure is simple, it is small to occupy cellar area, switching voltage is low, switching time is short and with CMOS system Make process compatible.
Summary of the invention
According to an aspect of the invention, there is provided a kind of resistive random access memory (RRAM) circuit, comprising: more A RRAM unit, wherein each RRAM unit respectively includes RRAM device；Bit line decoder, be configured as to it is the multiple More bit lines of two or more connections in RRAM unit apply simultaneously forms signal；And current limiting element, matched It is set to during the formation operation of the initial conduction filament formed in the RRAM device, the electric current on the more bit lines is same When be limited to less than to form value.
According to another aspect of the present invention, a kind of resistive random access memory (RRAM) circuit is provided, comprising: more A RRAM unit, wherein the first electrode that each RRAM unit respectively includes being connected to bit line is connected with by access transistor To the second electrode of source electrode line；Bit line decoder is configured as during formation operation that signal will be formed while being applied to and institute State more bit lines of two or more connections in multiple RRAM units；And current limiting element, being configured as will be described The current value of electric current on more bit lines is limited to smaller than during write operation during the formation operation.
According to another aspect of the invention, the method that a kind of pair of RRAM circuit executes formation operation is provided, comprising: activation It is operably coupled to the wordline of the RRAM cell row in RRAM array；To the multiple RRAM being connected in the RRAM cell row More bit lines of unit apply form signal simultaneously, to execute the shape for forming initial conduction filament in the multiple RRAM unit At operation；And the electric current on the more bit lines is limited in lower than formation value simultaneously during formation operation.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, various aspects of the invention are best understood from described in detail below.It should Note that according to the standard practices in industry, various components are not drawn on scale.In fact, in order to clearly discuss, various assemblies Size can be arbitrarily increased or decreased.
Fig. 1 is shown including being configured as improving the resistive random access memory for the current limiting element for forming the time (RRAM) some embodiments of the block diagram of circuit.
Fig. 2 shows some additional embodiments of the block diagram of RRAM circuit, RRAM circuit includes being configured as improving being formed The current limiting element of time.
Fig. 3 shows some additional embodiments of the block diagram of RRAM circuit, and RRAM circuit includes being configured as improving being formed The current limiting element of time.
Fig. 4 A to 4B shows the cross section of RRAM unit and some embodiments of schematic diagram.
Fig. 5 shows some additional embodiments of the block diagram of RRAM circuit, and RRAM circuit includes being configured as improving being formed The current limiting element of time.
Fig. 6 A to 6B shows some implementations of the method for RRAM circuit of the operation with disclosed current limiting element The block diagram and timing diagram of example.
Fig. 7 shows the flow chart that some embodiments of method of formation operation are executed to RRAM circuit.
Specific embodiment
Following disclosure provides the different embodiments or example of many different characteristics for realizing provided theme. The specific example of component and arrangement is described below to simplify the present invention.Certainly, these are only example, are not intended to limit this Invention.For example, in the following description, above the second component or upper formation first assembly may include first assembly and second The embodiment that component is formed in a manner of directly contacting, and also may include can be with shape between first assembly and the second component At additional component, so that the embodiment that first assembly and the second component can be not directly contacted with.In addition, the present invention can be Repeat reference numerals and/or character in each example.The repetition is that for purposes of simplicity and clarity, and itself is not indicated The relationship between each embodiment and/or configuration discussed.
Moreover, for ease of description, can be used herein such as " in ... lower section ", " ... below ", "lower", " ... it On ", the spatially relative terms such as "upper" with describe an element or component and another (or other) element as shown in the figure or The relationship of component.Other than orientation shown in figure, spatially relative term is intended to include the difference of device in use or operation Orientation.Device can otherwise orient (be rotated by 90 ° or in other directions), and space as used herein is opposite retouches Corresponding explanation can similarly be made by stating symbol.
Resistive random access memory (RRAM) device is typically included in setting in back-end process (BEOL) metallization heap The high-k dielectric material layer arranged between conductive electrode in overlapping piece.RRAM device be configured as based between resistance states can The process of inverse switching carrys out work.It is realized by being formed selectively the conductive filament across high-k dielectric material layer this reversible Switching.For example, being usually that the high-k dielectric material layer to insulate can be extended through by applying voltage at conductive electrode both ends with being formed The conductive filament of excessively high k dielectric material layer and it is conductive.RRAM unit with first (for example, high) resistance states corresponds to first Data value (for example, logic ' 0 ') and with second (for example, low) resistance states RRAM unit correspond to the second data value (example Such as, logic ' 1 ').
Before RRAM device can be used for storing data, technique is initially formed to the RRAM unit execution in RRAM array. It is initially formed technique and forms conductive filament in high-k dielectric material layer.Because being initially formed operation to the execution of entire RRAM array, So may be time-consuming process if being applied to RRAM unit one by one by will form voltage/current completes this operation. Alternatively, if executing formation operation to the RRAM unit in the multiple row of RRAM array simultaneously, can high-current consumption, due to integrated Limitation in circuit, high current may not be able to provide multiple column simultaneously.It may for example, providing big formation electric current to multiple column Need to consume the big transmission gate transistor of the large space in integrated chip, and it is non-equal between each RRAM unit and/or each bit line Even property may cause lesser formation electric current and cannot provide each RRAM unit enough electric currents to be effectively formed conduction Filament.
This disclosure relates to which a kind of resistive random access memory (RRAM) circuit is with and related methods.The circuit includes It is configured as improving the current limiting element of the formation time of RRAM array by the electric current on more bit lines of limitation, to permit Perhaps formation operation occurs in the RRAM device for being connected to the more bit lines simultaneously.In some embodiments, RRAM circuit packet Include the RRAM array with multiple RRAM devices.Bit line decoder be configured as to multiple RRAM in a line of RRAM array More bit lines of two or more connections in device apply simultaneously forms signal.Current limiting element is configured as being formed During the formation operation of conductive filament in RRAM device simultaneously by more bit lines formation signal current limit be lower than Formation value.By limiting the electric current on bit line during formation operation, signal can will be formed simultaneously and be applied to multiple RRAM devices Part, while relatively low total current drain is kept, to allow to execute formation operation quickly and with good consistency.
Fig. 1 is shown including being configured as improving the resistive random access memory for the current limiting element for forming the time (RRAM) some embodiments of the block diagram of circuit 100.
RRAM circuit 100 includes the multiple RRAM units 104 being arranged in integrated chip1,1To 104M, n.Multiple RRAM are mono- Member 1041,1To 104M, nRespectively include the RRAM device with changeable resistance states.RRAM unit 1041,1To 104M, nIt is arranged in Including in row and/or the RRAM array 102 arranged.RRAM unit in a line of RRAM array 102 is (for example, 1041,1To 1041,n) It is operably coupled to wordline WL1To WLmIn one, and the one of RRAM array 102 column in RRAM unit (for example, 1041,1 To 104M, 1) it is operably coupled to bit line BL1To BLnIn one.For example, RRAM unit 1041,1It is connected to bit line BL1And word Line WL1, and RRAM unit 1042,3It is connected to bit line BL3With wordline WL2.This makes multiple RRAM units 1041,1To 104M, nRespectively It is associated with address defined in the crosspoint as wordline and bit line.In some embodiments, each address RRAM can chain It is connected to the data input/output pin of the distribution in the integrated chip including RRAM circuit 100.
RRAM array 102 is connected to support circuits, and support circuits are configured to from multiple RRAM units 1041,1To 104M, n Read data and/or to multiple RRAM units 1041,1To 104M, nElectronic data is written.In some embodiments, support circuits packet Include bit line decoder 106 and wordline decoder 108.Bit line decoder 106 is configured as based on the address S receivedADDRSelection Property by signal (for example, electric current and/or voltage) be applied to more bit line BL1 to BLn one or more.Wordline decoder 108 are configured as based on the address S receivedADDRSelectively one or more application letter of Xiang Duogen wordline WL1 into WLm Number (for example, electric current and/or voltage).
The bit line BL of RRAM array 1021To BLnIt is also operable to be connected to sensing circuit 110 and current limiting element 112. Sensing circuit 110 is configured as sensing multiple RRAM units 1041,1To 104M, nSelected one data mode.For example, being From RRAM unit 1041,1Data, wordline decoder 104 and bit line decoder 106 are read by signal (for example, voltage) selectivity Ground is applied to RRAM unit 1041,1, this, which receives sensing circuit 110, has depending on RRAM unit 1041,1Data mode Value signal (for example, voltage).Sensing circuit 110 is configured as sensing this signal and determines that RRAM is mono- based on the signal Member 1041,1Data mode (for example, by the way that voltage to be compared with reference voltage).
Current limiting element 112 was configured as in formation operation (that is, being initially formed conductive filament in the RRAM device) phase Between selectively limit more bit line BL1To BLnIn more (for example, all) bit lines on electric current.In some embodiments, Current limiting element 112 can pass through more bit line BL1To BLnIt is connected to multiple RRAM units 1041,1To 104m,n.In other realities It applies in example, current limiting element 112 can be connected to multiple RRAM units 104 by source electrode line (as shown in Figure 3)1,1Extremely 104M, n。
In some embodiments, current limiting element 112 can be by more bit line BL1To BLnOn current limit be lower than shape At value (for example, predetermined value small than the electric current used during write operation (set or resetting operation)).In some implementations In example, current limiting element 112 can be configured as limits more bit line BL during formation operation1To BLnOn electric current, and More bit line BL during being not limited in read operation or write operation1To BLnOn electric current.By using current limiting element 112 Come the electric current during being limited in formation operation on bit line, signal can will be formed simultaneously and be applied to more bit line BL1To BLn(example Such as, all RRAM units 104 in the line are applied to1,1To 104m,n), while consuming relatively low total current.This allows fast Speed and accurately execute formation operation.
Fig. 2 shows some additional embodiments of the block diagram of RRAM circuit 200, RRAM circuit includes being configured as improving shape At the current limiting element of time.
RRAM circuit 200 includes being operably coupled to more bit line BL1To BLnCurrent limiting element 202.Some In embodiment, current limiting element 202 includes multiple current limit component 204a to 204n, and each current limit component connects respectively It is connected to more bit line BL1To BLnIn one.Current limit component 204a to 204n is configured as will be in more bit line BL1Extremely BLnIn corresponding one on current limit be lower than formation value.In some embodiments.Formation value can have in about 1 μ Value between A to about 5 μ A.In other embodiments, formation value can have other values.
Sensing circuit 206 is configured to determine that the RRAM unit 104 in RRAM array 1021,1To 104M, nInterior data shape State.In some embodiments, sensing circuit 206 is separated by current limiting element with RRAM array 102.In other embodiments In, sensing circuit 206 can be separated by bit line decoder 106 with RRAM array 102.In some embodiments, sensing circuit 206 may include data selector 208 and sensing amplifier 210.During read operation, data selector 208 is configured as From more bit line BL1To BLnIn one or more receive and signal and selectively provide signals to sensing amplifier 210.Sense Amplifier 210 is configured as received signal and reference voltage VrefCompare to generate and be stored in selected RRAM The corresponding output data state D of data mode in unitout(for example, " 1 " or " 0 ").
In some embodiments, control unit 212 is connected to current limiting element 202.Control unit 212 is configured as defeated Signal S is controlled outCTRL, selectively operation electric current limits component 204a to 204n to limit to the control signal during formation operation Make more bit line BL1To BLnInterior electric current.In some embodiments, current limit component 204a to 204n is configured as receiving phase Same control signal SCTRL, so that current limit component 204a to 204n limits more bit line BL simultaneously during formation operation1Extremely BLnAbove (for example, in all more bit line BL1To BLnOn) electric current.In some embodiments, control unit 212 is configured to Operation electric current limits component 204a to 204n not limit more positions to during the reading of RRAM array 102 and/or write operation Electric current on line BL1 to BLn.For example, in various embodiments, current limiting element 202 can be in read operation and/or write-in It disconnects and/or is turned off with more bit line BL1 to BLn during operation.
In various embodiments, current limit component 204a to 204n may include being configured as selectively limiting more positions Any kind of device of electric current on line BL1 to BLn.For example, in some embodiments, current limit component 204a to 204n It may include variable resistance.In such embodiments, the resistance of variable resistance limits on more bit line BL1 to BLn Electric current (because according to Ohm's law, voltage is equal to electric current multiplied by resistance).In other embodiments, current limit component 204a is extremely 204n may include transistor.
Fig. 3 shows some additional embodiments of the block diagram of RRAM circuit 300, and RRAM circuit includes being configured as improving shape At the current limiting element of time.
RRAM circuit 300 includes the multiple RRAM units 304 being arranged in RRAM array 302.Multiple RRAM units 304 divide It Bao Kuo not RRAM device 306 and access transistor 308.RRAM device 306, which has, is connected to bit line BL1To BLnFirst electrode The second electrode 306b of 306a and the source terminal for being connected to access transistor 308.Access transistor 308, which has, is connected to wordline The gate terminal of WL1 to WLn, so that bit line BL1To BLnWith wordline WL1To WLnIt is configured to combine and is provided to RRAM unit 304 Access.Access transistor 308 further includes being connected to more root polar curve SL1To SLnIn one drain electrode end.
More root polar curve SL1To SLnIt is additionally coupled to current limiting element 310.In some embodiments, current limiting element 310 include being configured as generating reference current IrefCurrent source 312.Current source 312, which is connected to, is configured as control reference current IrefValue control unit 212.Reference current IrefThe source electrode to the transistor 314 of diode connection is provided from current source 312 End.The transistor 314 of diode connection further includes the drain electrode end for being connected to ground terminal and the gate terminal for being connected to source terminal.With reference to Electric current IrefAlso it provides from current source 312 to multiple current limit components in current limiting element 310.In some embodiments, Multiple current limit components include transistor device 316.
During operation, control unit 212 is configured as operation electric current source 312 to export reference current Iref.Diode connects The transistor 314 of method is configured as reference current IrefBe converted to the bias voltage at node 315.Due to transistor device The conductance at 316 channel both ends (that is, between source terminal and drain electrode end) different, transistors with the different value of gate bias Part 316 can be used as variable resistance, and wherein resistance value is controlled by the voltage of node 315.
In some embodiments, sensing circuit 318 can be configured as through bit line BL1To BLnRead data.In this way Embodiment in, transistor device 316, which is respectively provided with, to be connected to the gate terminal of current source 312, is connected to source electrode line SL1To SLn's Source terminal and the drain electrode end for being connected to ground terminal so that during the reading of RRAM array 302, sensing circuit 318 can pass through by Source electrode line SL1To SLnIt is connected to ground terminal and reads the value of RRAM unit from bit line.In some embodiments, sensing circuit 318 One or more components can be shared with bit line decoder 106.
Fig. 4 A shows some embodiments of the cross section of RRAM unit 400.
RRAM unit 400 includes the RRAM device 418 being arranged on substrate 402.In various embodiments, substrate 402 can One or more tube cores including such as semiconductor crystal wafer and/or on wafer any kind of semiconductor body (for example, Silicon, SiGe, SOI), and metal layer, device, semiconductor and/or the extension of any other type relevant to semiconductor body Layer etc..In some embodiments, substrate 402 may include having the first doping type (for example, n-type doping or p-type doping) Intrinsic dope semiconductor substrates.
Transistor device 404 is arranged in substrate 402.Transistor device 404 includes the source area separated by channel region 407 406 and drain region 408.Transistor device 404 further includes the gate electrode 410 separated by gate dielectric 409 with channel region.Source Polar region domain 406 passes through one or more metal interconnecting layers 414 (for example, metal wire, metal throuth hole and/or conductive contact piece) and connects To source electrode line 412.Gate electrode 410 passes through one or more metal interconnecting layers 414 and is connected to wordline 416.Drain region 408 passes through one A or multiple metal interconnecting layers 414 are connected to the bottom electrode 420 of RRAM device 418.
The bottom electrode 420 of RRAM device 418 is separated by dielectric materials layer 422 with upper electrode 424.Including Lacking oxygen The conductive filament 426 of chain can extend through dielectric materials layer 422 after executing formation process to RRAM device 418.Top The upper electrode of RRAM device 418 is also connected to bit line 428 by metal throuth hole, wherein bit line 428 is formed in covering RRAM device In 418 metal interconnecting layer.In various embodiments, bottom electrode 420 and upper electrode 424 may include conductive material, all Such as platinum (Pt), aluminum bronze (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN) and/or copper (Cu).In various embodiments, dielectric materials layer 422 may include such as nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (WO3), aluminium oxide (Al2O3), tantalum oxide (TaO), molybdenum oxide (MoO) and/or copper oxide (CuO).
Although RRAM unit 400 is shown to have the RRAM device structure of 1T1R (transistor, a resistor), It is it should be appreciated that in other embodiments, disclosed RRAM circuit can be applied as with other RRAM device structure (examples Such as, 2T2R).In addition, source electrode line 412, wordline 416 and bit line 428 can be located in the layer different from shown in the example.
Fig. 4 B shows the schematic diagram 430 of RRAM unit 400.As shown in schematic diagram 430, wordline 416' is connected to transistor The gate terminal 410' of 404'.Transistor 404' includes being connected to the source terminal 406' of source electrode line 412' and being connected to RRAM unit The drain electrode end 408' of the first electrode 420' of 418'.The second electrode 424' of RRAM unit 418' is connected to bit line 428'.
Fig. 5 shows some additional embodiments of the block diagram of RRAM circuit 500, and RRAM circuit 500 includes being configured as changing The kind current limiting element for forming the time.
RRAM circuit 500 includes more root polar curve SL1To SLn, every root polar curve is respectively connected in RRAM array 302 One column RRAM unit.More root polar curve SL1To SLnIt is additionally coupled to switching element 502.Switching element 502 is configured as forming behaviour By more root polar curve SL during work1To SLnIt is selectively connected to current limiting element 310.Current limiting element 310 is configured To limit more bit line BL during formation operation1To BLnOn electric current.
In some embodiments, switching element 502 is configured as more root polar curve SL during read operation1To SLnChoosing It is connected to selecting property sensing circuit 206, the sensing circuit 206 includes data selector 208 and sensing amplifier 210.One In a little embodiments, data selector 208 is configured as during read operation selectively by more bit line BL1To BLnIn with institute Associated one output of the RRAM unit of access is provided to sensing amplifier 210.It in some embodiments, can be in data Arrangement load (for example, resistor) between selector 208 and sense amplifier 210, by more bit line BL1To BLnIn one Electric current output be converted to voltage.Sensing amplifier 210 may include being configured as by the output of data selector 208 and with reference to electricity Press VrefIt is compared a pair of cross coupled inverters to determine the data mode being stored in accessed RRAM unit.
In other embodiments (not shown), RRAM circuit 500 be can be configured as through more bit line BL1To BLnFrom RRAM array 302 reads data.In such some embodiments, sensing circuit passes through bit line decoder 106 and RRAM array 302 separation.In order to enable sensing circuit from more bit line BL1To BLnData are read, switching element 502 can be configured as By more root polar curve SL during read operation1To SLnIt is selectively connected to ground terminal.
In some embodiments, RRAM circuit 500 can also include multiple additional current limiting element 506a to 506n. In such embodiments, switching element 502 is configured as more root polar curve SL during write operation1To SLnSelectively It is connected to multiple extra current restriction element 506a to 506n.Additional current limiting element 506a to 506n is configured to writing More bit line BL are independently limited during entering operation (for example, during set and/or resetting operation)1To BLnIn respective bit line On electric current.For example, additional current limiting element 506a to 506n includes being configured as the first bit line BL of limitation1On electric current Without limiting the first current limiting element 506a of the electric current on the second bit line BL2, and it is configured as the second bit line BL2 of limitation On electric current without limit the first bit line BL1On electric current the second current limiting element 506b.In some embodiments, multiple Extra current restriction element 506a to 506n is configured as more bit line BL during write operation1To BLnOn current limit For the first value, which is greater than current limiting element 310 and is configured as more bit line BL during formation operation1To BLnOn The current limit value that is.
Control unit 504 can connect to switching element 502.Control unit 504 is configured as generating second control signal SCTRL2, second control signal SCTRL2In conjunction with bit line decoder 106 and wordline decoder 108 and/or current limiting element 310 To control the operation of multiple switching element 502a to 502n in switching element 502.For example, control is single during formation operation Member 504 is configured as operation bit line decoder 106 and is applied to more bit line BL will form voltage1To BLn, and at the same time operation Multiple switching element 502a to 502n are with by more root polar curve SL1To SLnIt is connected to current limiting element 310.In the read operation phase Between, control unit 504 is configured as operation bit line decoder 106 and is applied to more positions will be less than the reading voltage to form voltage Line BL1To BLnIn one, and at the same time operating multiple switching element 502a to 502n with by more root polar curve SL1To SLnEven It is connected to sensing circuit 206.During write operation, control unit 504 is configured as operation bit line decoder 106, will be less than The write-in voltage for forming voltage is applied to more bit line BL1To BLnAnd at the same time operating multiple switching element 502a to 502n to incite somebody to action More root polar curve SL1To SLnIt is connected to extra current restriction element 506a to 506n.
Fig. 6 A to Fig. 6 B shows some realities of the method for RRAM circuit of the operation with disclosed current limiting element Apply the block diagram 600 and timing diagram 602 of example.
As shown in block diagram 600 and timing diagram 602, during formation operation 604, has and form voltage value VfBit-line voltage BLvx(v=1 to n) is in moment t1It is applied to more bit line BL1To BLn.Since filament being not present in RRAM device, so most Just formed filament need voltage more higher than subsequent write operation (once for example, filament is formed, can be then using lower Filament is resetted and (disconnected, lead to high resistance) voltage or set (re-forming, cause compared with low resistance) is with storing data state). In moment t1, more wordline WLx(wherein wordline WL of the x=1 into m)x(wherein x=1,2 ... or m) be also activated (and Remaining more wordline is not activated) so that multiple RRAM devices 306 in a line of RRAM array 302 and more root polar curves SL1To SLnBetween form conductive path.More root polar curve SL1To SLnIt is maintained at low source line voltage SLvx(for example, VDD), with Just big voltage difference is formed between the electrode 306a and 306b of RRAM device 306.Big voltage difference drives current through RRAM device Dielectric materials layer in part, so that in moment t2Initial filament is formed in multiple RRAM devices 306 (for example, by generating heat Energy and/or electromagnetic force, thermal energy and/or electromagnetic force cause Lacking oxygen and ion is moved to conductive filament from dielectric materials layer Migration).
Current source 312 is configured as in moment t1Output has the first current value I1Reference current Iref.First current value I1So that reference current IrefTransistor device 316 in bias current restriction element 310, by more bit line BL1To BLnOn Bit line current IBLIt is limited to less than to form value If.As the resistance of RRAM unit reduces (as initial filament is formed), bit line electricity Flow IBLIncrease with time.
During write operation 606, one or more of multiple RRAM devices 306 can be write data into.By Moment t3There to be write-in voltage value VwBit-line voltage BLvx(v=1 to n) is applied to more bit line BL1To BLnA bit line BLx((wherein x=1,2... or n), writes data into one or more of multiple RRAM devices 306, and other more bit lines BL1To BLnIn each may remain in 0V.More root polar curve SL1To SLnIt is maintained at low source line voltage SLvx(for example, VDD), to form potential difference between the electrode 306a and 306b of RRAM device 306, and electric current is driven to pass through dielectric material Layer (leads to the reaction for changing conductive filament).In moment t3, more wordline WLx(wherein wordline WL of the x=1 into m)x(its Middle x=1,2... m) are also activated, with one and more root polar curve SL in multiple RRAM devices 3061To SLnIn one The conductive path formed between root.
In various embodiments, write operation can be set operation (not shown), and set operation is configured as in RRAM Conductive filament is formed between the conductive electrode 306a and 306b of device, so as to cause low resistance state；Or it can be reset behaviour Make (showing), resets operation and be configured as disconnecting the filament between the electrode 306a and 306b of conductive RRAM device 306, to lead Cause high resistance state.In some embodiments, voltage value V is writtenwIt can be less than and form voltage value Vf.For example, write-in voltage value Vw It can have the value between about 0.5V and about 4V, and form voltage value VfIt can have in about 2V and big Value between about 10V.In some embodiments, the write-in voltage V of set operationwOperation is resetted for that can be greater than Write-in voltage Vw。
In some embodiments, current source 312 can be configured as in moment t3Output has second value I2Reference current Iref.Second current value I2So that reference current IrefTransistor device 316 in bias current restriction element 310, so that more Root bit line BL1To BLnIn one on bit line current IBLWith with formation value IfThe initial write current of different (for example, being greater than) Value Iw1.For example, in some embodiments, reference current IrefTransistor device 316 in bias current restriction element 310, with base More bit line BL are not limited in sheet1To BLnIn one on electric current so that initial write current value Iw1Greater than formation value If.With The resistance of RRAM unit increases (when filament disconnects), and write current value is from being originally written into current value Iw1It is reduced to the second write-in electricity Flow valuve Iw2。
It, can be from one or more reading data in multiple RRAM devices 306 during read operation 608.By when Carve t5To have and read voltage value VrBit-line voltage BLvx(v=1 to n) is applied to more bit line BL1To BLnA bit line BLx(wherein x=1,2...n) reads data from one or more in multiple RRAM devices 306, and more bit line BL1To BLn In other bit lines may remain in 0V.In some embodiments, voltage value V is readrWrite-in voltage value V can be less thanw.For example, Read voltage value VrIt can have the value between about 1V and about 2V.Read voltage value VrIt can have and be less than The value of the threshold voltage of RRAM device, to prevent from unintentionally covering the data that (overwrite) is stored in RRAM device.
In some embodiments, current source 312, which is configured as output, has third current value I3Reference current Iref.The Three current value I3Make reference current IrefTransistor device 316 in bias current restriction element 310, so that more bit line BL1Extremely BLnOne bit line current IBLWith with formation value IfThe reading current value of different (for example, being less than).If source line voltage SLvxGreater than reference voltage Vref, then the data obtained state is " 1 ", and if source line voltage SLvxLess than reference voltage Vref, then The data obtained state is " 0 ".
Fig. 7 shows the flow chart for executing some embodiments of the method 700 of formation operation of RRAM array.
Although disclosed method 700 is depicted and described as a series of actions or event herein, should manage The shown sequence of solution, these movements or event is not necessarily to be construed as restrictive.For example, some movements can be in a different order Occur and/or in addition to it is illustrated herein and/or description movement or event other than other movement or event occur simultaneously.Separately Outside, one or more aspects or embodiment that not all of the illustrated actions requires for realizing description herein.In addition, this One or more movements that text is described can execute in one or more individually movement and/or stages.
At step 702, activation is operably coupled to the wordline of a line RRAM device.In some embodiments, wordline A line RRAM device can be connected to by multiple access transistors.
At step 704, formation voltage is applied to more bit lines for being connected to the first electrode of the row RRAM device.? In some embodiments, forms voltage and be applied to all bit lines in the RRAM array including RRAM device.
It, will be on more bit lines during the formation operation of the initial conduction filament formed in RRAM device in step 706 Current limit is lower than formation value.In some embodiments, in step 708, by the transistor device for being connected to source electrode line Grid apply offset signal and carry out operation electric current restriction element to limit the electric current on more bit lines, and source electrode line is connected to the row The second electrode of RRAM device.
In step 710, second voltage is applied to the more root polar curves for the second electrode for being connected to the row RRAM device, with Initial conduction filament is formed in the RRAM device of the row RRAM device.In some embodiments, second voltage can be ground connection 's.
Therefore, this disclosure relates to resistive random access memory (RRAM) circuit comprising current limiting element, electric current Restriction element is configured as improving the formation time of RRAM array by the electric current on more bit lines of limitation, and to allow Generation simultaneously is formed in the RRAM device for being connected to the more bit lines and associated method.
In some embodiments, this disclosure relates to resistive random access memory (RRAM) circuit.RRAM circuit includes Multiple RRAM units, respectively include RRAM device.Bit line decoder is configured as to two be connected in multiple RRAM units More a or more bit lines apply form signal simultaneously.Current limiting element is configured as first in formation RRAM device Simultaneously by the current limit on more bit lines below formation value during the formation operation of beginning conductive filament.
In some embodiments, RRAM circuit further include: control unit is configured as operating the current limit simultaneously Element is to limit the electric current on the bit line, and operation institute's bit line decoder so that the formation signal is applied to institute State more bit lines.
In some embodiments, institute's bit line decoder is configured as that voltage application will be formed during the formation operation One or more in the more bit lines is applied to the more bit lines and during write operation by write-in voltage；With And said write voltage is less than the formation voltage.
In some embodiments, the current limiting element includes: multiple transistor devices, each transistor device difference With one source terminal being operably coupled in the more bit lines.
In some embodiments, the RRAM circuit further include: the transistor of diode connection, with source terminal, ground connection The gate terminal of drain electrode end and the gate terminal for being connected to the multiple transistor device；And current source, it is connected to the diode The gate terminal of the source terminal of the transistor of connection and the multiple transistor device.
In some embodiments, RRAM circuit further include: one or more additional current limiting elements are configured as The electric current on one in the more bit lines is independently limited during write operation.
In some embodiments, each of the multiple RRAM unit respectively includes being connected in the more bit lines One first electrode and the second electrode that source electrode line is connected to by access transistor.
In some embodiments, the current limiting element includes: multiple transistor devices, each transistor device difference Source terminal including being connected to the source electrode line；The transistor of diode connection has source terminal, drain grounded end and connection To the gate terminal of the gate terminal of the multiple transistor device；And current source, it is connected to the transistor of the diode connection The gate terminal of source terminal and the multiple transistor device.
In some embodiments, RRAM circuit further include: sensing circuit, being configured as can during the formation operation It is operatively disconnected from the more bit lines, and is operably coupled to the more bit lines during read operation.
In other embodiments, this disclosure relates to resistive random access memory (RRAM) circuit.RRAM circuit includes Multiple RRAM units respectively include the first electrode for being connected to bit line and are connected to the second of source electrode line by access transistor Electrode.Bit line decoder is configured as to form signal during formation operation while being applied to being connected in multiple RRAM units Two or more more bit lines.Current limiting element is configured as the electric current on more bit lines during formation operation It is limited to the current value smaller than during write operation.
In some embodiments, institute's bit line decoder is configured as that voltage application will be formed during the formation operation One or more in the more bit lines is applied to more bit lines and during said write operation by write-in voltage；With And wherein, said write voltage is less than the formation voltage.
In some embodiments, each of the multiple RRAM unit respectively includes being connected in the more bit lines One first electrode and the second electrode that source electrode line is connected to by access transistor.
In some embodiments, the current limiting element includes: multiple transistor devices, wherein each transistors Part respectively includes the source terminal for being connected to the source electrode line；The transistor of diode connection has source terminal, drain grounded end With the gate terminal for the gate terminal for being connected to the multiple transistor device；And current source, it is connected to the diode connection The gate terminal of the source terminal of transistor and the multiple transistor device.
In some embodiments, RRAM circuit further include: control unit is configured as operating institute during formation is handled Current source is stated to export the first reference current, and exports the second reference current during read operation and write operation.
In some embodiments, RRAM circuit further include: sensing circuit, being configured as can during the formation operation It is disconnected operatively from the more bit lines, and is operably coupled to the more bit lines during read operation.
In some embodiments, RRAM circuit further include: one or more additional current limiting elements are configured as The electric current on one in the more bit lines is independently limited during write operation.
In other embodiments, this disclosure relates to a kind of method for executing formation operation on RRAM circuit.This method packet Include the wordline of the row for the RRAM unit that activation is operably coupled in RRAM array.The method further includes forming letter Number it is applied to more bit lines of the multiple RRAM units being connected in the RRAM cell row simultaneously, to execute the multiple The formation operation of initial conduction filament is formed in RRAM unit.This method further includes during formation operation while by more bit lines On current limit be lower than formation value.
In some embodiments, this method further include: described more by being applied to including the formation signal for forming voltage Root bit line, wherein the more bit lines are connected to the first electrode of the multiple RRAM unit；And the formation electricity will be less than The second voltage of pressure is applied to more root polar curves, wherein more root polar curves are connected to the second of the multiple RRAM unit Electrode.
In some embodiments, this method further include: operationally by sensing circuit from institute during the formation operation It states and is disconnected at more bit lines.
In some embodiments, this method further include: the formation voltage is applied to the institute of the RRAM array simultaneously There is bit line.
Foregoing has outlined the feature of several embodiments so that those skilled in the art may be better understood it is of the invention each Aspect.It should be appreciated by those skilled in the art that they can easily be used for using based on the present invention to design or modify Implement and other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.Art technology Personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from of the invention In the case where spirit and scope, they can make a variety of variations, replace and change herein.

Claims (19)

1. a kind of resistive random access memory RRAM circuit, comprising:
Multiple RRAM units, wherein each RRAM unit respectively includes RRAM device；
Bit line decoder, be configured as to two or more more bit lines connecting in the multiple RRAM unit simultaneously Application forms signal；And
Current limiting element is configured as during the formation operation of the initial conduction filament formed in the RRAM device, will Current value on the more bit lines is limited to less than the current value to form the initial conduction filament simultaneously.
2. RRAM circuit according to claim 1, further includes:
Control unit, be configured as operating the current limiting element with and meanwhile limit the electric current on the more bit lines, And operation institute's bit line decoder is to be applied to the more bit lines for the formation signal.
3. RRAM circuit according to claim 1,
Wherein, institute's bit line decoder is configured as that formation voltage is applied to the more bit lines during the formation operation And voltage will be written during write operation and be applied to one or more in the more bit lines；And
Wherein, said write voltage is less than the formation voltage.
4. RRAM circuit according to claim 1, wherein the current limiting element includes: multiple transistor devices, often A transistor device is respectively provided with one source terminal being operably coupled in the more bit lines.
5. RRAM circuit according to claim 4, further includes:
The transistor of diode connection has source terminal, drain grounded end and the grid for being connected to the multiple transistor device Extreme gate terminal；And
Current source is connected to the source terminal of the transistor of the diode connection and the gate terminal of the multiple transistor device.
6. RRAM circuit according to claim 1, further includes:
One or more additional current limiting elements, are configured as independently limiting the more bit lines during write operation In one on electric current.
7. RRAM circuit according to claim 1, wherein each of the multiple RRAM unit includes RRAM device And access transistor, the RRAM device include one first electrode being connected in the more bit lines and are deposited by described Take one second electrode that transistor is connected in more root polar curves.
8. RRAM circuit according to claim 7, wherein the current limiting element includes:
Multiple transistor devices, each transistor device respectively include one source electrode being connected in more root polar curves End；
The transistor of diode connection has source terminal, drain grounded end and the grid for being connected to the multiple transistor device Extreme gate terminal；And
Current source is connected to the source terminal of the transistor of the diode connection and the gate terminal of the multiple transistor device.
9. RRAM circuit according to claim 7, further includes:
Sensing circuit is configured as operationally disconnecting from the more bit lines during the formation operation, and is reading The more bit lines are operably coupled to during operation.
10. a kind of resistive random access memory RRAM circuit, comprising:
Multiple RRAM units, wherein each RRAM unit includes RRAM device and access transistor, and the RRAM device includes One first electrode being connected in more bit lines and one in more root polar curves is connected to by the access transistor Second electrode；
Bit line decoder is configured as to be formed during the formation operation of the initial conduction filament formed in the RRAM device Signal is applied to more bit lines connecting with two or more in the multiple RRAM unit simultaneously；And
Current limiting element is configured as the current value of the electric current on the more bit lines being limited in the formation operation phase Between it is smaller than during write operation.
11. RRAM circuit according to claim 10,
Wherein, institute's bit line decoder be configured as during the formation operation being formed voltage be applied to more bit lines and Voltage will be written during said write operation and be applied to one or more in the more bit lines；And
Wherein, said write voltage is less than the formation voltage.
12. RRAM circuit according to claim 10, wherein the current limiting element includes:
Multiple transistor devices, wherein each transistor device respectively includes one be connected in more root polar curves Source terminal；
The transistor of diode connection has source terminal, drain grounded end and the grid for being connected to the multiple transistor device Extreme gate terminal；And
Current source is connected to the source terminal of the transistor of the diode connection and the gate terminal of the multiple transistor device.
13. RRAM circuit according to claim 12, further includes
Control unit is configured as operating the current source during formation is handled to export the first reference current, and is reading The second reference current is exported during extract operation and write operation.
14. RRAM circuit according to claim 10, further includes:
Sensing circuit is configured as operationally disconnecting at the more bit lines during the formation operation, and is reading The more bit lines are operably coupled to during extract operation.
15. RRAM circuit according to claim 10, further includes:
One or more additional current limiting elements, are configured as independently limiting the more bit lines during write operation In one on electric current.
16. the method that a kind of pair of RRAM circuit executes formation operation, comprising:
Activate the wordline for the RRAM cell row being operably coupled in RRAM array；
To the multiple RRAM units being connected in the RRAM cell row more bit lines and meanwhile apply form signal, with execute exist The formation operation of initial conduction filament is formed in the multiple RRAM unit；And
The current value on the more bit lines is limited in be lower than simultaneously during formation operation and forms the initial conduction filament Current value.
17. according to the method for claim 16, further includes:
To include forming the formation signal of voltage to be applied to the more bit lines, wherein the multiple RRAM unit it is every One includes RRAM device and access transistor, and the first electrode of the RRAM device is connected to one in the more bit lines Root；And
The second voltage for forming voltage will be less than and be applied to more root polar curves, wherein the second electrode of the RRAM device One in more root polar curves is connected to by the access transistor.
18. according to the method for claim 17, further includes:
Operationally sensing circuit is disconnected at the more bit lines during the formation operation.
19. according to the method for claim 17, further includes:
The formation voltage is applied to all bit lines of the RRAM array simultaneously.
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