CN112017715B - Resistive random access memory and protection circuit thereof - Google Patents
Resistive random access memory and protection circuit thereof Download PDFInfo
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- CN112017715B CN112017715B CN202010859320.8A CN202010859320A CN112017715B CN 112017715 B CN112017715 B CN 112017715B CN 202010859320 A CN202010859320 A CN 202010859320A CN 112017715 B CN112017715 B CN 112017715B
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0059—Security or protection circuits or methods
Abstract
The invention discloses a protection circuit of a resistive random access memory, which comprises: the controllable switch unit and the comparison unit are connected, the comparison unit controls the controllable switch unit to be connected when direct-current voltage for Forming/Set operation is applied to the corresponding resistive random access memory unit, so that the corresponding resistive random access memory unit is changed from a high-resistance state to a low-resistance state, and the controllable switch unit is controlled to be disconnected at the moment when the corresponding resistive random access memory unit finishes the change from the high-resistance state to the low-resistance state, so that a Forming/Set access is disconnected, the problem that the resistive random access memory is damaged due to long-time application of voltage to the resistive random access memory is solved, and the service life of the resistive random access memory is greatly prolonged. The invention also discloses a resistive random access memory with the protection circuit.
Description
Technical Field
The invention relates to the technical field of storage, in particular to a protection circuit of a resistive random access memory and the resistive random access memory with the protection circuit.
Background
In the related art, due to the unique working principle and the device structure of the resistive random access memory (RRAN), before the resistive random access memory is normally used, a Forming operation is required, that is, a corresponding operation voltage is applied to excite the resistive random access memory to realize the conversion of a high-resistance state and a low-resistance state, the current resistive random access memory mainly has a direct-current voltage operation mode, although the mode has almost infinite energy, the operation voltage can be reduced, and the operation success is ensured, but because the resistive random access memory has the resistance change principle related to the strength of an electric field, the cycle and retention characteristics of the resistive random access memory are damaged due to the long-time action of the voltage on the resistive random access memory, so that the service life of the resistive random access memory is greatly shortened.
Disclosure of Invention
The present invention is directed to solving at least one of the problems in the art to some extent. Therefore, one object of the present invention is to provide a protection circuit for a resistive random access memory, which enables the resistive random access memory to instantly and automatically turn off a Forming/Set path after resistive random access is completed by adding the protection circuit to the Forming/Set path, thereby avoiding the problem of damage to the resistive random access memory due to long-term voltage acting on the resistive random access memory, and greatly prolonging the service life of the resistive random access memory.
The second purpose of the invention is to provide a resistive random access memory.
In order to achieve the above object, a protection circuit of a resistive random access memory according to an embodiment of a first aspect of the present invention is provided, where the protection circuit is disposed corresponding to a Forming/Set path of the resistive random access memory, and the protection circuit includes: the first end of the controllable switch unit is connected to the ground wire of the corresponding resistive random access memory unit, and the second end of the controllable switch unit is grounded; the output end of the comparison unit is connected with the control end of the controllable switch unit, the comparison unit controls the controllable switch unit to be switched on when the corresponding resistive random access memory unit is applied with direct-current voltage for Forming/Set operation, so that the corresponding resistive random access memory unit is changed from a high-resistance state to a low-resistance state, and the controllable switch unit is controlled to be switched off at the moment when the corresponding resistive random access memory unit finishes changing from the high-resistance state to the low-resistance state, so that the Forming/Set access is switched off.
According to the protection circuit of the resistive random access memory, the comparison unit controls the controllable switch unit to be switched on when the direct-current voltage for Forming/Set operation is applied to the corresponding resistive random access memory unit, so that the corresponding resistive random access memory unit is changed from a high-resistance state to a low-resistance state, and the controllable switch unit is controlled to be switched off at the moment when the corresponding resistive random access memory unit is changed from the high-resistance state to the low-resistance state, so that a Forming/Set access is switched off, the problem that the resistive random access memory is damaged due to the fact that voltage acts on the resistive random access memory for a long time is solved, and the service life of the resistive random access memory is greatly prolonged.
In addition, the protection circuit of the resistive random access memory proposed according to the above embodiment of the present invention may further have the following additional technical features:
optionally, according to an embodiment of the present invention, the protection circuit of the resistive random access memory further includes a current mirror unit, where the current mirror unit is connected between the second end of the controllable switch unit and ground, and the current mirror unit is configured to limit a current of the Forming/Set path to determine a resistance value of the corresponding resistive random access memory unit in a low resistance state.
Optionally, according to an embodiment of the present invention, the controllable switch unit includes a first MOS transistor, a gate of the first MOS transistor is used as a control end of the controllable switch unit, a drain of the first MOS transistor is used as a first end of the controllable switch unit, and a source of the first MOS transistor is used as a second end of the controllable switch unit.
Optionally, according to an embodiment of the present invention, the comparing unit includes a comparator, a first input terminal of the comparator is connected to the drain of the first MOS transistor, a second input terminal of the comparator is connected to the reference voltage providing terminal, and an output terminal of the comparator is connected to the gate of the first MOS transistor.
Alternatively, according to an embodiment of the present invention, the current mirror unit includes: a bias current source; the source electrode of the second MOS tube is grounded, the drain electrode of the second MOS tube is connected with the source electrode of the first MOS tube, and the grid electrode of the second MOS tube is connected to the bias current source; and the source electrode of the third MOS tube is grounded, the grid electrode of the third MOS tube is connected with the grid electrode of the second MOS tube, and the drain electrode of the third MOS tube is connected with the grid electrode of the third MOS tube and then is connected to the bias current source.
Optionally, according to an embodiment of the present invention, a gating transistor in the Forming/Set path is connected between the first end of the controllable switch unit and a ground line of the corresponding resistive random access memory unit, where the gating transistor is configured to select the corresponding resistive random access memory unit to perform a Forming/Set operation.
Optionally, according to an embodiment of the present invention, the corresponding resistance change memory unit includes a plurality of resistance change memory modules, and the plurality of resistance change memory modules share a bit line and a ground line so as to perform a Forming/Set operation simultaneously.
Optionally, according to an embodiment of the present invention, each of the resistive memory modules includes a resistive element and a control transistor, one end of the resistive element is connected to a same bit line, the other end of the resistive element is connected to a first end of the control transistor, a control end of the control transistor is connected to a corresponding word line, and a second end of the control transistor is connected to a same ground line.
In order to achieve the above object, a resistive random access memory according to an embodiment of a second aspect of the present invention includes: a plurality of resistance change memory cells; each protection circuit corresponds to one resistive random access memory unit and is used for protecting the corresponding resistive random access memory unit which performs the Forming/Set operation.
According to the resistive random access memory provided by the embodiment of the invention, the protection circuit of the resistive random access memory protects the corresponding resistive random access memory unit, so that the resistive random access memory unit can instantly and automatically turn off the Forming/Set channel after the resistive random access memory unit finishes resistive random access, the problem that the resistive random access memory is damaged due to the long-term action of voltage on the resistive random access memory unit is avoided, and the service life of the resistive random access memory is greatly prolonged.
In addition, the resistive random access memory proposed according to the above embodiment of the present invention may further have the following additional technical features:
optionally, in an embodiment of the present invention, a plurality of the resistance change memory cells are arranged in an array.
Drawings
Fig. 1 is a schematic diagram of a protection circuit of a resistance change memory cell according to an embodiment of the invention;
fig. 2 is a schematic diagram of a protection circuit of a plurality of resistance change memory cells according to an embodiment of the invention;
fig. 3 is a current-voltage graph illustrating resistance change behavior of a resistance change memory according to an embodiment of the present invention;
fig. 4 is a voltage-time graph of an operating voltage applied during a resistance change process of a resistance change memory according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
According to the resistive random access memory and the protection circuit thereof, the Forming/Set passage is automatically turned off instantly after the resistive random access memory finishes the resistive random access memory by adding the protection circuit on the Forming/Set passage, so that the voltage which is originally acted on the resistive random access memory for a long time acts on the transistor without passage current, the resistive random access memory is prevented from being damaged, and the service life of an RRAM device is greatly prolonged
In order to better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
A protection circuit of a resistance change memory and a resistance change memory having the protection circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in fig. 1, the protection circuit of the resistive random access memory according to the embodiment of the present invention is configured to correspond to a Forming/Set path of the resistive random access memory, and includes a controllable switch unit 10 and a comparison unit 20.
A first terminal of the controllable switch unit 101 is connected to the ground line SL of the corresponding resistive memory unit, and a second terminal of the controllable switch unit 101 is grounded.
In the embodiment of the present invention, the controllable switch unit 10 includes a first MOS transistor Q1, a gate G of the first MOS transistor Q1 is used as a control terminal of the controllable switch unit 10, a drain D of the first MOS transistor Q1 is used as a first terminal of the controllable switch unit 10, and a source S of the first MOS transistor Q1 is used as a second terminal of the controllable switch unit 10.
In an embodiment, the first MOS transistor Q1 is an NMOS transistor.
It should be noted that the ground line SL of the corresponding resistance change memory cell turns on the external decoder and the driving circuit to the ground.
The output end of the comparison unit 20 is connected to the control end of the controllable switch unit 10, and the comparison unit 20 controls the controllable switch unit 10 to be turned on when the direct-current voltage for Forming/Set operation is applied to the corresponding resistive random access memory unit, so that the corresponding resistive random access memory unit is changed from a high-resistance state to a low-resistance state, and controls the controllable switch unit 10 to be turned off at the moment when the corresponding resistive random access memory unit completes the change from the high-resistance state to the low-resistance state, so as to turn off the Forming/Set path.
As an embodiment, the comparing unit includes a comparator U1, a first input terminal of the comparator U1 is connected to the drain D of the first MOS transistor Q1, a second input terminal of the comparator is connected to the reference voltage supply terminal Vref, and an output terminal of the comparator U1 is connected to the gate G of the first MOS transistor Q1.
That is, by providing the comparator U1 and the first MOS transistor Q1 in the Forming/Set path of the resistive random access memory, as shown in fig. 3 and 4, in the Forming/Set operation process, the ground line SL of the corresponding resistive random access memory unit applies the dc voltage VBL and steps up, when the resistive random access memory does not successfully change the resistance, the drain D of the first MOS transistor Q1 is a low voltage, that is, the first input end of the comparator U1 is a low voltage, and at this time, the first input end of the comparator U1 is smaller than the second input end and is connected to the reference voltage, so that the output end of the comparator U1 outputs a high voltage and applies the high voltage to the gate G of the first MOS transistor Q1 connected to the output end of the comparator U1, so that the first MOS transistor Q1 is turned on, and the corresponding resistive random access memory unit is changed from the high resistance state to the low resistance state; when the resistive random access memory successfully changes the resistance, the potential of the drain D (point N1) of the first MOS transistor Q1 rises due to the voltage division on the series path, and when the potential of the drain D of the first MOS transistor Q1 exceeds the second input end of the comparator U1 and is connected to the reference voltage, the output end of the comparator U1 outputs a low voltage to close the first MOS transistor Q1, so that the source S (point N2) of the first MOS transistor Q1 falls to the ground, and the Forming/Set path is closed.
Further, in the present embodiment, the resistance-variable memory further includes a current mirror unit 40, the current mirror unit 40 is connected between the second end of the controllable switch unit 10 and the ground, and the current mirror unit 40 is configured to limit the current of the Forming/Set path to determine the resistance value of the corresponding resistance-variable memory unit in the low resistance state.
As one embodiment, the current mirror unit includes: a bias current source Ibias, a second MOS transistor Q2 and a third MOS transistor Q3.
The source electrode of the second MOS tube Q2 is grounded, the drain electrode of the second MOS tube Q2 is connected with the source electrode S of the first MOS tube Q1, and the grid electrode of the second MOS tube Q2 is connected to a bias current source Ibias; the source electrode of the third MOS tube Q3 is grounded, the grid electrode of the third MOS tube Q3 is connected with the grid electrode of the second MOS tube Q2, and the drain electrode of the third MOS tube Q3 is connected with the grid electrode of the third MOS tube Q3 and then is connected to a bias current source Ibias.
That is, the current mirror unit 40 limits the current of the Forming/Set path by setting the bias current source Ibias, the second MOS transistor Q2 and the third MOS transistor Q3 to determine the resistance value of the corresponding resistive random access memory unit in the low resistance state.
In addition, as a specific embodiment, the gating transistor 50 in the Forming/Set path is connected between the first end of the controllable switch unit 10 and the ground line SL of the corresponding resistive memory unit, wherein the gating transistor 50 is used for selecting the corresponding resistive memory unit to perform the Forming/Set operation; the corresponding resistive random access memory unit comprises a plurality of resistive random access memory modules, and the plurality of resistive random access memory modules share a bit line BL and a ground line SL so as to simultaneously perform the Forming/Set operation; each resistive random access memory module comprises a resistive random access element 3010 and a control transistor 3011, one end of the resistive random access element 3010 is connected to the same bit line BL, the other end of the resistive random access element 3010 is connected to a first end of the control transistor 3011, a control end of the control transistor 3011 is connected to a corresponding word line WL, and a second end of the control transistor 3011 is connected to the same ground line BL.
That is to say, as shown in fig. 2, a corresponding resistive memory unit is disposed in the Forming/Set path, the corresponding resistive memory unit includes a plurality of resistive memory modules, each resistive memory module includes a resistive element 3010 and a control transistor 3011, each resistive memory module is correspondingly provided with a protection circuit, the resistive element 3010 and the control transistor 3011 of the same resistive memory module share a bit line BL and a ground line SL, and the ground line SL of the same resistive memory module is connected to the first end of the controllable switch unit 10 through the gating transistor 50, so that the corresponding resistive memory unit is selected through the gating transistor 50 to perform the Forming/Set operation, and the corresponding protection circuit is used for protection.
It should be noted that due to the self-turn-off characteristic of the protection circuit, a plurality of resistive random access memories can be simultaneously subjected to direct current operation in an array, so that the operation time is greatly reduced.
In summary, according to the protection circuit of the resistive random access memory in the embodiment of the invention, the comparison unit controls the controllable switch unit to be turned on when the direct-current voltage for Forming/Set operation is applied to the corresponding resistive random access memory unit, so that the corresponding resistive random access memory unit is changed from the high-resistance state to the low-resistance state, and controls the controllable switch unit to be turned off at the moment when the corresponding resistive random access memory unit completes the change from the high-resistance state to the low-resistance state, so as to turn off the Forming/Set path, thereby avoiding the problem that the resistive random access memory is damaged due to the long-time action of the voltage on the resistive random access memory, and greatly prolonging the service life of the resistive random access memory.
In addition, as shown in fig. 2, a resistive random access memory according to an embodiment of the present invention includes a plurality of resistive random access memory cells and a plurality of protection circuits of the resistive random access memory as described in the foregoing embodiments, where each protection circuit is disposed corresponding to one resistive random access memory cell to protect the corresponding resistive random access memory cell performing a Forming/Set operation.
Optionally, in an embodiment of the present invention, the plurality of resistive random access memory cells may be arranged in an array.
According to the resistive random access memory provided by the embodiment of the invention, the protection circuit of the resistive random access memory protects the corresponding resistive random access memory unit, so that the resistive random access memory unit can instantly and automatically turn off the Forming/Set channel after the resistive random access memory unit finishes resistive random access, the problem that the resistive random access memory is damaged due to the long-term action of voltage on the resistive random access memory unit is avoided, and the service life of the resistive random access memory is greatly prolonged.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above should not be understood to necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A protection circuit of a resistive random access memory is characterized in that the protection circuit is arranged corresponding to a Forming/Set path of the resistive random access memory, and the protection circuit comprises:
the first end of the controllable switch unit is connected to the ground wire of the corresponding resistive random access memory unit, and the second end of the controllable switch unit is grounded;
the output end of the comparison unit is connected with the control end of the controllable switch unit, the comparison unit controls the controllable switch unit to be switched on when the corresponding resistive random access memory unit is applied with direct-current voltage for Forming/Set operation, so that the corresponding resistive random access memory unit is changed from a high-resistance state to a low-resistance state, and the controllable switch unit is controlled to be switched off at the moment when the corresponding resistive random access memory unit finishes changing from the high-resistance state to the low-resistance state, so that the Forming/Set access is switched off.
2. The protection circuit of the resistive random access memory according to claim 1, further comprising a current mirror unit connected between the second end of the controllable switch unit and ground, wherein the current mirror unit is configured to limit a current of the Forming/Set path to determine a resistance value of the corresponding resistive random access memory unit in a low resistance state.
3. The protection circuit of the resistive random access memory according to claim 2, wherein the controllable switch unit comprises a first MOS transistor, a gate of the first MOS transistor is used as a control terminal of the controllable switch unit, a drain of the first MOS transistor is used as a first terminal of the controllable switch unit, and a source of the first MOS transistor is used as a second terminal of the controllable switch unit.
4. The protection circuit of the resistive random access memory according to claim 3, wherein the comparison unit comprises a comparator, a first input terminal of the comparator is connected to a drain electrode of the first MOS transistor, a second input terminal of the comparator is connected to a reference voltage supply terminal, and an output terminal of the comparator is connected to a gate electrode of the first MOS transistor.
5. The protection circuit of a resistive random access memory according to claim 3, wherein the current mirror unit includes:
a bias current source;
the source electrode of the second MOS tube is grounded, the drain electrode of the second MOS tube is connected with the source electrode of the first MOS tube, and the grid electrode of the second MOS tube is connected to the bias current source;
and the source electrode of the third MOS tube is grounded, the grid electrode of the third MOS tube is connected with the grid electrode of the second MOS tube, and the drain electrode of the third MOS tube is connected with the grid electrode of the third MOS tube and then is connected to the bias current source.
6. The protection circuit of the resistive random access memory according to any one of claims 1 to 5, wherein a gating transistor in the Forming/Set path is connected between a first end of the controllable switch unit and a ground line of the corresponding resistive random access memory unit, wherein the gating transistor is used for selecting the corresponding resistive random access memory unit to perform the Forming/Set operation.
7. The protection circuit of the resistive-switching memory according to claim 6, wherein the respective resistive-switching memory cells include a plurality of resistive-switching memory modules that share a bit line and a ground line so as to simultaneously perform a Forming/Set operation.
8. The protection circuit of the resistive random access memory according to claim 7, wherein each of the resistive random access memory modules includes a resistive random access element and a control transistor, one end of the resistive random access element is connected to a same bit line, the other end of the resistive random access element is connected to a first end of the control transistor, a control end of the control transistor is connected to a corresponding word line, and a second end of the control transistor is connected to a same ground line.
9. A resistance change memory, characterized by comprising:
a plurality of resistance change memory cells;
a plurality of protection circuits of the resistive random access memory according to any one of claims 1 to 8, wherein each protection circuit is arranged corresponding to one resistive random access memory unit so as to protect the corresponding resistive random access memory unit which performs the Forming/Set operation.
10. The resistive random access memory according to claim 9, wherein the plurality of resistive random access memory cells are arranged in an array.
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| CN109327131A (en) * | 2018-09-29 | 2019-02-12 | 上海南芯半导体科技有限公司 | A kind of current limiting switch circuit and switching power unit |
| CN111091858A (en) * | 2019-12-31 | 2020-05-01 | 清华大学 | Operation method of resistive random access memory array |
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