CN102254803A - Method for manufacturing resistive type memory - Google Patents
Method for manufacturing resistive type memory Download PDFInfo
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- CN102254803A CN102254803A CN2011102218642A CN201110221864A CN102254803A CN 102254803 A CN102254803 A CN 102254803A CN 2011102218642 A CN2011102218642 A CN 2011102218642A CN 201110221864 A CN201110221864 A CN 201110221864A CN 102254803 A CN102254803 A CN 102254803A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 238000003860 storage Methods 0.000 claims abstract description 87
- 238000000137 annealing Methods 0.000 claims abstract description 22
- 239000010949 copper Substances 0.000 claims description 116
- 229910052802 copper Inorganic materials 0.000 claims description 61
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 55
- 238000002360 preparation method Methods 0.000 claims description 50
- -1 oxonium ion Chemical class 0.000 claims description 34
- 230000003647 oxidation Effects 0.000 claims description 33
- 238000007254 oxidation reaction Methods 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 25
- 238000002513 implantation Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 14
- 239000007924 injection Substances 0.000 claims description 14
- 239000000203 mixture Substances 0.000 claims description 13
- 229910052718 tin Inorganic materials 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052684 Cerium Inorganic materials 0.000 claims description 3
- 229910004166 TaN Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 229910052748 manganese Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 229910052774 Proactinium Inorganic materials 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000008901 benefit Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 230000000295 complement effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 157
- 239000011229 interlayer Substances 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 13
- 238000005530 etching Methods 0.000 description 11
- 239000013078 crystal Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 239000007772 electrode material Substances 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 208000005189 Embolism Diseases 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000000354 decomposition reaction Methods 0.000 description 4
- 210000002615 epidermis Anatomy 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910008482 TiSiN Inorganic materials 0.000 description 2
- 229910008651 TiZr Inorganic materials 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 229910016411 CuxO Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 238000009388 chemical precipitation Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- MPTQRFCYZCXJFQ-UHFFFAOYSA-L copper(II) chloride dihydrate Chemical compound O.O.[Cl-].[Cl-].[Cu+2] MPTQRFCYZCXJFQ-UHFFFAOYSA-L 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
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- 239000011368 organic material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-O oxonium Chemical compound [OH3+] XLYOFNOQVPJJNP-UHFFFAOYSA-O 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
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Abstract
The invention provides a method for manufacturing a resistive type memory, comprising the following steps: constructing a picture for a lower electrode and carrying out oxygen ion implantation on the lower electrode to form an oxide storage medium layer on the lower electrode; annealing the oxide storage medium layer; and constructing a picture on the oxide storage medium layer and forming an upper electrode. By using the method, an empty hole is not generated between the storage medium layer and the lower electrode; and the oxygen storage medium layer is even, and O elements are distributed evenly in the oxygen storage medium layer. The resistive type memory manufactured by the method has the advantages of low manufacturing cost and good effect and is easy to integrate with a CMOS (complementary metal oxide semiconductor) technology.
Description
Technical field
Invention relates to a kind of preparation method of semiconductor device, relates in particular to a kind of preparation method of resistor-type memory.
Background technology
Memory occupies an important position in semi-conductor market.Because constantly popularizing of portable electric appts, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by flash memory (Flash Memory).But because the requirement of stored charge, the floating boom of flash memory can not be with the unrestricted attenuate of the development of technology, and the limit that report predicted flash memory technology is arranged is about 32nm, and this just forces people to seek the more superior nonvolatile memory of future generation of performance.
Recently resistor-type memory (Resistive Switching Memory) because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to.Resistor-type memory passes through action of electric signals, make storage medium at high resistance state (High Resistance State, be abbreviated as HRS) and low resistance (Low Resistance State is abbreviated as LRS) but inverse conversion between the state, thereby realize memory function.The storage medium material that resistor-type memory uses can be the SrZrO of phase-change material, doping
3, ferroelectric material PbZrTiO
3, ferromagnetic material Pr
1-xCa
xMnO
3, binary metal oxide material, organic material etc., wherein, Cu
xO (1＜x≤2) material is shown great attention to.This is because of Cu extensive use in interconnection process, Cu
xCan generating through conventional means above Cu embolism or Cu line of O material only needs the extra 1-2 of increasing piece photolithography plate to get final product, and be with low cost, and can realize three-dimensional stacked structure with the multilayer interconnection line.
Disclosed Chinese patent application CN101110393A disclosed a kind of Cu on January 23rd, 2008
xPreparation of O Memister and the integrated method of copper wiring technique, it forms Cu by plasma oxidation or thermal oxidation
xThe O storage medium.Adopt the Cu of this method preparation
xThe O based resistance memory is with low cost, easy and CMOS technology is integrated, but has following shortcoming: (1) is easily at Cu
xProduce the cavity between O storage medium and Cu matrix.(2) because the Cu interconnection line is generally polycrystalline structure, during with its oxidation, the oxidation rate on crystal grain and the crystal boundary is different, causes the Cu that forms with plasma oxidation or thermal oxidation
xThe O uniformity of film is relatively poor.(3) Cu
xThe distribution of O element directly is associated with the quality of device performance in the O film, with the distribution of the very difficult effectively regulation and control O element of the method for plasma oxidation or thermal oxidation in film.
Summary of the invention
At the above-mentioned shortcoming that exists in the background technology, the object of the present invention is to provide a kind of preparation method of resistor-type memory, it makes and does not produce the cavity between oxide storage medium layer and the bottom electrode matrix.
At the above-mentioned shortcoming that exists in the background technology, another object of the present invention is to provide a kind of preparation method of resistor-type memory, it makes that the oxide storage medium layer is even.
At the above-mentioned shortcoming that exists in the background technology, a further object of the present invention is to provide a kind of preparation method of resistor-type memory, and it makes the O element be evenly distributed in the oxide storage medium layer.
In order to reach purpose of the present invention, the invention provides a kind of preparation method of resistor-type memory, comprise step: to the bottom electrode composition, described bottom electrode is carried out oxonium ion inject, so that bottom electrode forms the oxide storage medium layer; Described oxide storage medium layer is carried out annealing in process; And on described oxide storage medium layer composition and form top electrode.
In preparation method according to resistor-type memory of the present invention, the bottom electrode composition is included in blanket dielectric layer is set on the described bottom electrode and in described blanket dielectric layer, offers the perforate that described bottom electrode is exposed, described bottom electrode is carried out oxonium ion inject and undertaken by described perforate.
In preparation method according to resistor-type memory of the present invention, described bottom electrode is carried out implantation temperature that oxonium ion injects is lower than the heating-up temperature that plasma oxidation or thermal oxidation method produce the oxide storage medium layer, implantation temperature is preferably below 200 ℃, be preferably room temperature～100 ℃ again, more preferably room temperature～50 ℃, most preferably be room temperature.
In the preparation method according to resistor-type memory of the present invention, described bottom electrode is selected from Ta, TaN, Cu, W, Ti, TiN, Zr, Ni, Co, Ce, In, Fe, Cr, Mn, Al, Ag, Hf, Mg, V, Sn.
In the preparation method according to resistor-type memory of the present invention, described bottom electrode is the copper lead-in wire that is formed in the copper wiring technique of Damascus in the groove, and described oxide storage medium layer is Cu
xO base storage medium layer, wherein 1＜x≤2.
In the preparation method according to resistor-type memory of the present invention, for described copper lead-in wire, in the step of carrying out oxonium ion injection formation oxide storage medium layer, the implantation dosage of oxonium ion is 1 * 10
8/ cm
2～1 * 10
18/ cm
2, more preferably 1 * 10
10/ cm
2～1 * 10
16/ cm
2
In preparation method according to resistor-type memory of the present invention, for described copper lead-in wire, inject the step that forms the oxide storage medium layer carrying out oxonium ion, it is 500e～500ke, 5ke～100ke more preferably that oxonium ion injects energy.
In preparation method according to resistor-type memory of the present invention, for described copper lead-in wire, inject to form the step of oxide storage medium layer carrying out oxonium ion, implantation temperature is below 200 ℃, be preferably room temperature～100 ℃, more preferably room temperature～50 ℃, most preferably be room temperature.
In preparation method according to resistor-type memory of the present invention, for described copper lead-in wire, inject the step that forms the oxide storage medium layer carrying out oxonium ion, injection pressure is vacuum, preferably less than 2 * 10
-3Pa, be more preferably less than 1 * 10
-3Pa.
In preparation method according to resistor-type memory of the present invention, for described copper lead-in wire, when described oxide storage medium layer was carried out annealing in process, annealing temperature was 50 ℃～800 ℃, preferred 200 ℃～500 ℃, more preferably 300 ℃～450 ℃.
In the preparation method according to resistor-type memory of the present invention, for described copper lead-in wire, when described oxide storage medium layer was carried out annealing in process, annealing time was 1s～1h, be preferably 0.5min～5min.
In the preparation method according to resistor-type memory of the present invention, for described copper lead-in wire, when described oxide storage medium layer was carried out annealing in process, annealing pressure was vacuum or normal pressure; Annealing atmosphere is N
2, or inert gas.
In the preparation method according to resistor-type memory of the present invention, for described copper lead-in wire, the thickness of described oxide storage medium layer is 0.5nm～500nm, be preferably 5nm～100nm.
Technique effect of the present invention is as follows.
By mode and the employing implantation temperature formation oxide storage medium layer lower that adopts oxonium ion to inject, can effectively avoid producing between oxide storage medium layer and the bottom electrode matrix cavity than the heating-up temperature of plasma oxidation or thermal oxidation method generation oxide storage medium layer.
Form the oxide storage medium layer by the oxonium ion injection mode, can effectively eliminate of the influence of bottom electrode crystal grain, improve the homogeneity of oxide storage medium layer oxide storage medium layer growth.
By control to injection energy and implantation dosage, can realize the accurate control that the O element distributes in the oxide storage medium layer, thereby make the distribution of oxygen vacancy concentration in the oxide storage medium precisely controlled, effectively the activation voltage of abatement device, improve device yield, reduce the discreteness of device parameters.
Adopt the resistor-type memory of preparation method's preparation of the present invention to have low, effective, the easy and integrated advantage of CMOS technology of cost of manufacture.
Description of drawings
Fig. 1 is the flow chart according to the preparation method of resistor-type memory of the present invention;
Fig. 2 to Fig. 4 is the STRUCTURE DECOMPOSITION schematic diagram according to preparation method's process of resistor-type memory of the present invention;
Fig. 5 is according to Cu of the present invention
xThe preparation method's of O based resistance memory flow chart; And
Fig. 6 to Figure 16 is the Cu integrated with dual damascene process
xThe STRUCTURE DECOMPOSITION figure of preparation method's process of O based resistance memory.
Wherein, description of reference numerals is as follows:
S11, S12, S13, S14, S21, S22, S23, S24, S25, S26 step
21 blanket dielectric layer, 23 oxide storage medium layer, 27 holes
Metallic dielectric layer before 30 top electrodes, 40 bottom electrodes 100
101 first interlayer dielectric layers, 102 second interlayer dielectric layers 103 the 3rd interlayer dielectric layer
201 first etching barrier layer 202a, the first block layer 202b, the second block layer
203 second etching barrier layers, 204 anti-reflecting layers, 300 holes
401,402 first diffusion impervious layers, 403,404 second diffusion impervious layers
Two parts of 500 second layer copper lead-in wire, 501,502 ground floor copper lead-in wire
503,504 bronze medal embolisms, 601 first grooves, 602 second grooves
700 Cu
xO base storage medium layer 800 upper electrode material layers 801 top electrode
903 tungsten plugs
Embodiment
Below in conjunction with the preparation method of description of drawings according to resistor-type memory of the present invention.
Fig. 1 is the flow chart according to the preparation method of resistor-type memory of the present invention, and Fig. 2 to Fig. 4 is the STRUCTURE DECOMPOSITION schematic diagram according to preparation method's process of resistor-type memory of the present invention.Describe the preparation method of resistor-type memory in detail below in conjunction with Fig. 1 to Fig. 4.
With reference to Fig. 1 and in conjunction with Fig. 2 to Fig. 4, comprise according to the preparation method of resistor-type memory of the present invention: step S11, perforate exposes bottom electrode, and is illustrated in figures 1 and 2; Step S12 carries out the O ion to the bottom electrode that exposes and injects, so that the bottom electrode that exposes forms the oxide storage medium layer, as shown in figures 1 and 3; Step S13 anneals to the oxide storage medium layer; And step S14, composition and form top electrode on the oxide storage medium layer, as shown in Figure 1 and Figure 4.
In step S11, as shown in Figure 2, perforate exposure bottom electrode normally carries out in to bottom electrode 40 compositions.In to bottom electrode 40 compositions, blanket dielectric layer 21 is set on bottom electrode 40 usually, hole-opening 27 is actual to be to carry out in the blanket dielectric layer 21 on bottom electrode 40.Offering of hole 27 is used for the local cellar area size that exposes bottom electrode and define storage medium layer.In the present invention, bottom electrode 40 can be selected from but be not limited only to Ta, TaN, Cu, W, Ti, TiN, Zr, Ni, Co, Ce, In, Fe, Cr, Mn, Al, Ag, Hf, Mg, V, Sn.Blanket dielectric layer 21 can be selected from but be not limited only to silica, silicon nitride.Hole 27 can form by the method for photoetching or etching.By step S11, finish the technology in early stage of preparation resistor-type memory.
In step S12, as shown in Figure 3,, injects the bottom electrode that exposes by partly being carried out oxonium ion, form certain thickness oxide storage medium layer 23.In this step, the bottom electrode metal of exposure and oxonium ion generation chemical reaction generate the oxide storage medium layer, it should be noted that blanket dielectric layer 21 plays mask layer simultaneously when oxonium ion injects.In this step, the bottom electrode that exposes is partly carried out oxonium ion inject the low implantation temperature of heating-up temperature that adopts than plasma oxidation or thermal oxidation method generation oxide storage medium layer.Look concrete condition, for example implantation temperature can carry out below 200 ℃, can be room temperature～200 ℃, preferred room temperature～100 ℃, and more preferably room temperature～50 ℃ most preferably are room temperature.Certainly, it also is feasible adopting the temperature that is lower than room temperature, as long as the cost of temperature control relevant device allows in production practices.
In step S13, the oxide storage medium layer 23 that forms among the step S12 is carried out annealing in process.
In step S14, after step S13 finishes, composition and form top electrode 30, top electrode 30 capping oxide storage medium layer 23 and blanket dielectric layer 21 on oxide storage medium layer 23 shown in Figure 3, thereby obtain structure shown in Figure 4, i.e. resistor-type memory.Wherein, top electrode 30 can pass through physical vapour deposition (PVD) (Physical Vapor Deposition is abbreviated as PVD) and upper electrode material is covered on the oxide storage medium layer 23 obtains.The material of top electrode 30 can but be not limited only to Ta, Ti, TaN.In addition, deposition process is not limited to PVD.
Below in conjunction with Fig. 5 to Figure 16, with Cu as lower electrode material, illustrate with dual damascene process integrated with Cu copper-connection backend process compatibility
xThe preparation method of O (wherein, 1＜x≤2) based resistance memory.
Fig. 5 is according to Cu of the present invention
xThe preparation method's of O based resistance memory flow chart, Fig. 6 to Figure 16 are the Cus integrated with dual damascene process
xThe STRUCTURE DECOMPOSITION figure of preparation method's process of O based resistance memory.
As shown in Figure 5, comprise according to the preparation method of the CuxO based resistance memory of of the present invention and copper-connection backend process compatibility: step S21 is formed at copper lead-in wire in the groove as Cu in Damascus copper wiring technique with routine
xThe bottom electrode of O based resistance memory; Step S22 forms blanket dielectric layer above the copper lead-in wire; Step S23, in blanket dielectric layer with the follow-up Cu that will form
xThe position of O base storage medium layer correspondence makes hole; Step S24 is that mask carries out the oxonium ion injection to the copper lead-in wire that is positioned at the hole bottom with the blanket dielectric layer, forms Cu
xO base storage medium layer; Step S25 is to Cu
xO base storage medium layer is carried out annealing in process; And step S26, at Cu
xForm top electrode on the O base storage medium layer.
In step S21 (simultaneously with reference to Fig. 6), Cu
xO based resistance memory and dual damascene process are integrated, Cu
xO base storage medium layer will be formed on the bottom, copper lead-in wire of the copper embolism of explanation after a while.As shown in Figure 6, the step that forms the copper lead-in wire in conventional Damascus copper wiring technique can comprise: metal medium (Premetal Dielectric before forming on the MOS device, be abbreviated as PMD) layer 100, pmd layer 100 can be silica PSG dielectric materials such as (Phospho Silicate Glass) of mixing phosphorus; Form tungsten plug 903 in pmd layer 100, tungsten plug 903 is used to connect ground floor copper lead-in wire and metal-oxide-semiconductor source electrode or drain electrode; On pmd layer 100, form first etch stop layer, 201, the first etch stop layers 201 and can be Si
3N4, SiON, SiCN; On first etch stop layer 201, form first interlayer dielectric layer, 101, the first interlayer dielectric layers 101 and can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; Form the copper lead-in wire in first interlayer dielectric layer, 101 grooves, wherein 501 do not need figure oxidation formation Cu for the part of ground floor copper lead-in wire and the upper epidermis of this part
xO base storage medium layer, 502 for another part of ground floor copper lead-in wire also will be as Cu
xThe bottom electrode of O based resistance memory and the upper epidermis of this part need the figure oxidation to form Cu
xO base storage medium layer; Between the ground floor copper lead-in wire and first interlayer dielectric layer 101, be provided with first diffusion impervious layer 401 and 402 that prevents the copper diffusion, first diffusion impervious layer 401 and 402 can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, perhaps can be other electric conducting material that plays same purpose, as TiSiN, WN
x, WN
xC
y, Ru, TiZr/TiZrN etc.
In step S22 (simultaneously with reference to Fig. 7), but using plasma chemical vapour deposition technique (Plasma Enhanced Chemical Vapor Deposition, be abbreviated as PECVD) deposition forms the first block layer 202a above the part 501 and 502 of ground floor copper lead-in wire, at this moment, the first block layer 202a is the blanket dielectric layer in the corresponding diagram 5.In this embodiment, the first block layer 202a can be Si
3N
4, dielectric material such as SiON, the thickness of the first block layer 202a can be 20～2000nm, preferred 20～100nm.
In step S23 (simultaneously with reference to Fig. 8), by photoetching, be etched among the first block layer 202a and the follow-up Cu that will form
xA first block layer 202a opened in the position of O base storage medium layer correspondence, forms hole 300, thinks that step 24 is prepared (promptly the part 502 of ground floor copper lead-in wire to be carried out oxonium ion and inject, generate Cu
xO base storage medium layer 700), the size of hole 300 is the size of memory cell.In actual etching process, the cineration technics when avoiding removing photoresist can adopt secondarily etched technology usually with the copper oxidation that goes between.The concrete grammar of secondarily etched technology is: make the hole figure earlier by lithography; dry etching etches away a part with hole place block layer then; remove photoresist with cineration technics afterwards; this moment, block layer in hole place was by all etching is intact; copper below having protected goes between and does not make it oxidation; pass through secondarily etchedly at last, hole is opened fully.For example, when just having deposited, the first block layer 202a is 100nm, through the etching first time, hole opened 50nm, removes photoresist then and carries out the etching second time, and hole is opened fully, and this moment first, block layer 202a thickness became 50nm.
In step S24 (simultaneously with reference to Fig. 9), the part 502 that the ground floor copper that exposes in the hole 300 goes between is carried out the oxonium ion injection, copper and oxonium ion generation chemical reaction in the part 502 of ground floor copper lead-in wire generate Cu
xO base storage medium layer 700, wherein 1＜x≤2.Wherein the oxonium ion injection condition is: the oxonium ion implantation dosage is 1 * 10
8/ cm
2～1 * 10
18/ cm
2, be preferably 1 * 10
10/ cm
2～1 * 10
16/ cm
2It is 500e～500ke that oxonium ion injects energy, is preferably 5ke～100ke; Implantation temperature is lower than the heating-up temperature that plasma oxidation or thermal oxidation method produce the oxide storage medium layer, and implantation temperature is preferably below 200 ℃, is preferably room temperature～100 ℃ again, and more preferably room temperature～50 ℃ most preferably are room temperature; Injection pressure is vacuum (promptly being lower than normal pressure), preferably less than 2 * 10
-3Pa is more preferably less than 1 * 10
-3Pa.When oxonium ion injected, the first block layer 202a played mask layer simultaneously.The Cu that forms
xO storage medium layer 700 thickness ranges are 0.5nm～500nm, preferred 5nm～100nm.
In step S25, to Cu
xThe condition that O base storage medium layer is carried out annealing in process is: annealing temperature is 50 ℃～800 ℃, preferred 200 ℃～500 ℃, and more preferably 300 ℃～450 ℃; Annealing time is 1s～1h, is preferably 0.5min～5min; Annealing pressure is vacuum or normal pressure; Annealing atmosphere is N
2, or inert gas.
In step S26 (simultaneously with reference to Figure 10 and Figure 11), by modes such as reactive sputtering, PECVD, thermal evaporations, at Cu
xDeposition upper electrode material layer 800 on the O base storage medium layer 700, upper electrode material layer 800 can be selected from TaN, Ta, TiN, Ti, Cu, Al, Ni, Co; On upper electrode material layer 800, go out the top electrode figure, pass through dry method or wet etching more then, realize graphical treatment, form top electrode 801 upper electrode material layer 800 by lithographic definition.
So far, form the integrated Cu of CMOS logical device that forms with front-end process
xThe O based resistance memory, Cu
xThe O based resistance memory comprises bottom electrode 502, Cu
xO base storage medium layer 700 and top electrode 801.
Next with reference to Figure 12 to Figure 16, the rear end preparation process that forms second layer copper lead-in wire on aforementioned basis is described.
With reference to Figure 12, on top electrode 801, deposit the second block layer 202b, second interlayer dielectric layer 102, second etching barrier layer 203, the 3rd interlayer dielectric layer 103 and anti-reflecting layer 204 successively.Wherein, the second block layer 202b plays the effect that stops top electrode 801 diffusions, and the second block layer 202b can be dielectric materials such as SiN, SiON; Second interlayer dielectric layer 102 can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; Second etching barrier layer 203 can be Si
3N
4, materials such as SiON, SiCN; The 3rd interlayer dielectric layer 103 can be SiO
2Or mix the SiO of F or C
2Deng the low k dielectric material; Anti-reflecting layer 204 can be materials such as SiON.
With reference to Figure 13, pass through chemical wet etching, at the first block layer 202a, the second block layer 202b, second inter-level dielectric 102, second etching barrier layer 203, the 3rd interlayer dielectric layer 103, and the position of the part 501 of corresponding ground floor copper lead-in wire is formed for first groove 601 of second layer copper lead-in wire and exposes the top layer of the part 501 of ground floor copper trace layer in the anti-reflecting layer 204, at second a block layer 202b, second inter-level dielectric 102, second etching barrier layer 203, the 3rd interlayer dielectric layer 103, and the position of corresponding top electrode 801 is formed for second groove 602 of second layer copper lead-in wire and exposes the top layer of top electrode 801 in the anti-reflecting layer 204.
With reference to Figure 14, by first groove 601 and second groove 602, earlier carry out pre-sputter by the Ar ion, the top layer of the part 501 of removal ground floor copper lead-in wire and the natural oxidizing layer on memory cell top electrode 801 surfaces, to strengthen itself and the adhesive capacity of subsequently diffusion impervious layer (i.e. second diffusion impervious layer 403 and 404), then by chemical vapour deposition (CVD) (Chemical Vapor Deposition, be abbreviated as CVD) or PVD deposit second diffusion impervious layer 403 and 404, with the diffusion of the second layer copper that prevents to form later lead-in wire.Second diffusion impervious layer 403 and 404 can be TaN, Ta/TaN composite bed or Ti/TiN composite bed, or other plays the electric conducting material of same purpose, as TiSiN, WN
x, WN
xC
y, Ru, TiZr/TiZrN etc.
With reference to Figure 15, in first groove 601 and second groove 602, the PVD of elder generation growth inculating crystal layer Cu, adopt electrochemical deposition (Electro-Chemical Precipitation afterwards, be abbreviated as ECP) make the copper growth along 111 preferred orientations, thus reducing copper connecting lines resistivity, ECP growth Cu fills up and covering groove then, 200 ℃ again～400 ℃ annealing are to increase the crystal grain of copper; Thereby form second layer copper lead-in wire 500.
With reference to Figure 16, adopt smooth (the Chemical Mechanical Platen of chemical machinery, be abbreviated as CMP) the unnecessary second layer copper lead-in wire of removal, thereby form copper embolism 503 and 504 by first groove 601 and second groove 602 in second interlayer dielectric layer 102, wherein 503 is that its upper epidermis does not need oxidation to form Cu
xThe copper embolism of O base storage medium, 504 need oxidation formation Cu for its upper epidermis
xThe copper embolism of O base storage medium.
So far, form and the integrated Cu of dual damascene process
xThe O based resistance memory.
By mode and the employing implantation temperature formation oxide storage medium layer lower that adopts oxonium ion to inject, can effectively avoid producing between oxide storage medium layer and the bottom electrode matrix cavity than the heating-up temperature of plasma oxidation or thermal oxidation method generation oxide storage medium layer.With Cu is example, adopts thermal oxidation method or plasma oxidation to generate Cu
xDuring the O storage medium layer, because Cu
xThe easy diffusivity of mismatch in coefficient of thermal expansion and Cu atom between O and the Cu matrix, under the high temperature of plasma oxidation or thermal oxidation method, the Cu atom is easily along Cu
xO crystal boundary place diffuses out, and then at Cu
xThe cavity of generation at the interface between O dielectric layer and the Cu matrix.And with oxonium ion injection method growth Cu
xThe O dielectric layer can form Cu under room temperature or lower temperature
xThe O medium has effectively avoided high temperature down because the empty problem that mismatch in coefficient of thermal expansion and Cu diffusion cause.
The mode of injecting by oxonium ion forms the oxide storage medium layer, can effectively eliminate the influence of bottom electrode crystal grain to oxide storage medium layer growth, improves the homogeneity of oxide storage medium layer.When adopting thermal oxidation or plasma oxidation method grow oxide storage medium layer, because oxygen atom (ion) diffusion along crystal boundary toward metal inside easily, at crystal boundary place grown oxide thicker than on the crystal grain, cause the oxide storage medium layer uniformity that generates relatively poor.And when preparing the oxide storage medium layer with the oxonium ion injection method, energy and dosage that the degree of depth that oxonium ion injects and concentration depend primarily on injection have reduced the influence of polycrystalline bottom electrode matrix to oxidation rate.
By control to injection energy and dosage, can realize the accurate control that the O element distributes in oxide, thereby make the distribution of oxygen vacancy concentration in medium precisely controlled, the electric activation of resistor-type memory is appreciated that the forming process that becomes the oxygen space channels, the distribution of injecting artificial control O room by the O ion, effectively the activation voltage of abatement device, improve device yield, reduce the discreteness of device parameters.
Adopt the resistor-type memory of this method preparation to have low, effective, the easy and integrated advantage of CMOS technology of cost of manufacture.
The invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, in order to know the thickness in amplification layer and zone, but should not be considered to the proportionate relationship that strictness has reflected physical dimension as schematic diagram.
Accompanying drawing only is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as preparation.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
Claims (10)
1. the preparation method of a resistor-type memory is characterized in that, comprises step:
To the bottom electrode composition, described bottom electrode is carried out oxonium ion inject, so that bottom electrode forms the oxide storage medium layer;
Described oxide storage medium layer is carried out annealing in process; And
Composition and form top electrode on described oxide storage medium layer.
2. the preparation method of resistor-type memory according to claim 1, it is characterized in that, the bottom electrode composition is included in blanket dielectric layer is set on the described bottom electrode and in described blanket dielectric layer, offers the perforate that described bottom electrode is exposed, described bottom electrode is carried out oxonium ion inject and undertaken by described perforate.
3. the preparation method of resistor-type memory according to claim 1, it is characterized in that, described bottom electrode is carried out implantation temperature that oxonium ion injects is lower than the heating-up temperature that plasma oxidation or thermal oxidation method produce the oxide storage medium layer, implantation temperature is preferably below 200 ℃, be preferably room temperature～100 ℃ again, more preferably room temperature～50 ℃, most preferably be room temperature.
4. the preparation method of resistor-type memory according to claim 1 is characterized in that, described bottom electrode is selected from Ta, TaN, Cu, W, Ti, TiN, Zr, Ni, Co, Ce, In, Fe, Cr, Mn, Al, Ag, Hf, Mg, V, Sn.
5. the preparation method of resistor-type memory according to claim 4 is characterized in that, described bottom electrode is the copper lead-in wire that is formed in the copper wiring technique of Damascus in the groove, and described oxide storage medium layer is Cu
xO base storage medium layer, wherein 1＜x≤2.
6. the preparation method of resistor-type memory according to claim 5 is characterized in that, for described copper lead-in wire, in the step of carrying out oxonium ion injection formation oxide storage medium layer, the implantation dosage of oxonium ion is 1 * 10
8/ cm
2～1 * 10
18/ cm
2, more preferably 1 * 10
10/ cm
2～1 * 10
16/ cm
2
7. the preparation method of resistor-type memory according to claim 5, it is characterized in that, for described copper lead-in wire, inject the step that forms the oxide storage medium layer carrying out oxonium ion, it is 500e～500ke, 5ke～100ke more preferably that oxonium ion injects energy.
8. the preparation method of resistor-type memory according to claim 5 is characterized in that, for described copper lead-in wire, injects the step that forms the oxide storage medium layer carrying out oxonium ion, and injection pressure is vacuum, preferably less than 2 * 10
-3Pa, be more preferably less than 1 * 10
-3Pa.
9. the preparation method of resistor-type memory according to claim 5, it is characterized in that, for described copper lead-in wire, when described oxide storage medium layer was carried out annealing in process, annealing temperature was 50 ℃～800 ℃, preferred 200 ℃～500 ℃, more preferably 300 ℃～450 ℃.
10. the preparation method of resistor-type memory according to claim 5 is characterized in that, for described copper lead-in wire, when described oxide storage medium layer was carried out annealing in process, annealing time was 1s～1h, be preferably 0.5min～5min.
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Cited By (2)
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| CN106463340A (en) * | 2015-01-05 | 2017-02-22 | 王士原 | Resistive random-access memory with implanted and radiated channels |
| WO2022105606A1 (en) * | 2020-11-19 | 2022-05-27 | International Business Machines Corporation | Resistive switching memory cell |
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| CN101068038A (en) * | 2006-05-04 | 2007-11-07 | 三星电子株式会社 | Variable resistance memory device with buffer layer at lower electrode |
| CN101232076A (en) * | 2008-01-17 | 2008-07-30 | 复旦大学 | Method for eliminating CuxO resistance memory formation voltage |
| US20080185572A1 (en) * | 2007-02-05 | 2008-08-07 | Tony Chiang | Methods for forming resistive switching memory elements |
| US20080219039A1 (en) * | 2007-03-05 | 2008-09-11 | Nitin Kumar | Nonvolatile memory elements with metal-deficient resistive-switching metal oxides |
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2011
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| CN101068038A (en) * | 2006-05-04 | 2007-11-07 | 三星电子株式会社 | Variable resistance memory device with buffer layer at lower electrode |
| US20080185572A1 (en) * | 2007-02-05 | 2008-08-07 | Tony Chiang | Methods for forming resistive switching memory elements |
| US7678607B2 (en) * | 2007-02-05 | 2010-03-16 | Intermolecular, Inc. | Methods for forming resistive switching memory elements |
| US20080219039A1 (en) * | 2007-03-05 | 2008-09-11 | Nitin Kumar | Nonvolatile memory elements with metal-deficient resistive-switching metal oxides |
| CN101232076A (en) * | 2008-01-17 | 2008-07-30 | 复旦大学 | Method for eliminating CuxO resistance memory formation voltage |
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| CN106463340A (en) * | 2015-01-05 | 2017-02-22 | 王士原 | Resistive random-access memory with implanted and radiated channels |
| WO2022105606A1 (en) * | 2020-11-19 | 2022-05-27 | International Business Machines Corporation | Resistive switching memory cell |
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