CN113517393B - Phase change memory device and method of forming the same - Google Patents

Phase change memory device and method of forming the same Download PDF

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Publication number
CN113517393B
CN113517393B CN202110307279.8A CN202110307279A CN113517393B CN 113517393 B CN113517393 B CN 113517393B CN 202110307279 A CN202110307279 A CN 202110307279A CN 113517393 B CN113517393 B CN 113517393B
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layer
phase change
change material
opening
etch
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CN113517393A (en
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李东颖
林毓超
余绍铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/992,210 external-priority patent/US11411180B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H10N70/8613—Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

The method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a Phase Change Material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is flush with or below a top surface of the dielectric layer; and forming a top electrode on the PCM layer. Embodiments of the present application relate to a phase change memory device and a method of forming the same.

Description

Phase change memory device and method of forming the same
Technical Field
Embodiments of the present application relate to a phase change memory device and a method of forming the same.
Background
Semiconductor memories are used in integrated circuits for electronic applications including, for example, radios, televisions, cell phones, and personal computing devices. One type of semiconductor memory is a Phase Change Random Access Memory (PCRAM) that involves storing values in a phase change material, such as a chalcogenide material. The phase change material may be switched between an amorphous phase (where the phase change material has a low resistivity) and a crystalline phase (where the phase change material has a high resistivity) to indicate a bit pattern. PCRAM cells typically include a Phase Change Material (PCM) element located between two electrodes.
Disclosure of Invention
Some embodiments of the present application provide a method of forming a phase change memory device, comprising: forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode comprising a barrier layer; forming a Phase Change Material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the phase change material layer is flush with or below the top surface of the dielectric layer; and forming a top electrode on the phase change material layer.
Other embodiments of the present application provide a method of forming a phase change memory device, comprising: depositing an inter-metal dielectric (IMD) layer over the first conductive feature; forming the inter-metal dielectric layer exposing the first conductive feature; forming a second conductive member in the opening; performing a first etch-back process to recess the second conductive feature into the opening; depositing a Phase Change Material (PCM) in the opening and over the second conductive member; performing a second etch-back process to remove an upper portion of the phase change material; and depositing a conductive material over the phase change material.
Still further embodiments of the present application provide a phase change memory device including: a metallization layer over the semiconductor substrate; an inter-metal dielectric (IMD) layer over the metallization layer; and a Phase Change Random Access Memory (PCRAM) cell, the phase change random access memory cell comprising: a bottom electrode in the intermetal dielectric layer and electrically connected to the metallization layer; a Phase Change Material (PCM) layer on the bottom electrode and within the inter-metal dielectric layer, wherein the inter-metal dielectric layer surrounds the phase change material layer, and wherein a top surface of the inter-metal dielectric layer is free of the phase change material layer; and a top electrode on the phase change material layer and on the top surface of the inter-metal dielectric layer.
Drawings
The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-5 illustrate cross-sectional views of intermediate stages in the formation of a Phase Change Random Access Memory (PCRAM) cell in accordance with some embodiments.
Fig. 6-8 illustrate cross-sectional views of intermediate stages in PCRAM cell formation, in accordance with some embodiments.
Fig. 9 illustrates a process flow of an electrode etch back process, according to some embodiments.
Fig. 10A-10D illustrate cross-sectional views of a bottom electrode of a PCRAM cell in accordance with some embodiments.
Fig. 11-14 illustrate cross-sectional views of intermediate stages in PCRAM cell formation, in accordance with some embodiments.
Fig. 15 and 16 illustrate cross-sectional views of intermediate stages in PCRAM cell formation, in accordance with some embodiments.
Fig. 17 schematically illustrates a perspective view of a PCRAM array in accordance with some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
According to some embodiments of the present disclosure, a Phase Change Random Access Memory (PCRAM) is formed to include a plurality of PCRAM cells, which may be arranged in an array. The PCRAM cell includes a bottom electrode, a Phase Change Material (PCM) layer on the bottom electrode, and a top electrode on the PCM layer. In some embodiments, the bottom electrode is formed by etching an opening in the dielectric layer, and then depositing a barrier layer material and a conductive material in the opening. An etch back process is performed to recess the barrier material and the conductive material into the opening, the remaining barrier material and conductive material forming a bottom electrode. For example, the etch back process may be an Atomic Layer Etch (ALE) process or the like, which may remove most or all of the barrier material from the sidewalls of the opening above the recessed bottom electrode. Removing the barrier material from the sidewalls of the opening may reduce the thermal leakage of the PCRAM cell. PCM is deposited on the bottom electrode and another etch back process is performed to remove excess PCM material, the remaining PCM forming a PCM layer. The etch back process may recess the PCM below the top surface of the dielectric layer. Then, a top electrode is formed on the PCM layer. By forming the PCM layer surrounded by the dielectric layer, the PCRAM layer may have improved thermal insulation, and thus the PCRAM layer may be heated more effectively during operation, which may improve the efficiency and performance of the PCRAM cell.
Fig. 1 to 8 and 11 to 16 are cross-sectional views showing the device region 12 of the wafer 10 in which PCRAM cells 60 are formed (see fig. 14 and 15). Fig. 5 to 8 and 11 to 14 show an enlarged portion 45 of the structure. Fig. 9 illustrates a process flow of the electrode etch back process 100, and fig. 10A through 10D illustrate an exemplary bottom electrode 50 formed using the electrode etch back process 100. Fig. 17 shows a schematic diagram of a PCRAM array 70 comprising a plurality of PCRAM cells 60.
Fig. 1 illustrates a cross-sectional view of a device region 12 of a wafer 10, according to some embodiments. The device region 12 is a different area of the wafer 10 that is singulated in subsequent steps to form a plurality of device dies 12, each device die including a PCRAM structure, such as PRCAM units 60 (see fig. 14-15) or a PCRAM array 70 including a plurality of PCRAM units 60 (see fig. 17). The wafer 10 includes a semiconductor substrate 20, which may be, for example, doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 20 may comprise other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInP and/or GaInAsP; or a combination thereof. Other substrates, such as multi-layer or gradient substrates, may also be used. The semiconductor substrate 20 has an active surface (e.g., the surface facing upward in fig. 1), sometimes referred to as the front side, and a passive surface (e.g., the surface facing downward in fig. 1), sometimes referred to as the back side.
Devices are formed at the active surface of the semiconductor substrate 20. The devices may include active devices and/or passive devices. For example, the devices may include transistors, diodes, capacitors, resistors, etc., and may also be processed according to an appropriate manufacturing process. For example, fig. 1 shows an access transistor 22 formed on a front surface of a semiconductor substrate 20 for accessing (or "selecting") a PCRAM cell 60 of a device die 12 (see fig. 16). According to some embodiments, the access transistor 22 includes a gate dielectric layer 25, a gate electrode 26, source/drain regions 24, source/drain contact plugs 30, and gate contact plugs 32. In some embodiments, source/drain regions 24 may extend to semiconductor substrate 20.
As shown in fig. 1, one or more inter-layer dielectric (ILD) layers 31 are formed on the semiconductor substrate 20, and conductive features such as contact plugs 30/32 are formed on the ILD layers 31 to electrically connect with the access transistors 22. For example, the contact plugs 30/32 may be formed of tungsten, cobalt, nickel, copper, silver, aluminum, or the like, or a combination thereof. ILD layer 31 may be made of any suitable dielectric material, such as an oxide, e.g., silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), etc.; nitrides, such as silicon nitride and the like; low k dielectric materials, or the like, or combinations thereof. The ILD layer may be formed by any suitable deposition process, such as spin-on, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), the like, or combinations thereof. The contact plugs 30/32 or other conductive features in the ILD layer 31 may be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.), or the like, or combinations thereof. In some embodiments, ILD layer 31 comprises one or more inter-metal dielectric (IMD) layers.
Still referring to fig. 1, according to some embodiments, an inter-metal dielectric (IMD) layer 33 and metal lines 34 are formed over ILD layer 31. IMD layer 33 may be made of any suitable dielectric material, for example, an oxide, such as silicon oxide, PSG, BSG, BPSG/USG, etc.; nitrides, such as silicon nitride and the like; etc., or a combination thereof. IMD layer 33 may be formed by any suitable deposition process, such as spin coating, PVD, CVD, the like, or combinations thereof. IMD layer 33 may be a layer formed of a low-k dielectric material having a k value less than about 3.0.
Metal lines 34 are formed in IMD layer 33 and electrically coupled to access transistors 22 (e.g., through contact plugs 30/32). In some embodiments, as described in more detail in fig. 17, some or all of the metal lines 34 may be used as Word Lines (WL) that are connected to columns of PCRAM cells 60 in the PCRAM array 70. According to some embodiments, the metal line 34 includes a diffusion barrier layer and a conductive material over the diffusion barrier layer. As an exemplary process of forming metal line 34, an opening (not shown) may be formed in IMD layer 33 using, for example, a suitable etching process. The openings expose underlying conductive features such as contact plugs 30/32. The diffusion barrier layer may be formed of tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, or the like, or a combination thereof, and may be formed in the opening by a deposition process, such as Atomic Layer Deposition (ALD), or the like. The conductive material may include copper, aluminum, tungsten, silver, or the like, or combinations thereof, and may be formed over the diffusion barrier in the opening using an electrochemical plating process, CVD, ALD, PVD, or the like, or combinations thereof. In an embodiment, the conductive material is copper and the diffusion barrier is a thin barrier layer that prevents copper diffusion to IMD layer 33. After forming the diffusion barrier and the conductive material, the excess diffusion barrier and conductive material may be removed, for example, by a planarization process, such as a Chemical Mechanical Polishing (CMP) process. The remaining diffusion barrier and conductive material form metal lines 34 in IMD layer 33. Other techniques may also be used to form the metal lines 34.
Fig. 2 illustrates the formation of a dielectric layer 36 and a metallization layer 40 over the metal lines 34 and electrically connected to the metal lines 34, according to some embodiments. The metallization layer 40 provides additional interconnects (e.g., interconnects between the metal lines 34, the access transistors 22, etc.). In some embodiments, dielectric layer 36 may be considered an IMD layer, and dielectric layer 36 may be formed of a dielectric layer material similar to the dielectric layer materials described above for IMD layer 33. Metallization layer 40 (e.g., metallization pattern) may include metal lines and vias formed in dielectric layer 36. The metallization layer 40 may be formed using a damascene process, such as a single damascene process, a dual damascene process, or the like. For example, the metallization layer 40 may be formed by: etching into the dielectric layer 36 to form an opening; filling the opening with a conductive material; and performing a planarization process, such as a CMP process or a polishing process, to remove the excess conductive material. In some embodiments, metallization layer 40 may be formed in a similar manner as metal lines 34, or may be formed using other suitable techniques. It will be appreciated that although one metallization layer 40 (including metal lines and underlying vias) is shown in fig. 2, in other embodiments, additional metallization layers may be formed in additional dielectric layers above dielectric layer 36. Alternatively, the subsequently formed PCRAM cell 60 (shown in fig. 14) may be formed directly on the metal line 34 without forming the metallization layer 40. In some embodiments, the metal lines 34 and/or the contact plugs 30/32 may also be considered part of the metallization layer. In some embodiments, the width W1 of the metal line region of the metallization layer 40 formed is in the range of about 100nm to about 300 nm.
Fig. 3-15 are various views of intermediate stages in the manufacture of PCRAM cell 60 of device die 12 (see fig. 15), according to some embodiments. Fig. 3 and 4 show the same cross-sectional views shown in fig. 1 and 2, fig. 5 to 8 and 10A to 10D and fig. 11 to 15 show an enlarged portion 45 of the structure shown in fig. 4.
Turning to fig. 3, in some embodiments, IMD layer 42 is formed over dielectric layer 36 and metallization layer 40. In some embodiments, an etch stop layer (not shown) is formed on dielectric layer 36 and metallization layer 40 prior to forming IMD layer 42. The etch stop layer may be formed of one or more layers of dielectric materials such as aluminum nitride, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, and the like, or combinations thereof. The etch stop layer may be formed by CVD, PVD, ALD, spin-on dielectric processes, or the like, or a combination thereof. In some embodiments, IMD layer 42 is formed from tetraethyl orthosilicate (TEOS) oxide (e.g., silicon oxide deposited using TEOS as a precursor, such as a CVD process). In some embodiments, IMD layer 42 may be formed using PSG, BSG, BPSG, USG, fluorosilicate glass (FSG), silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, siOCH, flowable oxide, porous oxide, or the like, or a combination thereof. For example, IMD layer 42 may also be formed of a low-k dielectric material having a k value less than about 3.0. In some embodiments, IMD layer 42 is formed to a thickness T1 in the range of about 60nm to about 1000 nm. Other thicknesses are also possible.
In fig. 4 and 5, openings 44 are patterned in IMD layer 42 according to some embodiments. Fig. 5 shows an enlarged portion 45 of the cross-sectional view shown in fig. 4. The opening 44 exposes the topmost metallization layer 40 such that the bottom electrode 50 of a PCRAM cell 60 subsequently formed in the opening 44 (see fig. 14) makes electrical connection with the metallization layer 40. In some embodiments where metallization layer 40 is not formed, IMD layer 42 is formed over metal lines 34 and openings 44 expose metal lines 34. The openings 44 may be formed using acceptable photolithography and etching techniques. For example, a mask layer (not shown) such as a hard mask layer or a photoresist layer (e.g., a single layer of photoresist, a triple layer of photoresist, etc.) may be formed and patterned over IMD layer 42. IMD layer 42 may be etched using the patterned mask layer as an etch mask to form openings 44.IMD layer 42 may be etched using an anisotropic etching process, such as a suitable dry etching process. One or more etching processes may be performed and openings 44 extend through the etch stop layer (if present) over metallization layer 40. After forming the openings 44, the remaining portions of the mask layer may be removed using, for example, an ashing process, an etching process, or other suitable process.
The opening 44 may have tapered sidewalls as shown in fig. 4-5, or the opening 44 may have substantially vertical sidewalls. In some embodiments, the width W2 of the formed opening 44 is in the range of about 40nm to about 80 nm. Other widths are also possible. In some embodiments, the upper width of the opening 44 is greater than the lower width of the opening 44, as shown in fig. 4-5. In other embodiments, the opening 44 has a substantially constant width (e.g., width W2). In some embodiments, the width W2 of the opening 44 may be less than or about equal to the width W1 of the underlying metallization layer 40. In some embodiments, the opening 44 has a width to height to width ratio (e.g., W2: T1 ratio) in the range of about 1:8 to about 1:15.
Fig. 6-10D illustrate the formation of the bottom electrode 50 of the PCRAM cell 60, according to some embodiments. In fig. 6, a barrier layer 46 and a conductive material 48 are deposited over IMD layer 42 and in opening 44, according to some embodiments. Barrier layer 46 may be conformally deposited on IMD layer 42, on the sidewalls of opening 44, and on metallization layer 40. In some embodiments, barrier layer 46 is formed from one or more conductive materials such as titanium, titanium nitride, tantalum nitride, cobalt, or the like, or combinations thereof. Barrier layer 46 may be formed using one or more suitable deposition processes, such as PVD, CVD, ALD, and the like. In some embodiments, barrier layer 46 is a tantalum nitride layer that is deposited using an ALD process or other suitable process. In some embodiments, the thickness of the barrier layer 46 formed within the opening 44 is in the range of about 20nm to 80 nm. Other thicknesses are also possible.
After the barrier layer 46 is deposited, a conductive material 48 is deposited over the barrier layer 46 to fill the opening 44. In some embodiments, the conductive material 48 is formed from one or more conductive materials such as titanium, titanium nitride, tantalum, aluminum, tungsten, platinum, nickel, chromium, ruthenium, and the like. The conductive material 48 may be deposited using CVD, PVD, ALD, electrochemical plating, electroless plating, or the like. In some embodiments, conductive material 48 is titanium nitride deposited using PVD.
In fig. 7, a planarization process is performed to remove excess barrier layer 46 and conductive material 48 from IMD layer 42, according to some embodiments. For example, the planarization process may include a CMP process or a mechanical polishing process. Planarization may level the top surfaces of IMD layer 42, barrier layer 46, and conductive material 48.
In fig. 8, an electrode etch back process is performed on barrier layer 46 and conductive material 48 to form bottom electrode 50, according to some embodiments. The electrode etch back process etches the barrier layer 46 and the conductive material 48 to recess the barrier layer 46 and the conductive material 48 into the opening 44. In some embodiments, an electrode etch back process may selectively etch the material of barrier layer 46 and the material of conductive material 48 over the material of IMD layer 42. In this manner, barrier layer 46 may be removed from the sidewalls of opening 44 without significantly etching the sidewalls of opening 44. Fig. 9 depicts an exemplary electrode etch-back process 100 in more detail. The area within opening 44 corresponding to the removed barrier layer 46 and conductive material 48 is labeled as recessed area 51 in fig. 8. After performing the electrode etch back process, the barrier layer 46 and the conductive material 48 remaining in the opening 44 form a bottom electrode 50 of the PCRAM cell 60 (see fig. 14). For example, an electrode etch back process may recess barrier layer 46 and conductive material 48 from the top surface of IMD layer 42 by depth D1, which forms recessed region 51 of depth D1. After performing the electrode etch back process, the remaining barrier layer 46 and conductive material 48 form a bottom electrode 50, having a thickness T2, located over the underlying metallization layer 40.
In some embodiments, the thickness T2 of the bottom electrode 50 may be in the range of about 10nm to about 30 nm. Other thicknesses are also possible. In some embodiments, thickness T2 of bottom electrode 50 may be between about 25% and about 50% of thickness T1 of IMD layer 42, although other ratios are possible. In some embodiments, the ratio of the thickness T2 to the depth D1 of the recessed region 51 (e.g., thickness T2: depth D1) may be between about 1:1 to about 1:3, although other ratios are possible. In some embodiments, the thickness T3 of the subsequently formed Phase Change Material (PCM) layer 54 (see fig. 12) is determined by the thickness T2 of the bottom electrode 50. In this way, by controlling the depth D1 of the electrode etch back process, the relative or absolute size of the bottom electrode 50 and the PCM layer 54 may be controlled, and thus the operating characteristics of the PCRAM cell 60 may be controlled. For example, during operation of PCRAM cell 60, the heating characteristics of bottom electrode 50 may be controlled by controlling thickness T2. In addition, fig. 8 shows bottom electrode 50 having a flat top surface, however in other embodiments, bottom electrode 50 may have a convex surface, a concave surface, an irregular surface, or a combination thereof, as described in more detail below with respect to fig. 10A-10D.
By forming bottom electrode 50 using the electrode back-etching process described herein, a subsequently formed PCM layer 54 (see fig. 12) may be defined within IMD layer 42, which may improve heat transfer efficiency, and thus, performance and power consumption, of PCRAM cell 60. In addition, because the barrier layer 46 is recessed, the electrode etch-back process removes at least some of the barrier layer 46 from the sidewalls of the opening 44. In this way, the excess barrier layer 46 within the opening 44 that is not part of the bottom electrode 50 may be removed. For example, the electrode etch back process may partially or completely remove the barrier layer 46 within the recessed region 51, which may expose sidewalls of the opening 44 within the recessed region 51. By removing the excess barrier layer 46 within the opening 44, electrical and/or thermal leakage due to the presence of the excess barrier layer 46 may be reduced, which may improve the electrical performance and heat transfer efficiency of the PCRAM cell 60.
Fig. 9 illustrates a process flow of an electrode etch back process 100 according to some embodiments. As shown in fig. 8, for example, an electrode etch back process 100 may be used to etch the barrier layer 46 and the conductive material 48 to form the bottom electrode 50. The electrode etch-back process 100 includes an etch pretreatment 101, an etch process 110, and an etch post treatment 131. In some embodiments, the etching process 110 is an ALE process or the like. In some embodiments, electrode etch-back process 100 selectively etches barrier layer 46 and conductive material 48 over IMD layer 42. The electrode etch-back process 100 is an example electrode etch-back process, and other process parameters, process gases, or etching techniques may be used.
Before the etching process 110 is performed, the pre-etch treatment 101 may be performed to remove metal oxide from a surface (e.g., the surface of the structure shown in fig. 7). For example, the etch pretreatment 101 may remove titanium oxide or tantalum oxide from the exposed surfaces of the barrier layer 46 or the conductive material 48. Removing metal oxide using the pre-etch process 101 may result in a more uniform etch during the etch process 100. After the etching pretreatment 101, purging may be performed to remove process gases, reaction products, and the like.
In some embodiments, the pre-etch process 101 includes a plasma process, such as a plasma etch. The plasma process may include flowing one or more process gases into a process chamber and igniting the one or more process gases into a plasma. For example, the etch pretreatment 101 may include a plasma process using one or more process gases, such as CH 4、Cl2, ar, etc., other gases, or combinations thereof. For example, in some embodiments, a mixture of CH 4、Cl2 and Ar may be used, where CH 4 is between about 3sccm and about 10sccm, cl 2 is between about 30sccm and about 100sccm, and/or Ar is between about 50sccm and about 100 sccm. Other mixtures are also possible. The plasma process may be performed using a plasma source power in the range of about 150W to about 400W and a bias power in the range of about 30W to about 60W. In some embodiments, no bias power is applied. The pre-etch process 101 may be performed using a pressure in the range of about 3mTorr to about 10mTorr, a process gas flow rate in the range of about 100sccm to about 250 sccm. Other process gases or process parameters are also possible.
In some embodiments, the etching process 110 includes a process gas soak 111 followed by one or more etching cycles 120. For example, during the process gas soak 111, the structure may be exposed to a process gas such as Cl 2 or other gases. In some embodiments, the process gas may flow at a flow rate in the range of about 100sccm to about 300sccm, although other flow rates are possible. In some embodiments, the process gas is not ignited into a plasma during the process gas soak 111. After the etching process 110, purging is performed to remove process gases, reaction products, and the like.
After the process gas soak 111, one or more etching cycles 120 are performed. In some embodiments, each etch cycle 120 includes a main etch step 121 and an overetch step 122. Each of the main etching step 121 and the overetch step 122 may include flowing one or more process gases into the process chamber and igniting the one or more process gases into a plasma. The main etch step 121 may include a plasma etch using one or more process gases such as Cl 2、BCl3, ar, he, etc., other gases, or combinations thereof. For example, in some embodiments, a mixture of Cl 2、BCl3, ar, and He may be used, where Cl 2 is between about 30% and about 70%, BCl 3 is between about 20% and about 60%, ar is between about 20% and about 50%, and/or He is between about 20% and about 50%. Other mixtures are also possible. The main etching step 121 may be performed using a plasma source power in a range of about 250W to about 400W, and the main etching step 121 may be performed using a bias power in a range of about 0W to about 30W. In some embodiments, the switching duty cycle of the bias power is between about 20% to about 80%, or the frequency is in the range of about 100Hz to about 1000 Hz. The main etch step 121 may be performed using a pressure in the range of about 3mTorr to about 10mTorr and a process gas flow rate in the range of about 300 seem to about 1000 seem. In some embodiments, the main etch step 121 may be performed continuously in a range of about 100 seconds to about 500 seconds. Other process gases or process parameters are also possible.
The overetch step 122 may include a plasma etch using one or more process gases such as Cl 2、BCl3, ar, he, etc., other gases, or combinations thereof. For example, in some embodiments, a mixture of Cl 2、BCl3, ar, and He may be used, where Cl 2 is between about 30% and about 70%, BCl 3 is between about 20% and about 60%, ar is between about 20% and about 50%, and/or He is between about 20% and about 50%. Other mixtures are also possible. In some embodiments, the mixture of process gases used in the overetch step 122 is the same as the mixture of process gases used in the main etch step 121. The overetch step 122 may be performed using a plasma source power in the range of about 150W to about 250W, and the overetch step 122 may be performed using a bias power in the range of about 0W to about 20W. In some embodiments, the switching duty cycle of the bias power is between about 20% to about 50%, or the frequency is in the range of about 100Hz to about 1000 Hz. In some embodiments, overetch step 122 is similar to main etch step 121, except that the bias power used in overetch step 122 is lower than the bias power used in main etch step 121. For example, the bias power of the overetch step 122 may be between about 10% and about 30% of the bias power used in the main etch step 121, although other percentages are also possible. The overetch step 122 may be performed using a pressure in the range of about 5mTorr to about 15mTorr and a process gas flow rate in the range of about 33sccm to about 1000 sccm. In some embodiments, the overetch step 122 may be performed continuously in a range of about 100 seconds to about 300 seconds. Other process gases or process parameters are also possible.
Similar to the ALE process, the electrode etch-back process 100 described herein may allow for a high degree of etch control. In some embodiments, the etch distance for each etch cycle 120 is in the range of about 1nm to 1.5nm, although other etch rates are possible. In some embodiments, the etch cycle 120 removes about one monolayer of the barrier layer 46 and/or the conductive material 48. The etching cycle 120 may be repeated any number of times until the desired amount of material is removed. In some embodiments, the etching process 110 includes performing the etching cycle 120 in a range of about 10 times to about 30 times, although the etching cycle 120 may be performed a different number of times in other embodiments. In this way, the electrode etch-back process 100 may allow improved control of the thickness T2 of the bottom electrode 50 and improved control of the thickness T3 of the PCM layer 54 (see fig. 12).
Turning to fig. 10A-10D, in some embodiments, the bottom electrode 50 is shown with a differently shaped top surface. In some embodiments, controlling the process gas during the etching cycle 120 may block the relative etching rates of the layer 46 and the conductive material 48 to control the shape of the top surface of the bottom electrode 50. In some embodiments, barrier layer 46 is tantalum nitride, conductive material 48 is titanium nitride, the flow rate of Cl 2 is controlled during etch cycle 120 to control the etch rate of barrier layer 46, and the flow rate of BCl 3 is controlled during etch cycle 120 to control the etch rate of conductive material 48.
Referring to fig. 10A, an example bottom electrode 50 is shown, similar to the bottom electrode 50 shown in fig. 8, with the top surfaces of the barrier layer 46 and the conductive material 48 being substantially horizontal. In some embodiments, by controlling the etching process 110, the bottom electrode 50 may be formed with a substantially horizontal surface of the barrier layer 46 and the conductive material 48 such that the etch rate of the barrier layer 46 is substantially the same as the etch rate of the conductive material 48. In some cases, the etch rate may be controlled by controlling the flow rate of the corresponding process gas during the etch process 110. For example, a similar ratio of barrier layer 46 and conductive material 48 may be etched at a Cl 2 flow rate to BCl 3 flow rate ratio of about 1:6. For example, the flow rate of CL 2 is about 30sccm and the flow rate of BCl 3 is about 180sccm. This is an illustrative example, and other ratios or flow rates may be used. In some cases, forming the barrier layer 46 and the conductive material 48 with substantially flush top surfaces may result in enhanced diffusion barrier of the barrier layer 46.
Referring to fig. 10B, an example bottom electrode 50 is shown, with the top surface of the conductive material 48 being concave, according to some embodiments. In some embodiments, the conductive material 48 having a concave surface may be formed by etching the conductive material 48, with an etch rate of the conductive material being greater than an etch rate of the barrier layer 46 during the etching process 110. For example, in some cases, the conductive material 48 may be etched at a Cl 2 flow rate to BCl 3 flow rate ratio of about 1:1 to 1:2, with the conductive material having an etch rate greater than the etch rate of the barrier layer 46. This is an illustrative example, and other ratios or flow rates may be used. In some cases, forming bottom electrode 50 with conductive material 48 having a concave top surface, for example, extending below the top surface of barrier layer 46 may result in enhanced diffusion barrier of barrier layer 46.
Fig. 10C illustrates an example bottom electrode 50, with the top surface of the conductive material 48 being convex and protruding above the top surface of the barrier layer 46, according to some embodiments. Fig. 10D illustrates an example bottom electrode 50, with the top surface of the barrier layer 46 being concave and extending below the top surface of the conductive material 48, according to some embodiments. In some embodiments, during the etching process 110, the convex conductive material 48 and/or the concave barrier layer 46 may be formed by etching the barrier layer 46, the etch rate of the barrier layer 46 being greater than the etch rate of the conductive material 48. For example, in some cases, the barrier layer 46 may be etched at a Cl 2 flow rate to BCl 3 flow rate ratio of about 1:1 to 2:1, with the etch rate of the barrier layer being greater than the etch rate of the conductive material 48. This is an illustrative example, and other ratios or flow rates may be used.
Returning to fig. 9, after the etching process 110 is completed, a post-etch process 131 may be performed. In some embodiments, post etch process 131 uses a process gas such as N2H2, or the like. In some embodiments, post etch treatment 131 may comprise a plasma process. The plasma process may be performed using a plasma source power in the range of about 200W to about 400W. The post etch treatment 131 may be performed using a pressure, a process temperature, or a process gas flow rate, the pressure being in the range of about 20mTorr to about 80mTorr, the process temperature being in the range of about 60 ℃ to about 120 ℃, the process gas flow rate being in the range of about 200sccm to about 1000 sccm. Other process gases or process parameters are also possible. After the post-etch treatment 131, a purge is performed to remove process gases, reaction products, and the like.
The electrode etch-back process 100 shown in fig. 9 is an example electrode etch-back process, and the electrode etch-back process may be different in other embodiments. Some of the steps and processes shown may be omitted or repeated, or may include other steps and processes described. For example, in other embodiments, the etch cycle 120 may include only one step (e.g., only the main etch step 121) or may include more than three steps, any of which may be similar to or different from the steps described for the electrode etch-back process 100. Other variations of the electrode etch back process 100 are also possible.
Referring to fig. 11, according to some embodiments, a PCM53 is formed in the opening 44 and covers the bottom electrode 50. As shown in fig. 11, PCM53 may be deposited to fill recessed region 51, and PCMs 53 may also cover the surface of IMD layer 42. In some embodiments, PCM53 may be partially deposited to fill recessed region 51. In some embodiments, PCM53 is a chalcogenide material such as GeSbTe (GST) or GeSbTeX, where X is a material such as Ag, sn, in, si, N, or the like. Other materials are also possible. PCM53 may be formed using a suitable deposition process such as PVD, CVD, plasma Enhanced CVD (PECVD), ALD, and the like.
In fig. 12, a PCM etch back process is performed to etch the PCM53 and form a PCM layer 54, according to some embodiments. PCM53 is removed from the top surface of IMD layer 42 by a PCM etch back process, with the remaining PCM53 forming PCM layer 54 of PCRAM cell 60 (see fig. 14). As shown in fig. 12, the PCM etch back process may form PCM layer 54 having a top surface substantially horizontal to the top surface of IMD layer 42 or the top surface of PCM layer 54 may be recessed from the top surface of IMD layer 42. In some embodiments, the top surface of PCM layer 54 may be recessed from the top surface of IMD layer 42 by a depth D2, with depth D2 being in the range of about 40nm to about 60 nm. Other distances are also possible. Recessing PCM layer 54 into the top surface of IMD layer 42 makes PCM layer 54 more limited to IMD layer 42, which may improve heat transfer efficiency and operation of PCRAM cell 60. Thus, a greater depth D2 may result in an enhanced confinement of the PCM layer 54. In some embodiments, a planarization process, such as a CMP process, may be performed before the PCM etch-back process is performed. The PCM layer 54 may be formed with a flat top surface, a concave top surface, a convex top surface, an irregular top surface, etc.
In some embodiments, the PCM etch-back process includes a plasma process, such as a plasma etch. The plasma process may include flowing one or more process gases into a process chamber and igniting the one or more process gases into a plasma. For example, the PCM etch back process may include a plasma process using one or more process gases, such as HBr, ar, he, or the like, other gases, or a combination thereof. For example, in some embodiments, a mixture of HBr, ar, and He may be used, where HBr is between about 20% to about 40%, ar is between about 30% to about 50%, and/or He is between about 10% to about 20%. Other mixtures are also possible. The plasma process may be performed using a plasma source power in the range of about 100W to about 400W or a bias power in the range of about 100W to about 200W. In some embodiments, no bias power is used. The PCM etch back process may be performed using a pressure, a process temperature, or a process gas flow rate, the pressure being in the range of about 3mTorr to about 10mTorr, the process temperature being in the range of about 40 ℃ to about 70 ℃, the process gas flow rate being in the range of about 100sccm to about 300 sccm. Other process gases or process parameters are also possible.
In some embodiments, forming the PCM layer 54 described herein in the opening 44 may result in improved sidewall quality of the PCM layer 54. For example, in some cases, forming the PCM layer using an etching process (e.g., as part of a photolithographic patterning) may cause the PCM layer to be damaged during the etching process. By forming the PCM layer 54 without etching the sidewalls of the PCM layer 54, etching damage to the sidewalls of the PCM layer 54 may be avoided. Thus, the formed PCM layer 54 may improve sidewall quality, which may reduce defects in the PCM layer 54, reduce electrical or thermal leakage of PCMRAM cells 60, and increase power of PCRAM cells 60 during operation.
As shown in fig. 12, the PCM etch-back process removes PCM53 from the top surface of IMD layer 42 and forms PCM layer 54 having a substantially uniform thickness. In some embodiments, the thickness T3 of the PCM layer 54 may be in the range of about 10nm to about 30nm, although other thicknesses are possible. In some embodiments, thickness T3 may be between about 30% and about 70% of thickness T1 of IMD layer 42, or thickness T3 may be between about 30% and about 100% of depth T1 of recessed region 51. In some embodiments, the ratio of the thickness T2 of the bottom electrode 50 to the thickness T3 of the PCM layer 54 is between about 1:1 to about 1:3. Other distances, percentages, or ratios are also possible. In this way, the absolute or relative thickness of the bottom electrode 50 and the PCM layer 54 may be controlled to achieve certain characteristics, such as size, resistance, power consumption, thermal efficiency, etc.
In fig. 13, top electrode material 55 is deposited over IMD layer 42 and covers PCM layer 54, according to some embodiments. As shown in fig. 13, top electrode material 55 extends below the top surface of IMD layer 42 to contact PCM layer 54. In some embodiments, top electrode material 55 includes a barrier layer and a conductive material over the barrier layer, which is not separately depicted in this figure. The barrier layer may be similar to barrier layer 46 described in fig. 6, or may be formed in a similar manner. For example, the barrier layer of top electrode material 55 may include tantalum nitride conformally deposited over IMD layer 42 and PCM layer 54, although other materials are possible. After depositing the barrier layer of top electrode material 55, a conductive material is deposited over the barrier layer. The conductive material may be similar to conductive material 48 described in fig. 6, or may be formed in a similar manner. For example, the conductive material of top electrode material 55 may include titanium nitride deposited on the barrier layer, although other materials are possible. In some embodiments, a planarization process (e.g., a CMP or polishing process) is performed on the top electrode material after deposition. In some embodiments, top electrode material 55 may be formed on top of IMD layer 42 at a thickness T4 in the range of about 20nm to about 50nm, although other thicknesses are possible.
Turning to fig. 14, according to some embodiments, top electrode material 55 is patterned to form top electrode 56 of PCRAM cell 60. Top electrode material 55 may be patterned using acceptable photolithography and etching techniques. For example, a mask layer (not shown), such as a hard mask layer or photoresist layer (e.g., a single layer of photoresist, a triple layer of photoresist, etc.), may be formed and patterned over top electrode material 55. The top electrode material 55 may be etched as an etched film using a patterned mask layer, with the remainder of the top electrode material 55 forming the top electrode 56. The top electrode material 55 may be etched using an anisotropic etching process, such as a suitable dry etching process. After forming the top electrode 56, the remaining portion of the mask layer may be removed, for example, by an ashing process, an etching process, or other suitable process. In this way, a PCRAM cell 60 including the bottom electrode 50, PCM layer 54, and top electrode 56 may be formed. In some embodiments, sides of PCM layer 54 are surrounded by IMD layer 42, and the bottom and top of PCM layer 54 are covered by bottom electrode 50 and top electrode 56, respectively.
As shown in fig. 14, top electrode 56 may extend above the top surface of IMD layer 42 and have a thickness T4 above the top surface of IMD layer 42. In some embodiments, a portion of top electrode 56 may extend below a top surface of IMD layer 42 to contact PCM layer 54. Thus, the portion of the top electrode 56 above the PCM layer 54 may have a thickness greater than the thickness T4. In some embodiments, the top electrode 56 may have a width W3, the width W3 being in the range of about 10nm to about 30 nm. The width W3 of the top electrode may be greater than, about equal to, or less than the width W1 of the underlying metallization layer 40.
Turning to fig. 15, a cross-sectional view of the device region 12 of the wafer 10 is shown, in accordance with some embodiments. The cross-sectional view shown in fig. 15 is similar to the cross-sectional view shown in fig. 1-4, except that a PCRAM cell 60 as described in fig. 5-14 is formed. As shown in fig. 15, PCRAM cell 60 is connected to metallization layer 40 and also to access transistor 22 or other devices formed in semiconductor substrate 20.
In fig. 16, according to some embodiments. IMD layer 62 is formed over IMD layer 42 and top electrode 56, and metallization layer 64 is formed in IMD layer 62. In some embodiments, as described in more detail below in fig. 17, some or all of the metallization layer 64 may function as Bit Lines (BL) that are connected to rows of PCRAM cells 60 in the PCRAM array 70. In some embodiments, an etch stop layer (not shown) is deposited over IMD layer 42 and top electrode 56 prior to forming IMD layer 62. IMD layer 62 may be formed of a similar dielectric material as previously described for IMD layer 42, dielectric layer 36, or IMD layer 33, or may be formed in a similar manner. Metallization layer 64 may include metal lines and vias formed in IMD layer 62. Metallization layer 64 may be formed using a damascene process, such as a single damascene process, a dual damascene process, and the like. For example, the metallization layer 64 may be formed by: to IMD layer 62 to form via openings (for vias) and trenches (for metal lines), the via openings and trenches are filled with a conductive material, and a planarization process, such as a CMP process or a grinding process, is performed to remove the excess conductive material. In some embodiments, metallization layer 64 may be formed in a similar manner as metal lines 34 or metallization layer 40, or may be formed using other suitable techniques. It will be appreciated that although one metallization layer 64 (including metal lines and underlying vias) is depicted in fig. 16, additional metallization layers may be formed in additional IMD layers above IMD layer 62. In a subsequent process, features are formed overlying metallization layer 64 and IMD layer 62 to form wafer 10 and device die 12. A separation process may be performed to separate the device regions 12 of the wafer 10 into individual device dies 12.
Fig. 17 schematically illustrates a perspective view of a PCRAM array 70 including PCRAM cells 60 arranged in an array, according to some embodiments. In the illustrated embodiment, WL is electrically connected to the bottom electrode 50 of each column of PCRAM cells 60 in PCRAM array 70. Each column of PCRAM array 70 has an associated word line, with PCRAM cells 60 in the column being connected to the word line of the column. For example, the word line may be a metal line 34 that is connected to the access transistor 22. BL are connected to top electrodes 56 of each row of PCRAM cells 60 in PCRAM array 70. Each row of PCRAM array 70 has an associated bit line with which PCRAM cell 60 within the row is connected. For example, the bit lines may be metal lines and vias of metallization layer 64. Some components, such as access transistor 22, metallization layer 40, etc., are not shown in fig. 17. Each PCRAM cell 60 of PCRAM array 70 may be selected from a suitable combination of word lines and bit lines. For example, a particular PCRAM cell 60 may be selected by accessing a single word line connected to the PCRAM cell 60 and accessing a single bit line connected to the PCRAM cell 60. Other configurations of bit lines, word lines, or PCRAM cells are also possible.
The resistance of PCM layer 54 of each PCRAM cell 60 is programmable and may vary between a high resistance state and a low resistance state, which may correspond to two states of a binary code. As current passes through PCRAM cell 60, PCRAM cell 60 may be controlled by bottom electrode 50 and/or top electrode 56 to change between a high resistance state and a low resistance state (e.g., the phase of PCM layer 54 may be changed) under heating of PCM layer 54. In this way, the resistance of its PCM layer 54 may be programmed using its corresponding access transistor 22 to write a value into the PCRAM cell 60, or the value may be read from the PCRAM cell 60 by measuring the resistance of its PCM layer 54 through its corresponding access transistor 22. The PCRAM cell 60 described herein includes the PCM layer 54 fully bounded by sidewalls that are substantially free of the barrier layer 46, which may improve heating control and efficiency or reduce power consumption during PCRAM cell 60 programming.
Embodiments may realize advantages. PCRAM cells may be formed using the techniques herein, with the sidewalls of the PCM layer completely confined in the dielectric layer. For example, a PCM layer may be formed that does not extend over the top surface of the dielectric layer. This may result in improved thermal confinement and heat transfer efficiency, allowing PCRAM cells to be programmed with smaller voltages and/or currents. For example, by forming a PCM layer that is bounded by a dielectric layer, heating of the PCM layer during programming may be better localized to the center of the PCM layer. Thus, the phase change of the PCM layer may diffuse from the center thereof, which may reduce the boundary effect, since the bottom electrode and/or the top electrode may reduce the efficiency. In addition, the techniques described herein enable removal of electrode barrier material prior to formation of the PCM layer. The barrier layer material on or near the PCM layer may cause thermal or electrical leakage, and thus, removal of the barrier layer material may reduce thermal or electrical leakage within the PCRAM cell. Thus, the techniques described herein result in improved energy efficiency of PCRAM arrays. In addition, the techniques described herein may form PCRAM cells without etching sidewalls of the PCM layer, which may reduce or eliminate damage to the PCM layer caused by etching or defects formed in the PCM layer caused by etching.
In some embodiments, a method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a PCM within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below a top surface of the dielectric layer; and forming a top electrode on the PCM layer. In one embodiment, the sidewalls of the PCM layer are free of barrier layers. In one embodiment, forming the bottom electrode includes depositing a barrier layer in the opening; depositing a conductive material on the barrier layer; and depositing a barrier layer and a conductive material, wherein the etching leaves the sidewalls of the opening treated. In one embodiment, after etching the barrier layer and the conductive material, a top surface of the conductive material protrudes. In one embodiment, after etching the barrier layer and the conductive material, a top surface of the barrier layer is flush with a top surface of the conductive material. In one embodiment, forming the PCM layer includes depositing a phase change material over the bottom electrode and the dielectric layer; and etching the phase change material to remove the phase change material from the top surface of the dielectric layer. In one embodiment, the thickness of the bottom electrode is between about 25% and about 50% of the thickness of the dielectric layer. In one embodiment, the thickness of the PCM layer is between about 30% to about 70% of the thickness of the dielectric layer.
In some embodiments, a method includes depositing an inter-metal dielectric (IMD) layer over a first conductive feature; forming an opening in the IMD layer exposing the first conductive feature; forming a second conductive member in the opening; performing a first etch-back process to recess the second conductive feature into the opening; depositing PCM in the opening and over the second conductive member; performing a second etch back process to remove an upper portion of the PCM; and depositing a conductive material on the PCM. In one embodiment, forming the second conductive feature includes depositing a tantalum nitride layer and depositing a titanium nitride layer over the tantalum nitride layer. In one embodiment, the first etch back process is an ALE process. In one embodiment, the first etch-back process includes flowing a first process gas into the process chamber and performing a plurality of etching cycles, wherein each etching cycle includes flowing a second process gas into the process chamber; igniting the second process gas into a plasma while using the first bias voltage; and igniting the second process gas into a plasma while using a second bias voltage lower than the first bias voltage. In one embodiment, the second process gas includes Cl 2、BCl3, ar, and/or He. In one embodiment, the first etch-back process includes flowing a third process gas into the process chamber before performing the plurality of etch cycles; and igniting the third process gas into a plasma. In one embodiment, the second etch-back process includes flowing a fourth process gas into the process chamber and igniting the fourth process gas into a plasma.
In some embodiments, a device includes a conductive metallization layer over a semiconductor substrate; an IMD layer over the metallization layer; and a PCRAM cell including a bottom electrode in the IMD layer, the bottom electrode electrically connected to the metallization layer; a PCM layer on the bottom electrode and within the IMD layer, wherein the PCM layer is surrounded by the IMD layer, and wherein a top surface of the IMD layer is free of the PCM layer; and a top electrode on the PCM layer and on a top surface of the IMD layer. In one embodiment, the top electrode extends below the top surface of the IMD layer to contact the PCM layer. In one embodiment, the sidewalls of the PCM layer are in physical contact with the IMD layer. In one embodiment, the PCM layer includes GeSbTe (GST). In one embodiment, the PCM layer is uniformly thick.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A method of forming a phase change memory device, comprising:
Forming a dielectric layer over a substrate, the dielectric layer having a top surface;
Etching an opening in the dielectric layer, the opening having tapered sidewalls;
forming a bottom electrode within the opening, the bottom electrode comprising a barrier layer;
Forming a phase change material layer within the opening and on the bottom electrode, wherein a sidewall of the barrier layer and a sidewall of the phase change material layer are both in direct contact with the tapered sidewall of the opening, and a top surface of the phase change material layer is flush with or below the top surface of the dielectric layer; and
A top electrode is formed on the phase change material layer.
2. The method of claim 1, wherein sidewalls of the phase change material layer are free of the barrier layer.
3. The method of claim 1, wherein forming the bottom electrode comprises:
Depositing the barrier layer in the opening;
depositing a conductive material on the barrier layer; and
The barrier layer and the conductive material are etched, wherein the etching exposes the tapered sidewalls of the opening.
4. The method of claim 3, wherein a top surface of the conductive material protrudes after etching the barrier layer and the conductive material.
5. The method of claim 3, wherein after etching the barrier layer and the conductive material, a top surface of the barrier layer is flush with a top surface of the conductive material.
6. The method of claim 1, wherein forming the phase change material layer comprises:
depositing a phase change material over the bottom electrode and the dielectric layer; and
The phase change material is etched to remove the phase change material from the top surface of the dielectric layer.
7. The method of claim 1, wherein the bottom electrode has a thickness between 25% and 50% of the thickness of the dielectric layer.
8. The method of claim 1, wherein a thickness of the phase change material layer is between 30% and 70% of a thickness of the dielectric layer.
9. A method of forming a phase change memory device, comprising:
depositing an inter-metal dielectric layer over the first conductive feature;
forming an opening in the intermetal dielectric layer exposing the first conductive feature, the opening having tapered sidewalls;
Forming a second conductive feature in the opening comprising a barrier layer, a sidewall of the barrier layer in direct contact with the tapered sidewall of the opening;
performing a first etch-back process to recess the second conductive feature into the opening;
depositing a phase change material in the opening and over the second conductive feature;
performing a second etch back process to remove an upper portion of the phase change material, wherein sidewalls of the phase change material abut sidewalls of the barrier layer and are in direct contact with the tapered sidewalls of the opening; and
Depositing a conductive material over the phase change material.
10. The method of claim 9, wherein forming the second conductive feature comprises depositing a tantalum nitride layer and depositing a titanium nitride layer on the tantalum nitride layer, the barrier layer being the tantalum nitride layer.
11. The method of claim 9, wherein the first etch-back process is an atomic layer etch process.
12. The method of claim 9, wherein the first etch-back process comprises:
flowing a first process gas into a process chamber; and
Performing a plurality of etching cycles, wherein each etching cycle comprises:
Flowing a second process gas into the process chamber;
Igniting the second process gas into a plasma using a first bias; and
The second process gas is ignited into a plasma using a second bias voltage that is less than the first bias voltage.
13. The method of claim 12, wherein the second process gas comprises Cl 2、BCl3, ar, and He.
14. The method of claim 12, wherein the first etch-back process further comprises:
Flowing a third process gas into the process chamber prior to performing the plurality of etching cycles; and
The third process gas is ignited into a plasma.
15. The method of claim 9, wherein the second etch-back process comprises:
Flowing a fourth process gas into the process chamber; and
The fourth process gas is ignited into a plasma.
16. A phase change memory device, comprising:
a metallization layer over the semiconductor substrate;
an inter-metal dielectric layer over the metallization layer; and
A phase change random access memory cell, the phase change random access memory cell comprising:
A bottom electrode in the intermetal dielectric layer and electrically connected to the metallization layer, the bottom electrode comprising a barrier layer;
a phase change material layer on the bottom electrode and within the inter-metal dielectric layer, wherein the inter-metal dielectric layer surrounds the bottom electrode and the phase change material layer, sidewalls of the barrier layer of the bottom electrode and sidewalls of the phase change material layer are adjacent and both in direct contact with the same tapered sidewalls of the inter-metal dielectric layer, and wherein a top surface of the inter-metal dielectric layer is free of the phase change material layer; and
And a top electrode on the phase change material layer and on the top surface of the inter-metal dielectric layer.
17. The phase-change memory device as claimed in claim 16, wherein the top electrode extends below the top surface of the inter-metal dielectric layer to contact the phase-change material layer.
18. The phase-change memory device of claim 16, wherein the thickness of the phase-change material layer is between 30% and 70% of the thickness of the inter-metal dielectric layer.
19. The phase-change memory device of claim 16, wherein the phase-change material layer comprises GeSbTe.
20. The phase-change memory device of claim 16, wherein the phase-change material layer is uniform in thickness.
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