CN113517393A

CN113517393A - Phase change memory device and method of forming the same

Info

Publication number: CN113517393A
Application number: CN202110307279.8A
Authority: CN
Inventors: 李东颖; 林毓超; 余绍铭
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-04-28
Filing date: 2021-03-23
Publication date: 2021-10-19

Abstract

The method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a Phase Change Material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is flush with or below a top surface of the dielectric layer; and forming a top electrode on the PCM layer. Embodiments of the present application relate to a phase change memory device and a method of forming the same.

Description

Phase change memory device and method of forming the same

Technical Field

Embodiments of the present application relate to a phase change memory device and a method of forming the same.

Background

Semiconductor memories are used in integrated circuits for electronic applications including, for example, radios, televisions, cell phones, and personal computing devices. One type of semiconductor memory is Phase Change Random Access Memory (PCRAM), which involves storing values in a phase change material, such as a chalcogenide material. The phase change material may be switched between an amorphous phase (where the phase change material has a low resistivity) and a crystalline phase (where the phase change material has a high resistivity) to indicate a bit code. A PCRAM cell typically includes a Phase Change Material (PCM) element located between two electrodes.

Disclosure of Invention

Some embodiments of the present application provide a method of forming a phase-change memory device, including: forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode comprising a barrier layer; forming a Phase Change Material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the phase change material layer is flush with or below the top surface of the dielectric layer; and forming a top electrode on the phase change material layer.

Other embodiments of the present application provide a method of forming a phase-change memory device, including: depositing an inter-metal dielectric (IMD) layer over the first conductive feature; forming the intermetal dielectric layer exposing the first conductive component; forming a second conductive member in the opening; performing a first etch-back process to recess the second conductive feature into the opening; depositing a Phase Change Material (PCM) in the opening and over the second conductive feature; performing a second etch-back process to remove an upper portion of the phase change material; and depositing a conductive material on the phase change material.

Still further embodiments of the present application provide a phase change memory device including: a metallization layer over the semiconductor substrate; an inter-metal dielectric (IMD) layer over the metallization layer; and a Phase Change Random Access Memory (PCRAM) cell, the phase change random access memory cell comprising: the bottom electrode is positioned in the intermetallic dielectric layer and is electrically connected with the metallization layer; a Phase Change Material (PCM) layer on the bottom electrode and within the inter-metal dielectric layer, wherein the inter-metal dielectric layer surrounds the phase change material layer, and wherein a top surface of the inter-metal dielectric layer is free of the phase change material layer; and a top electrode on the phase change material layer and on the top surface of the inter-metal dielectric layer.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1-5 illustrate cross-sectional views of intermediate stages in the formation of a Phase Change Random Access Memory (PCRAM) cell, according to some embodiments.

Figures 6-8 illustrate cross-sectional views of intermediate stages in the formation of a PCRAM cell according to some embodiments.

Figure 9 illustrates a process flow of an electrode etch-back process, according to some embodiments.

Figures 10A-10D illustrate cross-sectional views of a bottom electrode of a PCRAM cell according to some embodiments.

Figures 11-14 illustrate cross-sectional views of intermediate stages in the formation of a PCRAM cell according to some embodiments.

Figures 15 and 16 illustrate cross-sectional views of an intermediate stage in the formation of a PCRAM cell according to some embodiments.

Figure 17 schematically illustrates a perspective view of a PCRAM array, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments of the present disclosure, a Phase Change Random Access Memory (PCRAM) is formed to include a plurality of PCRAM cells, which may be arranged in an array. The PCRAM cell includes a bottom electrode, a Phase Change Material (PCM) layer on the bottom electrode, and a top electrode on the PCM layer. In some embodiments, the bottom electrode is formed by etching an opening in the dielectric layer and then depositing a barrier material and a conductive material in the opening. An etch back process is performed to recess the barrier material and the conductive material into the openings, with the remaining barrier material and conductive material forming the bottom electrode. For example, the etch-back process may be an Atomic Layer Etch (ALE) process or the like, which may remove most or all of the barrier layer material from the sidewalls of the opening over the recessed bottom electrode. Removing the barrier material from the sidewalls of the opening may reduce the thermoelectric leakage of the PCRAM cell. The PCM is deposited on the bottom electrode and another etch back process is performed to remove excess PCM material, leaving the PCM to form a PCM layer. The etch-back process may recess the PCM below the top surface of the dielectric layer. Then, a top electrode is formed on the PCM layer. By forming the PCM layer surrounded by the dielectric layer, the PCRAM layer may have improved thermal insulation, and thus, the PCRAM layer may heat more efficiently during operation, which may improve the efficiency and performance of the PCRAM cell.

Fig. 1-8 and 11-16 are cross-sectional views illustrating the device region 12 of the wafer 10 in which the PCRAM cell 60 is formed (see fig. 14 and 15). Fig. 5-8 and 11-14 show an enlarged portion 45 of the structure. Fig. 9 shows a process flow of the electrode etch-back process 100, and fig. 10A-10D show an exemplary bottom electrode 50 formed using the electrode etch-back process 100. Fig. 17 shows a schematic diagram of a PCRAM array 70 comprising a plurality of PCRAM cells 60.

Fig. 1 illustrates a cross-sectional view of a device region 12 of a wafer 10, according to some embodiments. The device regions 12 are different areas of the wafer 10 that are singulated in subsequent steps to form a plurality of device dies 12, each device die including a PCRAM structure, such as a PRCAM cell 60 (see fig. 14-15) or a PCRAM array 70 including a plurality of PCRAM cells 60 (see fig. 17). The wafer 10 includes a semiconductor substrate 20, which may be, for example, an active layer of a doped or undoped silicon or semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 20 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 20 has an active surface (e.g., the surface facing upward in fig. 1), sometimes referred to as the front side, and a passive surface (e.g., the surface facing downward in fig. 1), sometimes referred to as the back side.

The devices are formed at the active surface of the semiconductor substrate 20. The devices may include active devices and/or passive devices. For example, the devices may include transistors, diodes, capacitors, resistors, etc., and may also be processed according to applicable fabrication processes. For example, fig. 1 shows an access transistor 22 formed on the front surface of a semiconductor substrate 20, the access transistor being used to access (or "select") a PCRAM cell 60 of a device die 12 (see fig. 16). According to some embodiments, the access transistor 22 includes a gate dielectric layer 25, a gate electrode 26, source/drain regions 24, source/drain contact plugs 30, and gate contact plugs 32. In some embodiments, the source/drain regions 24 may extend to the semiconductor substrate 20.

As shown in fig. 1, one or more interlayer dielectric (ILD) layers 31 are formed on the semiconductor substrate 20, and conductive features such as contact plugs 30/32 are formed on the ILD layer 31 to electrically connect with the access transistors 22. For example, the contact plugs 30/32 may be formed of tungsten, cobalt, nickel, copper, silver, aluminum, or the like, or a combination thereof. ILD layer 31 may be formed of any suitable dielectric material, such as an oxide, for example, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like; nitrides such as silicon nitride and the like; low-k dielectric materials, the like, or combinations thereof. The ILD layer may be formed by any suitable deposition process, such as spin coating, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), the like, or combinations thereof. Contact plugs 30/32 or other conductive features in ILD layer 31 may be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.), the like, or combinations thereof. In some embodiments, ILD layer 31 comprises one or more inter-metal dielectric (IMD) layers.

Still referring to fig. 1, an inter-metal dielectric (IMD) layer 33 and metal lines 34 are formed over the ILD layer 31, according to some embodiments. IMD layer 33 may be formed of any suitable dielectric material, for example, an oxide such as silicon oxide, PSG, BSG, BPSG/USG, etc.; nitrides such as silicon nitride and the like; and the like or combinations thereof. IMD layer 33 may be formed by any suitable deposition process, such as spin coating, PVD, CVD, the like, or combinations thereof. IMD layer 33 may be a layer formed from a low-k dielectric material having a k value of less than about 3.0.

Metal line 34 is formed in IMD layer 33 and electrically coupled to access transistor 22 (e.g., through contact plug 30/32). In some embodiments, as described in more detail in fig. 17, some or all of metal lines 34 may be used as Word Lines (WLs) that are connected to columns of PCRAM cells 60 in PCRAM array 70. According to some embodiments, metal line 34 includes a diffusion barrier layer and a conductive material over the diffusion barrier layer. As an exemplary process for forming metal lines 34, openings (not shown) may be formed in IMD layer 33 using, for example, a suitable etching process. The openings expose underlying conductive members, such as contact plugs 30/32. The diffusion barrier layer may be formed of tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, or the like, or a combination thereof, and may be formed in the opening by a deposition process, such as Atomic Layer Deposition (ALD), or the like. The conductive material may include copper, aluminum, tungsten, silver, or the like, or combinations thereof, and may be formed over the diffusion barrier layer in the opening using an electrochemical plating process, CVD, ALD, PVD, or the like, or combinations thereof. In an embodiment, the conductive material is copper, and the diffusion barrier layer is a thin barrier layer that prevents diffusion of copper into the IMD layer 33. After the diffusion barrier and the conductive material are formed, excess diffusion barrier and conductive material may be removed by, for example, a planarization process, such as a Chemical Mechanical Polishing (CMP) process. The remaining diffusion barrier and conductive material form metal lines 34 in IMD layer 33. Other techniques may also be used to form metal lines 34.

Fig. 2 illustrates the formation of a dielectric layer 36 and a metallization layer 40 over and electrically connected to metal lines 34, according to some embodiments. The metallization layer 40 provides additional interconnects (e.g., interconnects between the metal lines 34, the access transistors 22, etc.). In some embodiments, dielectric layer 36 may be considered an IMD layer, and dielectric layer 36 may be formed of a dielectric layer material similar to that described above for IMD layer 33. Metallization layer 40 (e.g., a metallization pattern) may include metal lines and vias formed in dielectric layer 36. The metallization layer 40 may be formed using a damascene process, such as a single damascene process, a dual damascene process, and the like. For example, the metallization layer 40 may be formed by: etching into the dielectric layer 36 to form an opening; filling the opening with a conductive material; and performing a planarization process, such as a CMP process or a polishing process, to remove the excess conductive material. In some embodiments, metallization layer 40 may be formed in a similar manner as metal lines 34, or may be formed using other suitable techniques. It will be appreciated that although one metallization layer 40 (including metal lines and underlying vias) is shown in fig. 2, in other embodiments, additional metallization layers may be formed in additional dielectric layers above dielectric layer 36. Alternatively, a subsequently formed PCRAM cell 60 (as shown in fig. 14) may be formed directly on metal line 34 without forming metallization layer 40. In some embodiments, the metal lines 34 and/or the contact plugs 30/32 may also be considered part of the metallization layer. In some embodiments, the metal line region of the metallization layer 40 is formed with a width W1 in a range from about 100nm to about 300 nm.

Figures 3-15 are various views of intermediate stages in the manufacture of a PCRAM cell 60 of device die 12 (see figure 15), according to some embodiments. Fig. 3 and 4 show the same cross-sectional views as shown in fig. 1 and 2, and fig. 5 to 8 and 10A to 10D and 11 to 15 show an enlarged portion 45 of the structure shown in fig. 4.

Turning to fig. 3, in some embodiments, an IMD layer 42 is formed over the dielectric layer 36 and the metallization layer 40. In some embodiments, an etch stop layer (not shown) is formed on dielectric layer 36 and metallization layer 40 prior to forming IMD layer 42. The etch stop layer may be formed from one or more layers of dielectric materials such as aluminum nitride, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, and the like, or combinations thereof. The etch stop layer may be formed by CVD, PVD, ALD, spin-on dielectric processes, the like, or combinations thereof. In some embodiments, IMD layer 42 is formed from tetraethyl orthosilicate (TEOS) oxide (e.g., silicon oxide deposited using TEOS as a precursor, such as a CVD process). In some embodiments, IMD layer 42 may be formed using PSG, BSG, BPSG, USG, fluorosilicate glass (FSG), silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, SiOCH, flowable oxide, porous oxide, the like, or combinations thereof. For example, IMD layer 42 may also be formed from a low-k dielectric material having a k value of less than about 3.0. In some embodiments, IMD layer 42 is formed to a thickness T1 in a range from about 60nm to about 1000 nm. Other thicknesses are also possible.

In fig. 4 and 5, openings 44 are patterned in IMD layer 42, according to some embodiments. Fig. 5 shows an enlarged portion 45 of the cross-sectional view shown in fig. 4. Opening 44 exposes the topmost metallization layer 40 so that the bottom electrode 50 of a PCRAM cell 60 subsequently formed in opening 44 (see fig. 14) makes an electrical connection with metallization layer 40. In some embodiments where metallization layer 40 is not formed, IMD layer 42 is formed over metal line 34 and opening 44 exposes metal line 34. The openings 44 may be formed using acceptable photolithography and etching techniques. For example, a mask layer (not shown) such as a hard mask layer or a photoresist layer (e.g., a single layer of photoresist, a triple layer of photoresist, etc.) may be formed over IMD layer 42 and patterned. IMD layer 42 may be etched using the patterned mask layer as an etch mask to form opening 44. IMD layer 42 may be etched using an anisotropic etch process, such as a suitable dry etch process. One or more etching processes may be performed and the opening 44 extends through the etch stop layer (if present) over the metallization layer 40. After forming the opening 44, the remaining portions of the mask layer may be removed using, for example, an ashing process, an etching process, or other suitable process.

The opening 44 may have tapered sidewalls as shown in fig. 4-5, or the opening 44 may have substantially vertical sidewalls. In some embodiments, the width W2 of opening 44 is formed to be in the range of about 40nm to about 80 nm. Other widths are also possible. In some embodiments, the upper width of the opening 44 is greater than the lower width of the opening 44, as shown in fig. 4-5. In other embodiments, the opening 44 has a substantially constant width (e.g., width W2). In some embodiments, the width W2 of the opening 44 may be less than or about equal to the width W1 of the underlying metallization layer 40. In some embodiments, the width to height aspect ratio of opening 44 (e.g., W2: T1 ratio) is in the range of about 1:8 to about 1: 15.

Fig. 6-10D illustrate the formation of the bottom electrode 50 of the PCRAM cell 60, according to some embodiments. In fig. 6, barrier layer 46 and conductive material 48 are deposited over IMD layer 42 and in opening 44, according to some embodiments. Barrier layer 46 may be conformally deposited over IMD layer 42, over the sidewalls of opening 44, and over metallization layer 40. In some embodiments, barrier layer 46 is formed from one or more conductive materials such as titanium, titanium nitride, tantalum nitride, cobalt, and the like, or combinations thereof. The barrier layer 46 may be formed using one or more suitable deposition processes, such as PVD, CVD, ALD, and the like. In some embodiments, barrier layer 46 is a tantalum nitride layer deposited using an ALD process or other suitable process. In some embodiments, the thickness of barrier layer 46 formed within opening 44 is in the range of about 20nm to 80 nm. Other thicknesses are also possible.

After depositing barrier layer 46, conductive material 48 is deposited over barrier layer 46 to fill opening 44. In some embodiments, conductive material 48 is formed from one or more conductive materials such as titanium, titanium nitride, tantalum, aluminum, tungsten, platinum, nickel, chromium, ruthenium, and the like. The conductive material 48 may be deposited using CVD, PVD, ALD, electrochemical plating, electroless plating, and the like. In some embodiments, conductive material 48 is titanium nitride deposited using PVD.

In fig. 7, a planarization process is performed to remove excess barrier layer 46 and conductive material 48 from IMD layer 42, according to some embodiments. For example, the planarization process may include a CMP process or a mechanical polishing process. Planarization may make the top surfaces of IMD layer 42, barrier layer 46, and conductive material 48 flush.

In fig. 8, an electrode etch-back process is performed on barrier layer 46 and conductive material 48 to form bottom electrode 50, according to some embodiments. The electrode etch-back process etches the barrier layer 46 and the conductive material 48 to recess the barrier layer 46 and the conductive material 48 into the opening 44. In some embodiments, the electrode etch-back process may selectively etch the material of barrier layer 46 and the material of conductive material 48 over the material of IMD layer 42. In this manner, barrier layer 46 may be removed from the sidewalls of opening 44 without significantly etching the sidewalls of opening 44. Fig. 9 depicts an exemplary electrode etch-back process 100 in greater detail. The area within opening 44 corresponding to the removed barrier layer 46 and conductive material 48 is labeled as recessed area 51 in fig. 8. After performing the electrode etch-back process, the remaining barrier layer 46 and conductive material 48 in opening 44 form the bottom electrode 50 of PCRAM cell 60 (see fig. 14). For example, an electrode etch-back process may recess barrier layer 46 and conductive material 48 from the top surface of IMD layer 42 by a depth D1, which forms a recessed region 51 of depth D1. After performing the electrode etch-back process, the remaining barrier layer 46 and conductive material 48 form a bottom electrode 50 having a thickness T2 overlying the underlying metallization layer 40.

In some embodiments, the thickness T2 of bottom electrode 50 may be in the range of about 10nm to about 30 nm. Other thicknesses are also possible. In some embodiments, the thickness T2 of bottom electrode 50 may be between about 25% and about 50% of the thickness T1 of IMD layer 42, although other proportions are possible. In some embodiments, the ratio of the thickness T2 to the depth D1 of the recessed region 51 (e.g., thickness T2: depth D1) may be between about 1:1 to about 1:3, although other ratios are possible. In some embodiments, the thickness T3 of the subsequently formed Phase Change Material (PCM) layer 54 (see FIG. 12) is determined by the thickness T2 of the bottom electrode 50. In this manner, by controlling the depth D1 of the electrode etch-back process, the relative or absolute size of the bottom electrode 50 and the PCM layer 54 may be controlled, and thus the operating characteristics of the PCRAM cell 60 may be controlled. For example, during operation of PCRAM cell 60, the heating characteristics of bottom electrode 50 may be controlled by controlling thickness T2. Additionally, fig. 8 shows the bottom electrode 50 having a flat top surface, however in other embodiments, the bottom electrode 50 may have a convex surface, a concave surface, an irregular surface, or a combination thereof, as described in more detail below with respect to fig. 10A-10D.

By forming bottom electrode 50 using the electrode etch-back process described herein, a subsequently formed PCM layer 54 (see fig. 12) may be defined within IMD layer 42, which may improve heat transfer efficiency and, thus, improve performance and power consumption of PCRAM cell 60. In addition, the electrode etch-back process removes at least some of barrier layer 46 from the sidewalls of opening 44 due to the recessing of barrier layer 46. In this way, excess barrier layer 46 within opening 44 that is not part of bottom electrode 50 may be removed. For example, the electrode etch-back process may partially or completely remove the barrier layer 46 within the recessed region 51, which may expose sidewalls of the opening 44 within the recessed region 51. By removing excess barrier layer 46 within opening 44, electrical and/or thermal leakage due to the presence of excess barrier layer 46 may be reduced, which may improve electrical performance and heat transfer efficiency of PCRAM cell 60.

Figure 9 illustrates a process flow of the electrode etch-back process 100 according to some embodiments. As shown in fig. 8, for example, an electrode etch-back process 100 may be used to etch barrier layer 46 and conductive material 48 to form bottom electrode 50. The electrode etch-back process 100 includes a pre-etch process 101, an etch process 110, and a post-etch process 131. In some embodiments, the etching process 110 is an ALE process or the like. In some embodiments, electrode etch-back process 100 selectively etches barrier layer 46 and conductive material 48 over IMD layer 42. The electrode etch-back process 100 is an example electrode etch-back process, and other process parameters, process gases, or etching techniques may be used.

Before performing the etching process 110, an etch pretreatment 101 may be performed to remove metal oxide from a surface (e.g., the surface of the structure shown in fig. 7). For example, pre-etch treatment 101 may remove titanium oxide or tantalum oxide from the exposed surfaces of barrier layer 46 or conductive material 48. Removing the metal oxide using the pre-etch treatment 101 may make the etch more uniform during the etch process 100. After the pre-etch treatment 101, a purge may be performed to remove process gases, reaction products, and the like.

In some embodiments, the pre-etch treatment 101 includes a plasma process, such as a plasma etch. The plasma process may include flowing one or more process gases into the process chamber and igniting the one or more process gases into a plasma. For example, pre-etch treatment 101 may include the use of one or more process gases, such as CH₄、Cl₂Ar, etc., other gases, or combinations thereof. For example, in some embodiments, a CH may be used₄、Cl₂And Ar, wherein CH₄Between about 3sccm to about 10sccm, Cl₂Between about 30sccm to about 100sccm and/or Ar between about 50sccm to about 100 sccm. Other mixtures are also possible. The plasma process may be performed using a plasma source power in a range of about 150W to about 400W and a bias power in a range of about 30W to about 60W. In some embodiments, no bias power is applied. The pre-etch treatment 101 may be performed using a pressure in a range of about 3mTorr to about 10mTorr, a process gas flow rate in a range of about 100sccm to about 250 sccm. Other process gases or process parameters are also possible.

In some embodiments, the etch process 110 includes a process gas soak 111 followed by one or more etch cycles 120. For example, during the process gas immersion 111, the structure may be exposed to a process gas such as Cl₂Or other gases. In some embodiments, the process gas can have a flow rate in the range of about 100sccm to about 300sccmDown flow, but other flow rates are possible. In some embodiments, the process gas is not ignited into a plasma during the process gas immersion 111. After the etch process 110, a purge is performed to remove process gases, reaction products, and the like.

After the process gas soak 111, one or more etch cycles 120 are performed. In some embodiments, each etch cycle 120 includes a main etch step 121 and an overetch step 122. Each of the main etch step 121 and the overetch step 122 may include flowing one or more process gases into the process chamber and igniting the one or more process gases into a plasma. The main etch step 121 may include a plasma etch using one or more process gases, such as Cl₂、BCl₃Ar, He, etc., other gases, or combinations thereof. For example, in some embodiments, Cl may be used₂、BCl₃A mixture of Ar and He, wherein Cl₂Between about 30% and about 70%, BCl₃Between about 20% and about 60%, Ar between about 20% and about 50%, and/or He between about 20% and about 50%. Other mixtures are also possible. The main etch step 121 may be performed using a plasma source power in a range of about 250W to about 400W, and the main etch step 121 may be performed using a bias power in a range of about 0W to about 30W. In some embodiments, the bias power has a switching duty cycle between about 20% to about 80%, or a frequency in the range of about 100Hz to about 1000 Hz. The main etch step 121, pressure, process gas flow rate may be performed using a pressure in a range of about 3mTorr to about 10mTorr and a process gas flow rate in a range of about 300sccm to about 1000 sccm. In some embodiments, the main etch step 121 may be performed continuously in a range of about 100 seconds to about 500 seconds. Other process gases or process parameters are also possible.

The overetch step 122 may include a plasma etch using one or more process gases, such as Cl₂、BCl₃Ar, He, etc., other gases, or combinations thereof. For example, in some embodiments, Cl may be used₂、BCl₃A mixture of Ar and He, wherein Cl₂Between about 30% and about 70%, BCl₃Between about 20% and about 60%, Ar between about 20% and about 50%, and/or He between about 20% and about 50%. Other mixtures are also possible. In some embodiments, the mixture of process gases used in the overetch step 122 is the same as the mixture of process gases used in the main etch step 121. The overetch step 122 may be performed using a plasma source power in the range of about 150W to about 250W, and the overetch step 122 may be performed using a bias power in the range of about 0W to about 20W. In some embodiments, the bias power has a switching duty cycle between about 20% to about 50%, or a frequency in the range of about 100Hz to about 1000 Hz. In some embodiments, the overetch step 122 is similar to the main etch step 121 except that the overetch step 122 uses a lower bias power than the main etch step 121. For example, the bias power for the overetch step 122 may be between about 10% and about 30% of the bias power used for the main etch step 121, although other percentages are possible. The overetch step 122 may be performed using a pressure in a range of approximately 5mTorr to approximately 15mTorr and a process gas flow rate in a range of approximately 33sccm to approximately 1000 sccm. In some embodiments, the overetch step 122 may be performed continuously in a range of about 100 seconds to about 300 seconds. Other process gases or process parameters are also possible.

Similar to the ALE process, the electrode etch-back process 100 described herein may allow for a high degree of etch control. In some embodiments, the etch distance per etch cycle 120 is in the range of about 1nm to 1.5nm, although other etch rates are possible. In some embodiments, etch cycle 120 removes about one monolayer of barrier layer 46 and/or conductive material 48. The etch cycle 120 may be repeated any number of times until the desired amount of material is removed. In some embodiments, the etch process 110 includes performing the etch cycle 120 in a range of about 10 times to about 30 times, although the etch cycle 120 may be performed a different number of times in other embodiments. In this way, the electrode etch-back process 100 may result in improved control of the thickness T2 of the bottom electrode 50 and improved control of the thickness T3 of the PCM layer 54 (see fig. 12).

In some embodiments, turning to fig. 10A-10D, the bottom electrode 50 is shown with differently shaped top surfaces. In some embodiments, controlling the process gas during the etch cycle 120 may control the relative etch rates of the barrier layer 46 and the conductive material 48 to control the shape of the top surface of the bottom electrode 50. In some embodiments, barrier layer 46 is tantalum nitride and conductive material 48 is titanium nitride for Cl during etch cycle 120₂Is controlled to control the etch rate of barrier layer 46 and BCl during etch cycle 120₃Is controlled to control the etch rate of the conductive material 48.

Referring to fig. 10A, similar to bottom electrode 50 as shown in fig. 8, example bottom electrode 50, barrier layer 46 and conductive material 48 are shown with top surfaces that are substantially horizontal. In some embodiments, bottom electrode 50 may be formed with a substantially horizontal surface of barrier layer 46 and conductive material 48 by controlling etch process 110 such that the etch rate of barrier layer 46 is substantially the same as the etch rate of conductive material 48. In some cases, the etch rate may be controlled by controlling the flow rate of the respective process gases during the etch process 110. For example, it may be present in a Cl ratio of about 1:6₂Flow rate and BCl₃The flow rate ratio etches a similar ratio of barrier layer 46 and conductive material 48. For example, CL₂At a flow rate of about 30sccm, BCl₃The flow rate of (2) is about 180 sccm. This is an illustrative example, and other ratios or flow rates may be used. In some cases, forming barrier layer 46 and conductive material 48 with substantially flush top surfaces may enhance the diffusion barrier of barrier layer 46.

Referring to fig. 10B, an example bottom electrode 50 is shown, the top surface of the conductive material 48 being concave, according to some embodiments. In some embodiments, the conductive material 48 having a concave surface may be formed by etching the conductive material 48 at a rate greater than the rate of etching of the barrier layer 46 during the etching process 110. For example, in some cases, Cl may be present at about 1:1 to 1:2₂Flow rate and BCl₃The flow rate ratio etches the conductive material 48 at a rate greater than the etch rate of the barrier layer 46. This is achieved byAre illustrative examples, other ratios or flow rates may be used. In some cases, forming bottom electrode 50 with conductive material 48 having a top surface that extends below a top surface of barrier layer 46, e.g., a concave top surface, may result in enhanced diffusion barrier of barrier layer 46.

Fig. 10C illustrates an example bottom electrode 50 with a top surface of conductive material 48 being convex and raised above a top surface of barrier layer 46, according to some embodiments. Fig. 10D illustrates an example bottom electrode 50 with the top surface of barrier layer 46 being concave and extending below the top surface of conductive material 48, according to some embodiments. In some embodiments, during the etch process 110, the convex conductive material 48 and/or the concave barrier layer 46 may be formed by etching the barrier layer 46, the etch rate of the barrier layer 46 being greater than the etch rate of the conductive material 48. For example, in some cases, it may be present in a Cl range of about 1:1 to 2:1₂Flow rate and BCl₃The flow rate ratio etches the barrier layer 46, which has an etch rate greater than the etch rate of the conductive material 48. This is an illustrative example, and other ratios or flow rates may be used.

Returning to fig. 9, after the etching process 110 is complete, a post-etch process 131 may be performed. In some embodiments, the post etch process 131 uses a process gas such as N2H2 or the like. In some embodiments, post etch process 131 may include a plasma process. The plasma process may be performed using a plasma source power in a range of about 200W to about 400W. The post-etch process 131 may be performed using a pressure in a range of approximately 20mTorr to approximately 80mTorr, a process temperature in a range of approximately 60 ℃ to approximately 120 ℃, or a process gas flow rate in a range of approximately 200sccm to approximately 1000 sccm. Other process gases or process parameters are also possible. After the post-etch treatment 131, a purge is performed to remove process gases, reaction products, and the like.

The electrode etch-back process 100 as shown in fig. 9 is an example electrode etch-back process, and the electrode etch-back process may be different in other embodiments. Some of the steps and processes shown may be omitted or repeated, or other steps and processes described may also be included. For example, in other embodiments, the etch cycle 120 may include only one step (e.g., only the main etch step 121) or may include more than three steps, any of which may be similar or different from the steps described for the electrode etch-back process 100. Other variations of the electrode etch-back process 100 are also possible.

Referring to fig. 11, according to some embodiments, a PCM53 is formed in the opening 44 and covers the bottom electrode 50. As shown in fig. 11, a PCM53 may be deposited to fill the recessed region 51, and a PCM53 may also cover the surface of the IMD layer 42. In some embodiments, the PCM53 may be partially deposited to fill the recessed area 51. In some embodiments, PCM53 is a chalcogenide material such as GeSbTe (GST) or GeSbTeX, where X is a material such as Ag, Sn, In, Si, N, and the like. Other materials are also possible. The PCM53 may be formed using a suitable deposition process, such as PVD, CVD, plasma enhanced CVD (pecvd), ALD, and the like.

In fig. 12, a PCM etch-back process is performed to etch PCM53 and form PCM layer 54, according to some embodiments. The PCM etch back process removes PCM53 from the top surface of IMD layer 42, leaving PCM53 to form PCM layer 54 of PCRAM cell 60 (see fig. 14). As shown in fig. 12, the PCM etch-back process may form the PCM layer 54 having a top surface substantially level with the top surface of the IMD layer 42 or the top surface of the PCM layer 54 may be recessed from the top surface of the IMD layer 42. In some embodiments, the top surface of the PCM layer 54 may be recessed from the top surface of the IMD layer 42 by a depth D2, with a depth D2 in a range of about 40nm to about 60 nm. Other distances are also possible. Recessing PCM layer 54 into the top surface of IMD layer 42 makes PCM layer 54 more confined to IMD layer 42, which may improve thermal transfer efficiency and operation of PCRAM cell 60. Thus, a greater depth D2 may result in increased confinement of the PCM layer 54. In some embodiments, a planarization process, such as a CMP process, may be performed before the PCM etch-back process is performed. The PCM layer 54 may be formed to have a flat top surface, a concave top surface, a convex top surface, an irregular top surface, or the like.

In some embodiments, the PCM etch-back process comprises a plasma process, such as plasma etching. The plasma process may include flowing one or more process gases into the process chamber and igniting the one or more process gases into a plasma. For example, the PCM etch-back process may include a plasma process using one or more process gases, such as HBr, Ar, He, etc., other gases, or combinations thereof. For example, in some embodiments, a mixture of HBr, Ar, and He can be used, where HBr is between about 20% to about 40%, Ar is between about 30% to about 50%, and/or He is between about 10% to about 20%. Other mixtures are also possible. The plasma process may be performed using plasma source power in the range of about 100W to about 400W or bias power in the range of about 100W to about 200W. In some embodiments, no bias power is used. The PCM etch-back process may be performed using a pressure in a range of about 3mTorr to about 10mTorr, a process temperature in a range of about 40 ℃ to about 70 ℃, or a process gas flow rate in a range of about 100sccm to about 300 sccm. Other process gases or process parameters are also possible.

In some embodiments, forming the PCM layer 54 described herein in the opening 44 may result in an improved sidewall quality of the PCM layer 54. For example, in some cases, forming the PCM layer using an etching process (e.g., as part of lithographic patterning) may cause damage to the PCM layer during the etching process. By forming the PCM layer 54 without etching sidewalls of the PCM layer 54, etching damage to the sidewalls of the PCM layer 54 may be avoided. Thus, the formed PCM layer 54 may improve sidewall quality, which may reduce defects in the PCM layer 54, reduce electrical or thermal leakage of the PCMRAM cell 60, and increase power of the PCRAM cell 60 during operation.

As shown in fig. 12, the PCM etch-back process removes PCM53 from the top surface of IMD layer 42 and forms PCM layer 54 having a substantially uniform thickness. In some embodiments, the thickness T3 of the PCM layer 54 may be in the range of about 10nm to about 30nm, although other thicknesses are possible. In some embodiments, thickness T3 may be between about 30% and about 70% of thickness T1 of IMD layer 42, or thickness T3 may be between about 30% and about 100% of depth T1 of recessed region 51. In some embodiments, the ratio of the thickness T2 of the bottom electrode 50 to the thickness T3 of the PCM layer 54 is between about 1:1 to about 1: 3. Other distances, percentages or ratios are also possible. In this way, the absolute or relative thicknesses of the bottom electrode 50 and the PCM layer 54 may be controlled to achieve certain characteristics, such as size, resistance, power consumption, thermal efficiency, and the like.

In fig. 13, a top electrode material 55 is deposited over IMD layer 42 and overlying PCM layer 54, according to some embodiments. As shown in fig. 13, top electrode material 55 extends below the top surface of IMD layer 42 to contact PCM layer 54. In some embodiments, the top electrode material 55 includes a barrier layer and a conductive material over the barrier layer, which is not separately depicted in this figure. The barrier layer may be similar to barrier layer 46 described in fig. 6, or may be formed in a similar manner. For example, the barrier layer of top electrode material 55 may comprise tantalum nitride conformally deposited over IMD layer 42 and PCM layer 54, although other materials are possible. After depositing the barrier layer of top electrode material 55, a conductive material is deposited over the barrier layer. The conductive material may be similar to conductive material 48 described in fig. 6, or may be formed in a similar manner. For example, the conductive material of the top electrode material 55 may include titanium nitride deposited on a barrier layer, although other materials are possible. In some embodiments, after deposition, a planarization process (e.g., a CMP or polishing process) is performed on the top electrode material. In some embodiments, top electrode material 55 having a thickness T4 may be formed on the top surface of IMD layer 42, with a thickness T4 in the range of about 20nm to about 50nm, although other thicknesses are possible.

Turning to fig. 14, the top electrode material 55 is patterned to form a top electrode 56 of a PCRAM cell 60, according to some embodiments. The top electrode material 55 may be patterned using acceptable photolithography and etching techniques. For example, a mask layer (not shown) such as a hard mask layer or a photoresist layer (e.g., a single layer of photoresist, a triple layer of photoresist, etc.) may be formed and patterned over the top electrode material 55. The top electrode material 55 may be etched into an etch film using a patterned masking layer, with the remaining portions of the top electrode material 55 forming the top electrode 56. The top electrode material 55 may be etched using an anisotropic etch process, such as a suitable dry etch process. After forming the top electrode 56, the remaining portions of the mask layer may be removed by, for example, an ashing process, an etching process, or other suitable processes. In this way, a PCRAM cell 60 including the bottom electrode 50, the PCM layer 54 and the top electrode 56 may be formed. In some embodiments, the sides of the PCM layer 54 are surrounded by the IMD layer 42, and the bottom and top of the PCM layer 54 are covered by the bottom electrode 50 and the top electrode 56, respectively.

As shown in fig. 14, top electrode 56 may extend above the top surface of IMD layer 42 and have a thickness T4 above the top surface of IMD layer 42. In some embodiments, portions of top electrode 56 may extend below the top surface of IMD layer 42 to contact PCM layer 54. Thus, the portion of the top electrode 56 above the PCM layer 54 may have a thickness greater than the thickness T4. In some embodiments, the top electrode 56 may have a width W3, with a width W3 in the range of about 10nm to about 30 nm. The width W3 of the top electrode may be greater than, about equal to, or less than the width W1 of the underlying metallization layer 40.

Turning to fig. 15, a cross-sectional view of device region 12 of wafer 10 is shown, in accordance with some embodiments. The cross-sectional view shown in fig. 15 is similar to the cross-sectional view shown in fig. 1-4, except that a PCRAM cell 60 as described in fig. 5-14 is formed. As shown in fig. 15, a PCRAM cell 60 is connected to the metallization layer 40 and also to the access transistor 22 or other device formed in the semiconductor substrate 20.

In fig. 16, according to some embodiments. IMD layer 62 is formed over IMD layer 42 and top electrode 56, and metallization layer 64 is formed in IMD layer 62. In some embodiments, as described in more detail below with respect to fig. 17, some or all of the metallization layers 64 may be used as Bit Lines (BL) that are connected to rows of PCRAM cells 60 in the PCRAM array 70. In some embodiments, an etch stop layer (not shown) is deposited over IMD layer 42 and top electrode 56 prior to forming IMD layer 62. IMD layer 62 may be formed of a dielectric material similar to that previously described for IMD layer 42, dielectric layer 36, or IMD layer 33, and may also be formed in a similar manner. Metallization layer 64 may include metal lines and vias formed in IMD layer 62. The metallization layer 64 may be formed using a damascene process, such as a single damascene process, a dual damascene process, and the like. For example, the metallization layer 64 may be formed by: the IMD layer 62 is etched to form via openings (for vias) and trenches (for metal lines), the via openings and trenches are filled with a conductive material, and a planarization process, such as a CMP process or a grinding process, is performed to remove excess conductive material. In some embodiments, metallization layer 64 may be formed in a similar manner as metal lines 34 or metallization layer 40, or may be formed using other suitable techniques. It will be appreciated that although one metallization layer 64 (including metal lines and underlying vias) is depicted in fig. 16, additional metallization layers may be formed in additional IMD layers above IMD layer 62. In subsequent processes, features are formed overlying metallization layer 64 and IMD layer 62 to form wafer 10 and device die 12. A singulation process may be performed to singulate the device regions 12 of the wafer 10 into individual device dies 12.

Figure 17 schematically illustrates a perspective view of a PCRAM array 70 including PCRAM cells 60 arranged in an array, according to some embodiments. In the illustrated embodiment, the WL is electrically connected to the bottom electrode 50 of each column of PCRAM cells 60 in the PCRAM array 70. Each column of PCRAM array 70 has an associated word line to which the PCRAM cells 60 in the column are connected. For example, the word line may be a metal line 34 that is connected to the access transistor 22. BL is connected to the top electrode 56 of each row of PCRAM cells 60 in the PCRAM array 70. Each row of PCRAM array 70 has an associated bit line, and PCRAM cells 60 within a row are connected to the bit lines of that row. For example, the bit lines may be metal lines and vias of the metallization layer 64. Some components in fig. 17 are not shown, such as access transistor 22, metallization layer 40, etc. Each PCRAM cell 60 of PCRAM array 70 may be selected from a suitable combination of word lines and bit lines. For example, a particular PCRAM cell 60 may be selected by accessing a single word line connected to the PCRAM cell 60 and accessing a single bit line connected to the PCRAM cell 60. Other configurations of bit lines, word lines, or PCRAM cells are also possible.

The resistance of the PCM layer 54 of each PCRAM cell 60 is programmable and can be varied between a high resistance state and a low resistance state, which may correspond to two states of a binary code. Since current passes through PCRAM cell 60, heating of PCM layer 54 may be controlled by bottom electrode 50 and/or top electrode 56 to change (e.g., may change the phase of PCM layer 54) between a high resistance state and a low resistance state of PCRAM cell 60. In this way, the resistance of its PCM layer 54 may be programmed using its corresponding access transistor 22 to write a value into the PCRAM cell 60, or the resistance of its PCM layer 54 may be measured by its corresponding access transistor 22 to read a value from the PCRAM cell 60. The PCRAM cell 60 described herein includes a PCM layer 54 that is completely bounded by sidewalls that are substantially free of the barrier layer 46, which may improve heating control and efficiency or reduce power consumption during programming of the PCRAM cell 60.

Embodiments may realize advantages. PCRAM cells can be formed using the techniques herein with the sidewalls of the PCM layer completely confined in the dielectric layer. For example, a PCM layer may be formed that does not extend over the top surface of the dielectric layer. This may result in improved thermal limitations and heat transfer efficiency, allowing the PCRAM cell to be programmed using smaller voltages and/or currents. For example, by forming a PCM layer bounded by a dielectric layer, heating of the PCM layer during programming may be better localized to the center of the PCM layer. Thus, the phase change of the PCM layer may diffuse from its center, which may reduce the boundary effect, since the bottom and/or top electrode may reduce the efficiency. In addition, the techniques described herein enable removal of electrode barrier material prior to formation of the PCM layer. Barrier layer material on or near the PCM layer may cause thermal or electrical leakage, and thus, removal of the barrier layer material may reduce thermal or electrical leakage within the PCRAM cell. Thus, the techniques described herein enable improved energy efficiency of PCRAM arrays. Additionally, the techniques described herein may form a PCRAM cell without etching sidewalls of the PCM layer, which may reduce or eliminate etching-induced damage to the PCM layer or etching-induced defects formed in the PCM layer.

In some embodiments, a method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a PCM within the opening and on the bottom electrode, wherein a top surface of the PCM layer is flush with or lower than a top surface of the dielectric layer; and forming a top electrode on the PCM layer. In one embodiment, the sidewalls of the PCM layer are free of barrier layers. In one embodiment, forming the bottom electrode includes depositing a barrier layer in the opening; depositing a conductive material on the barrier layer; and depositing a barrier layer and a conductive material, wherein the etching leaves the sidewalls of the opening treated. In one embodiment, after etching the barrier layer and the conductive material, a top surface of the conductive material bulges. In one embodiment, after etching the barrier layer and the conductive material, the top surface of the barrier layer is flush with the top surface of the conductive material. In one embodiment, forming the PCM layer includes depositing a phase change material over the bottom electrode and the dielectric layer; and etching the phase change material to remove the phase change material from the top surface of the dielectric layer. In one embodiment, the thickness of the bottom electrode is between about 25% and about 50% of the thickness of the dielectric layer. In one embodiment, the thickness of the PCM layer is between about 30% and about 70% of the thickness of the dielectric layer.

In some embodiments, the method includes depositing an inter-metal dielectric (IMD) layer over the first conductive component; forming an opening in the IMD layer exposing the first conductive feature; forming a second conductive member in the opening; performing a first etch-back process to recess the second conductive feature in the opening; depositing a PCM in the opening and over the second conductive feature; performing a second etch-back process to remove an upper portion of the PCM; and depositing a conductive material on the PCM. In one embodiment, forming the second conductive feature includes depositing a tantalum nitride layer and depositing a titanium nitride layer on the tantalum nitride layer. In one embodiment, the first etch-back process is an ALE process. In one embodiment, a first etch-back process includes flowing a first process gas into a process chamber and performing a plurality of etch cycles, wherein each etch cycle includes flowing a second process gas into the process chamber; igniting the second process gas into a plasma while using the first bias voltage; and igniting the second process gas into a plasma while using a second bias voltage that is lower than the first bias voltage. In one embodiment, the second process gas comprises Cl₂、BCl₃Ar and/or He. In one embodiment, the first etch-back process includes flowing a third process gas into the process chamber before performing the plurality of etch cycles; and igniting the third process gas into a plasma. In one embodiment, the second etch-back process includes flowing a fourth process gas into the process chamber and igniting the fourth process gas into a plasma.

In some embodiments, a device includes a conductive metallization layer over a semiconductor substrate; an IMD layer over the metallization layer; and a PCRAM cell comprising a bottom electrode in the IMD layer, the bottom electrode being electrically connected to the metallization layer; a PCM layer on the bottom electrode and within the IMD layer, wherein the PCM layer is surrounded by the IMD layer, and wherein a top surface of the IMD layer is free of the PCM layer; and a top electrode on the PCM layer and on a top surface of the IMD layer. In one embodiment, the top electrode extends below a top surface of the IMD layer to contact the PCM layer. In one embodiment, the sidewalls of the PCM layer are in physical contact with the IMD layer. In one embodiment, the PCM layer comprises gesbte (gst). In one embodiment, the PCM layer is uniform in thickness.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a phase-change memory device, comprising:

forming a dielectric layer over a substrate, the dielectric layer having a top surface;

etching an opening in the dielectric layer;

forming a bottom electrode within the opening, the bottom electrode comprising a barrier layer;

forming a Phase Change Material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the phase change material layer is flush with or below the top surface of the dielectric layer; and

and forming a top electrode on the phase change material layer.

2. The method of claim 1, wherein sidewalls of the phase change material layer are free of the barrier layer.

3. The method of claim 1, wherein forming the bottom electrode comprises:

depositing the barrier layer in the opening;

depositing a conductive material on the barrier layer; and

etching the barrier layer and the conductive material, wherein the etching exposes sidewalls of the opening.

4. The method of claim 3, wherein the top surface of the conductive material bulges after etching the barrier layer and the conductive material.

5. The method of claim 3, wherein the top surface of the barrier layer is flush with the top surface of the conductive material after etching the barrier layer and the conductive material.

6. The method of claim 1, wherein forming the phase change material layer comprises:

depositing a phase change material over the bottom electrode and the dielectric layer; and

etching the phase change material to remove the phase change material from the top surface of the dielectric layer.

7. The method of claim 1, wherein the thickness of the bottom electrode is between 25% and 50% of the thickness of the dielectric layer.

8. The method of claim 1, wherein the thickness of the phase change material layer is between 30% and 70% of the thickness of the dielectric layer.

9. A method of forming a phase-change memory device, comprising:

depositing an inter-metal dielectric (IMD) layer over the first conductive feature;

forming the intermetal dielectric layer exposing the first conductive component;

forming a second conductive member in the opening;

performing a first etch-back process to recess the second conductive feature into the opening;

depositing a Phase Change Material (PCM) in the opening and over the second conductive feature;

performing a second etch-back process to remove an upper portion of the phase change material; and

depositing a conductive material on the phase change material.

10. A phase change memory device comprising:

a metallization layer over the semiconductor substrate;

an inter-metal dielectric (IMD) layer over the metallization layer; and

a Phase Change Random Access Memory (PCRAM) cell, the phase change random access memory cell comprising:

the bottom electrode is positioned in the intermetallic dielectric layer and is electrically connected with the metallization layer;

a Phase Change Material (PCM) layer on the bottom electrode and within the inter-metal dielectric layer, wherein the inter-metal dielectric layer surrounds the phase change material layer, and wherein a top surface of the inter-metal dielectric layer is free of the phase change material layer; and

a top electrode on the phase change material layer and on the top surface of the inter-metal dielectric layer.