CN101231961B - 内埋组件的基板制程 - Google Patents
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
一种内埋组件的基板制程,首先,提供一模具,该模具具有一表面及数个突起部,该些突起部形成于该表面上,接着,形成一第一介电层于该表面,该第一介电层并覆盖该些突起部,之后,设置至少一电子组件于该第一介电层,该电子组件具有一主动面及数个形成于该主动面的接点,该主动面朝向该第一介电层,该些接点对应于该些突起部,接着,形成一第二介电层于该第一介电层,之后,设置一载板于该电子组件的该背面,接着,进行一微压印步骤,其通过该模具的该些突起部使该第一介电层形成有数个开口,并且该些开口是对应该电子组件的该些接点,最后,移除该模具,以形成内埋组件的基板,因此本发明具有简化制程的功效,且该内埋组件的基板制程是以微压印步骤形成开口,可避免残留的蚀刻液污染。
Description
技术领域
本发明是有关于一种基板制程,特别是有关于一种内埋电子组件的基板制程。
背景技术
如图1所示,习知内埋组件的基板制程的流程图依序包含有「提供一载台」步骤1、「设置至少一电子组件于该载台」步骤2、「形成一第一介电层于该载台」步骤3、「设置一载板于该第一介电层」步骤4、「移除该载台」步骤5、「翻转该载板」步骤6、「清除残留的黏胶」步骤7、「形成一第二介电层于该第一介电层」步骤8、「以微影蚀刻法形成数个开口」步骤9、「形成一重分配线路层于该第二介电层」步骤10。首先,请参阅图1及图2A,在步骤1中,是提供一载台110,该载台110的一表面111是涂覆有一黏胶层112,接着,请参阅图1及图2B,在步骤2中,设置数个电子组件210于该载台110,每一电子组件210具有一主动面211、一背面212及数个接点213,该主动面211朝向该载台110的该表面111,该些接点213形成于该主动面211上,之后,请参阅图1及图2C,在步骤3中,形成一第一介电层220于该载台110,该第一介电层220是覆盖该些电子组件210,利用一整平步骤使该第一介电层220显露出该些电子组件210的该些背面212,接着,请参阅图1及图2D,在步骤4中,设置一载板230于该第一介电层220,该载板230是以一胶带231贴设于该第一介电层220与该些电子组件210的该些背面212,之后,请参阅图1及图2E,在步骤5中,移除该载台110,由于该载台110是以该黏胶层112使该些电子组件210固定于该载台110上,因此移除该载台110时会有黏胶的残留112’,之后,请参阅图1及图2F,在步骤6中,翻转该载板230,使该些电子组件210的该些主动面211朝上,接着,请参阅图1及图2G,在步骤7中,将残留于该些电子组件210的该些主动面211上的黏胶112’清除,之后,请参阅图1及图2H,在步骤8中,形成一第二介电层240于该第一介电层220并覆盖该些电子组件210的该些主动面211,接着,请参阅图1及图21,在步骤9中,以微影蚀刻法在该第二介电层240形成数个开口241以显露出该些电子组件210的该些接点213,最后,请参阅图1及图2J,在步骤10中,形成一重分配线路层250于该第二介电层240以形成该内埋组件的基板200,该重分配线路层250具有数个重分配垫251且该些重分配垫251是电性连接至该些电子组件210的该些接点213。然而习知内埋组件的基板制程步骤繁琐,且必须先将该些电子组件210黏设于该载台110,使得移除该载台110时会造成黏胶112的残留而污染该些主动面211,此外,以微影蚀刻法形成该些开口241时,该些接点213也容易受到化学药剂的污染或化学药剂残留于该些接点213或该第二介电层240上。
发明内容
本发明的主要目的是在于提供一种内埋组件的基板制程,首先,提供一模具,该模具的一表面形成有数个突起部,接着,形成一第一介电层于该表面并覆盖该些突起部,之后,设置至少一电子组件于该第一介电层,该电子组件的一主动面朝向该第一介电层,该电子组件的数个接点形成于该主动面上且该些接点对应于该些突起部,接着,形成一第二介电层于该第一介电层,之后,设置一载板于该电子组件上并进行一微压印步骤,以使该第一介电层形成有数个开口,并且该些开口是对应该电子组件的该些接点,最后,移除该模具,以形成内埋组件的基板,其具有简化制程的功效且由于该内埋组件的基板制程通过微压印步骤以形成开口,可避免残留的蚀刻液污染。
依本发明的一种内埋组件的基板制程,首先,提供一模具,该模具具有一表面及数个突起部,该些突起部形成于该表面上,接着,形成一第一介电层于该表面并覆盖该些突起部,之后,设置至少一电子组件于该第一介电层,该电子组件具有一主动面、一背面及数个接点,该主动面朝向该第一介电层,该些接点形成于该主动面上,其中该些接点对应于该些突起部,接着,形成一第二介电层于该第一介电层,之后,设置一载板于该电子组件上,接着,进行一微压印步骤,其通过该模具的该些突起部使该第一介电层形成有数个开口,并且该些开口是对应该电子组件的该些接点,最后,移除该模具。
本发明揭露的基板制程可避免残留的蚀刻液污染电子组件。
附图说明
图1:习知内埋组件的基板制程的流程图。
图2A至图2J:习知内埋组件的基板制程的截面示意图。
图3:依据本发明的一具体实施例,一种内埋组件的基板制程的流程图。
图4A至图4H:依据本发明的一具体实施例,该内埋组件的基板制程的截面示意图。
具体实施方式
请参阅图3,依据本发明的一具体实施例是揭示一种内埋组件的基板制程的流程图,其依序包含有「提供一模具」步骤21、「形成一第一介电层于该模具」步骤22、「设置至少一电子组件于该第一介电层」步骤23、「形成一第二介电层于该第一介电层」步骤24、「形成一载板于该电子组件」步骤25、「以微压印步骤形成数个开口」步骤26、「形成一重分配线路层于该第一介电层」步骤27。首先,请参阅图3及图4A,在步骤21中,提供一模具310,该模具310为一透明材质,该模具310具有一表面311及数个突起部312,该些突起部312形成于该表面311上,接着,请参阅图3及图4B,在步骤22中,形成一第一介电层410于该模具310的该表面311并覆盖该些突起部312,在本实施例中,该第一介电层410为半固化态的高分子材料,例如聚亚酰胺(polyimide,PI)、PBO(polybenzoxazole)材料或苯环丁烯(benzocyclobutene,BCB)。之后,请参阅图3及图4C,在步骤23中,设置至少一电子组件420于该第一介电层410上,该电子组件420系可为芯片或被动组件,该电子组件420具有一主动面421、一背面422及数个接点423,该主动面421朝向该第一介电层410,该些接点423形成于该主动面421上,其中该些接点423对应于该些突起部312,接着,请参阅图3及图4D,在步骤24中,形成一第二介电层430于该第一介电层410,在本实施例中,该第二介电层430是覆盖该电子组件420,该第二介电层是可为一封胶材料(Encapsulation),在此步骤中是可包含有利用一整平步骤,以使该第二介电层430显露该电子组件420的该背面422,较佳地,该第二介电层430是与该电子组件420的该背面422共平面,之后,请参阅图3及图4E,在步骤25中,设置一载板440于该电子组件420的该背面422上,该载板440是选自于硅基板或玻璃基板,在本实施例中,该载板440是以一胶带441贴设于该电子组件420的该背面422与该第二介电层430上。接着,请参阅图3及图4F,在步骤26中,于一真空设备B内进行一微压印步骤,其通过该模具310的该些突起部312使该第一介电层410形成有数个开口411,该些开口411是对应该电子组件420的该些接点423,此外,在该微压印步骤中更包含有加压、加热、抽真空以及以紫外光固化该第一介电层410。接着,请参阅图4G移除该模具310以形成一内埋组件的基板半成品400’,在移除该模具310后显露出该些开口411,该些开口411显露该些接点423。最后,请参阅图3及图4H,在步骤27中,形成一重分配线路层450于该第一介电层410上以完成一内埋组件的基板400.此外,其系可另包含有进行一移除该载板440、该胶带441及切割的步骤,以使该内埋组件的基板400为一芯片尺寸封装构造(Chip Scale Package,CSP),请再参阅图4H,该重分配线路层450具有数个重分配垫451,该些重分配垫451是电性连接至该电子组件420的该些接点423,此外在形成该重分配线路层450的步骤前是可以激光清除残留于该些接点423的污染物,以使该重分配线路层450确实与该些接点423电性连接。由于该内埋组件的基板制程是直接以该第一介电层410将该电子组件420固设于该模具310,防止黏胶的残留污染且制程简便,并利用微压印步骤以使该第一介电层410上形成有该些开口411以显露该些接点423,可避免残留的蚀刻液污染该电子组件420的该主动面421。
本发明的保护范围当视权利要求所界定者为准,任何熟知此项技艺者,在不脱离本发明的精神和范围内所作的任何变化与修改,均属于本发明的保护范围。
Claims (7)
1.一种内埋组件的封装制程,其是包含:
提供一模具,该模具具有一表面及数个突起部,该些突起部形成于该表面上;
形成一第一介电层于该表面并覆盖该些突起部;
设置至少一电子组件于该第一介电层,该电子组件具有一主动面、一背面及数个接点,该主动面朝向该第一介电层,该些接点形成于该主动面上,其中该些接点对应于该些突起部;
形成一第二介电层于该第一介电层上;
设置一载板于该电子组件的该背面上;
进行一微压印步骤,其通过该模具的该些突起部使该第一介电层形成有数个开口,该些开口是对应该电子组件的该些接点;
移除该模具以显露出该些开口,其中该些开口显露该些接点;以及
形成一重分配线路层于该第一介电层上,该重分配线路层具有数个重分配垫,该些重分配垫是电性连接至该电子组件的该些接点。
2.如权利要求1所述的内埋组件的封装制程,其中该第二介电层是覆盖该电子组件。
3.如权利要求2所述的内埋组件的封装制程,所述形成一第二介电层于该第一介电层上的步骤另包含有:利用一整平步骤使该第二介电层显露出该电子组件的该背面,使得该载板得以贴设于该背面。
4.如权利要求3所述的内埋组件的封装制程,其中该第二介电层与该电子组件的该背面是共平面。
5.如权利要求1所述的内埋组件的封装制程,其中在该微压印步骤中,是以紫外光固化该第一介电层。
6.如权利要求1所述的内埋组件的封装制程,其中该模具为一透明材质。
7.如权利要求1所述的内埋组件的封装制程,所述形成一重分配线路层于该第一介电层上的步骤另包含有:进行移除该载板的步骤。
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