CN101227147B - Direct current switch power supply control circuit - Google Patents
Direct current switch power supply control circuit Download PDFInfo
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- CN101227147B CN101227147B CN2008100578567A CN200810057856A CN101227147B CN 101227147 B CN101227147 B CN 101227147B CN 2008100578567 A CN2008100578567 A CN 2008100578567A CN 200810057856 A CN200810057856 A CN 200810057856A CN 101227147 B CN101227147 B CN 101227147B
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Abstract
The invention discloses a direct current switch power supply controlling circuit, which comprises a pulse-width modulating comparator, a controlling unit and a logic driving unit which are connected in turn, wherein output square-wave signals of the pulse-width modulating comparator are input in a first input end of the controlling unit, maximum duty cycle square-wave signal is input in a second input end, the output end is connected with the input end of the logic driving unit, when the duty cycle of output square-wave of the pulse-width modulating comparator which is input is lager than the maximum duty cycle, the controlling outputs the square-wave with 100% duty cycle. The direct current switch power supply controlling circuit realizes smooth conversion from the maximum duty cycle to 100% duty cycle through improving the controlling unit circuit of a power supply controlling circuit, which increases respond speed of the circuit, reduces ripple of output voltage in the process of conversation of the circuit from the maximum duty cycle mode to 100% duty cycle mode, the design of the circuit is simple, and the cost of circuit reconstruction is saved.
Description
Technical field
The present invention relates to the electronic circuit technology field, relate in particular to a kind of direct current switch power supply control circuit.
Background technology
The DC control switch power control circuit mainly comprises pulse width modulation (Pulse-widthModulation, hereinafter to be referred as pulse-width modulation or PWM) comparator, control switch and output lc circuit, described PWM comparator is used for the square-wave signal of the input signal generation different duty of its input of comparison, the square-wave signal that the PWM comparator produces is used for the closure and the shutoff of drive controlling switch, described control switch is used for when it is closed input voltage being inserted lc circuit, when it turn-offs, cut off the energy that is connected and discharges lc circuit of input voltage and lc circuit, described lc circuit comprises inductance that is connected with control switch and the electric capacity of connecting with described inductance, and the node voltage of the connected node of described inductance and electric capacity is used as output voltage.
The basic functional principle of described DC control switch power control circuit is exactly under the situation that input voltage changes, inner parameter changes or external load changes, control circuit carries out closed loop feedback by the difference of controlled signal and reference signal, the conducting pulse duration of regulation control switch makes output voltage remain unchanged.
In adopting battery powered direct-current switch power supply system,,, also need the switching power source control circuit can be at operation at low power supply voltage except needs improve the system effectiveness as far as possible in order to utilize the energy of battery to greatest extent.For the step-down type dc Switching Power Supply, under the situation that output voltage is fixed, this just needs control switch to have big as far as possible duty ratio.When input voltage and output voltage pressure reduction are very little, need control switch almost to be in conducting state always, to keep the constant of output voltage.This technology i.e. 100% duty ratio control technology, and the state when also circuit being in 100% duty ratio in some products is called the LDO pattern.
As shown in Figure 1, the DC control switch power control circuit comprises error amplifier (ErrorAmplifier) 10, outputting inductance 60 and output capacitance 70, bleeder circuit 80 and the control unit 100 of saw-toothed wave generator (Ramp Generator) 20, PWM comparator 30, logical drive unit 40, control switch 50, series connection.The positive input of described error amplifier (Error Amplifier) 10 is imported a reference voltage V
Ref, also being called reference voltage, reverse input end is imported output voltage V
OutThe feedback voltage V that dividing potential drop obtains
FB, described error amplifier 10 is with feedback voltage V
FBAnd reference voltage V
RefRelatively and with comparative result suitably amplify with output voltage V
EAODescribed saw-toothed wave generator 20 is used to produce stable sawtooth signal.The reverse input end of PWM comparator 30 is imported described sawtooth signal, the output signal of positive input error originated from input amplifier.PWM comparator 30 is used for sawtooth waveforms and voltage V
EAOCompare exporting the square-wave signal of certain duty ratio, this square-wave signal by control unit and logical drive unit after, as the switch controlling signal of described control switch 50.When the sawtooth signal current potential is lower than voltage V
EAOPWM comparator output high level signal in the time of current potential is when the sawtooth signal current potential is higher than voltage V
EAOPWM comparator output low level signal in the time of current potential.By adjusting voltage V
EAOThe current potential height duty ratio that just can regulate whole output square wave, the shutoff of just having adjusted control switch 50 and then is controlled the output voltage V of pwm control circuit constantly
Out
Described control switch 50 by a PMOS manage, NMOS pipe forms, described PMOS manages and links to each other the source electrode of described PMOS pipe and input voltage V respectively with logical drive unit 40 with the grid of NMOS pipe
InConnect, the source electrode of described NMOS pipe is connected with ground, described PMOS pipe is connected with the drain electrode of NMOS pipe and links to each other with outputting inductance 60 as the output of control switch 50, the other end ground connection of the output capacitance 70 of connecting with outputting inductance 60, outputting inductance 60 is drawn the output voltage V of making pwm control circuit with the voltage of the connected node of output capacitance 70
Out, described output voltage V
OutObtain aforementioned feedback voltage V through bleeder circuit 80
FBDescribed bleeder circuit 80 is by being connected on output voltage V
OutAnd the first divider resistance R between the ground
1With the second divider resistance R
2Form described R
1And R
2Intermediate node voltage as feedback voltage V
FB
As input voltage V
InUnder the situation that variation or external load change, described feedback voltage V
FBMay produce fluctuation, error amplifier 10 is with the feedback voltage V of fluctuation
FBWith reference voltage V
RefRelatively and with comparative result suitably amplify by adjusting voltage V
EAOWith the duty of control output square wave when control switch 50 shutoff constantly, and then the output voltage V of control pwm control circuit
OutConverge on a fiducial value, at this moment feedback voltage V
FBWith reference voltage V
RefBetween difference be zero, so this output voltage V
OutFiducial value and reference voltage V
RefDirectly related.
Be illustrated in figure 2 as the schematic diagram of another direct current switch power supply control circuit in the prior art, with Fig. 1 difference be that the reverse input end of PWM comparator is sawtooth waveforms and the feedback current voltage V that saw-toothed wave generator produces
IFBThe signal sum, feedback current voltage V
IFBSignal is the signal that returns by amplifier the feedback circuit 90 from the control switch output, the variation of reflection outputting inductance 60 current peaks.
As depicted in figs. 1 and 2, the output signal of the first input end input PWM comparator 30 of control unit 100, second input is imported the maximum duty cycle control signal (MAX_PWM square wave) that the first square wave maker (not drawing in the accompanying drawing) produces, the 3rd input is imported the minimum duty cycle control signal (MIN_PWM square wave) that the second square wave maker (not drawing in the accompanying drawing) produces, four-input terminal (the positive input V of the input of LDO mode detection module and PWM comparator that links to each other with the output of LDO pattern (referring to very duty cycle mode) detection module
EAOLink to each other), the control unit output links to each other with the input of logical drive unit 40.MAX_PWM square wave and MIN_PWM square wave and sawtooth signal are synchronous, the rising edge of the corresponding MIN_PWM square wave of the rising edge of MAX_PWM square wave.The duty ratio of MAX_PWM square wave is the circuit maximum duty cycle, and the duty ratio of MIN_PWM square wave is the circuit minimum duty cycle, and generally speaking, the operating rate of circuit is depended in the setting of the occurrence of circuit maximum duty cycle and circuit minimum duty cycle.During the initialization circuit maximum duty cycle, need guarantee that the low duration of correspondence in a clock cycle must be finished the operating time of turn-offing PMOS pipe and conducting NMOS pipe greater than circuit; During the initialization circuit minimum duty cycle, need guarantee that the high level lasting time of correspondence in a clock cycle must be finished the operating time that conducting PMOS managed and turn-offed the NMOS pipe greater than circuit.The high level lasting time of the low duration of circuit maximum duty cycle correspondence and circuit minimum duty cycle correspondence is traditionally arranged to be 5%～10% of the clock cycle in a clock cycle.Generally, if there is not the control of LDO pattern, in one-period, when the duty ratio of square-wave signal D1 reached maximum duty cycle, circuit can be forced PMOS is turn-offed, and that is to say, if there is not the control of LDO pattern, the maximum duty cycle of D1 signal necessarily is less than or equal to the duty ratio of MAX_PWM.
The circuit of control unit 100 as shown in Figure 3, comprise one or, a NAND gate, with a rest-set flip-flop, wherein, or two inputs of door are imported signal LDO_MODE and maximum duty cycle square-wave signal MAX_PWM that the LDO mode detection module produces respectively, two inputs of NAND gate are imported respectively or the output signal of door and the output signal D of PWM comparator, the output signal of the S end input nand gate of rest-set flip-flop, R end input minimum duty cycle square-wave signal MIN_PWM, the inverse output terminal of rest-set flip-flop is the output of control unit, and output signal is represented by D1.
In foregoing circuit, the duty ratio that supposing the system needs is 97%, and the maximum duty cycle of circuit is 95%, and output voltage will descend owing to the underpower that power supply provides so, thereby causes V
EAORise, work as V
EAOValue when being higher than very the duty cycle mode threshold value, LDO mode detection module output signal LDO_MODE is a high level, circuit forces to enter very duty cycle mode according to this high level signal, mask the control of maximum duty cycle signal MAX_PWM to the circuit maximum duty cycle, force PMOS to manage conducting always, raise up to output voltage, make V
EAODrop to very below the duty cycle mode threshold value, just enter normal control.Sequential chart is as shown in Figure 4 worked as V
EAOLDO_MODE is a high level when being higher than very the duty cycle mode threshold value, V
EAOLDO_MODE is a low level when being lower than very the duty cycle mode threshold value, and control circuit entered very duty cycle mode when LDO_MODE was high level.Wherein very the value of duty cycle mode threshold value minimum is the voltage of sawtooth waveforms of the trailing edge position correspondence of MAX_PWM square wave, but since the existence of hardware process deviation, LDO pattern V
EAOThe voltage place of threshold value sawtooth waveforms of the trailing edge position correspondence of above-mentioned MAX_PWM square wave can not be arranged on operate as normal the time, simultaneously because the needs of system's loop compensation, the bandwidth of error amplifier is generally lower, V
EAOBe a low frequency signal, thereby cause V
EAOIt is longer that value is elevated to time of this threshold value.
In said process, the defective that exists in the circuit in the prior art comprises:
(1) in the prior art at the square wave of input logic driver element in the maximum duty cycle pattern with when very changing between the duty cycle mode, the ripple of circuit output voltage obviously increases.
(2) V
EAOAmplitude of variation very big because the bandwidth of error amplifier is narrower, responding this bigger amplitude of variation needs the long period, causes the circuit response speed slow.
(3) circuit is in the maximum duty cycle pattern with when very switching between duty cycle mode, and the square wave of input logic driver element exists tangible state to change, and is easily affected by noise and unstable.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of direct current switch power supply control circuit, makes circuit in the maximum duty cycle pattern with when very changing between duty cycle mode, improves the reaction speed of circuit, reduces the ripple of circuit output voltage.
In order to address the above problem, the invention provides a kind of direct current switch power supply control circuit, comprise the pulse-width modulation comparator, control unit and the logical drive unit that link to each other successively, the first input end of described control unit is imported the output square-wave signal of described pulse-width modulation comparator, second input input maximum duty cycle square-wave signal, output links to each other with the input of described logical drive unit, described control unit during greater than maximum duty cycle, is exported the very square wave of duty ratio in the duty ratio of the pulse-width modulation comparator output square wave of input.
Further, when described control unit is less than or equal to maximum duty cycle in the duty ratio of the square wave of the pulse-width modulation comparator output of input, output and the identical square wave of pulse-width modulation comparator output square wave.
Further, described control unit also comprises the 3rd input of an input minimum duty cycle square-wave signal, and described control unit comprises first rest-set flip-flop and second rest-set flip-flop, and the output signal of described control unit and the relation of input signal satisfy following formula:
Wherein, D1 represents the output signal of control unit at present clock period, and D represents the input signal of the first input end of described control unit, and max represents the input signal of second input of described control unit, min represents the input signal of the 3rd input of described control unit, Q
1 nRepresent that the Q output of first rest-set flip-flop is at the output signal of last clock cycle, Q
2 nRepresent the Q output of second rest-set flip-flop in the output signal of last clock cycle, " " presentation logic operator " with ", "+" presentation logic operator " or ", "-" presentation logic operator " non-".
Further, described control unit also comprises and door, or door, first not gate and second not gate, the described first not gate input is the first input end of described control unit, the output of first not gate links to each other with the S end of described second rest-set flip-flop, the R end of described second rest-set flip-flop is the 3rd input of described control unit, the input of described second not gate is second input of described control unit, the output of second not gate links to each other with an input of door with described, the inverse output terminal of described second rest-set flip-flop links to each other with another input of door with described, the described end with the S of first rest-set flip-flop with the output of door links to each other, the R end of first rest-set flip-flop links to each other with the 3rd input, the forward output of first rest-set flip-flop links to each other with an input described or door, the inverse output terminal of second rest-set flip-flop links to each other with another input described or door, and output described or door is the output of control unit.
Further, described rest-set flip-flop satisfies following logical relation:
Wherein, Q
N+1Be the output signal of the Q of rest-set flip-flop end at present clock period, S represents the input signal of rest-set flip-flop S end, and R represents the input signal of rest-set flip-flop R end, Q
nThe Q end of expression rest-set flip-flop is in the output signal of last clock cycle.
The present invention also provides a kind of square-wave signal has been carried out the control circuit that duty ratio is adjusted, the pending square-wave signal of first input end input of described control circuit, second input input maximum duty cycle square-wave signal; Described control circuit during greater than the circuit maximum duty cycle, is exported the very square wave of duty ratio in the duty ratio of the square-wave signal of first input end input.
Further, when described control circuit is less than or equal to the circuit maximum duty cycle in the duty ratio of the square-wave signal of first input end input, export the square wave identical with described square-wave signal.
Further, described control circuit also comprises the 3rd input of an input minimum duty cycle square-wave signal, and described control circuit comprises first rest-set flip-flop and second rest-set flip-flop, and the output signal of described control circuit and the relation of input signal satisfy following formula:
Wherein, D1 represents the output signal of control circuit at present clock period, and D represents the input signal of the first input end of described control circuit, and A represents the input signal of second input of described control circuit, B represents the input signal of the 3rd input of described control circuit, Q
1 nRepresent that the Q output of first rest-set flip-flop is at the output signal of last clock cycle, Q
2 nRepresent the Q output of second rest-set flip-flop in the output signal of last clock cycle, " " presentation logic operator " with ", "+" presentation logic operator " or ", "-" presentation logic operator " non-".
Further, described control circuit also comprises and door, or door, first not gate and second not gate, the described first not gate input is the first input end of described control circuit, the output of first not gate links to each other with the S end of described second rest-set flip-flop, the R end of described second rest-set flip-flop is the 3rd input of described control circuit, the input of described second not gate is second input of described control circuit, the output of second not gate links to each other with an input of door with described, the inverse output terminal of described second rest-set flip-flop links to each other with another input of door with described, the described end with the S of first rest-set flip-flop with the output of door links to each other, the R end of first rest-set flip-flop links to each other with the 3rd input, the forward output of first rest-set flip-flop links to each other with an input described or door, the inverse output terminal of second rest-set flip-flop links to each other with another input described or door, and output described or door is the output of control circuit.
Further, described rest-set flip-flop satisfies following logical relation:
Wherein, S represents the input signal of rest-set flip-flop S end, and R represents the input signal of rest-set flip-flop R end, Q
nThe Q end of expression rest-set flip-flop is at the output signal of last clock cycle, Q
N+1Be the output signal of the Q of rest-set flip-flop end at present clock period.
Among the present invention,, reduce V by improving the control unit circuit in the power control circuit
EAOAmplitude of variation, improved the reaction speed of circuit, reduced circuit at maximum duty cycle pattern and the ripple of output voltage in the transfer process between duty cycle mode very, realized the level and smooth conversion of maximum duty cycle to 100% duty ratio, and circuit design is simple, has saved the cost of circuit modification.
Description of drawings
Fig. 1 is the schematic diagram of direct current switch power supply control circuit in the prior art;
Fig. 2 is the schematic diagram of another direct current switch power supply control circuit in the prior art;
Fig. 3 is the circuit theory diagrams of control unit in the prior art;
Fig. 4 is the sequential schematic diagram of sawtooth waveforms in the circuit of prior art, MAX_PWM, MIN_PWM, signal D, LDO_MODE and signal D1;
Fig. 5 is the schematic diagram of direct current switch power supply control circuit in the present embodiment;
Fig. 6 is the circuit theory diagrams of control unit in the present embodiment;
Fig. 7 is the logical schematic of rest-set flip-flop in the control unit circuit in the present embodiment;
Fig. 8 is the sequential schematic diagram of sawtooth waveforms, MAX_PWM, MIN_PWM, signal D, LDO_MODE and signal D1 in the circuit in the present embodiment.
Embodiment
The present invention improves the control unit circuit of power control circuit, and control unit during greater than the circuit maximum duty cycle, is exported the very square wave of duty ratio in the duty ratio of the pulse-width modulation comparator output square wave of input; When being less than or equal to maximum duty cycle, output is exported the identical square wave of square wave with the pulse-width modulation comparator in the duty ratio of the square wave of pulse-width modulation comparator output, thereby the control switch circuit is in time according to V
EAOVariation carry out switch control, reduce V
EAOAmplitude of variation, thereby improve the reaction speed of circuit, the output ripple of output voltage when reducing circuit from the maximum duty cycle pattern to duty cycle mode conversion very.
As shown in Figure 5, do not comprise the LDO mode detection module in the direct current switch power supply control circuit of the present invention, its control unit has three inputs and an output.The output signal of first input end input PWM comparator, second input input maximum duty cycle square wave (MAX_PWM square wave), the 3rd input input minimum duty cycle square wave (MIN_PWM square wave), output links to each other with the input of logical drive unit.
Wherein, control unit realizes that with logical circuit the control unit logical circuit comprises two rest-set flip-flops i.e. first rest-set flip-flop and second rest-set flip-flop, and the control unit logical circuit is used to realize following control logic:
Wherein, D represents the input signal (being the output signal of pulse-width modulation comparator) of first input end, max represents the input signal (being the maximum duty cycle square-wave signal) of second input, and min represents the input signal (being the minimum duty cycle square-wave signal) of the 3rd input, Q
1 nRepresent that the Q output of first rest-set flip-flop is at the output signal of last clock cycle, Q
2 nRepresent the output signal of the Q output of second rest-set flip-flop in the last clock cycle, D1 represents the output signal of control unit at present clock period, " " presentation logic operator " with ", "+" presentation logic operator " or ", "-" presentation logic operator " non-".
In specific embodiment, the specific implementation circuit of control unit as shown in Figure 6, control unit circuit is except comprising first rest-set flip-flop and second rest-set flip-flop, also comprise and door, or door, first not gate and second not gate, the described first not gate input is the first input end of described control unit, the output of first not gate links to each other with the S end of described second rest-set flip-flop, the R end of described second rest-set flip-flop is the 3rd input of described control unit, the input of described second not gate is second input of described control unit, the output of second not gate links to each other with an input of door with described, the inverse output terminal of described second rest-set flip-flop links to each other with another input of door with described, the described end with the S of first rest-set flip-flop with the output of door links to each other, the R end of first rest-set flip-flop links to each other with the 3rd input, the forward output of first rest-set flip-flop links to each other with an input described or door, the inverse output terminal of second rest-set flip-flop links to each other with another input described or door, and output described or door is the output of control unit.
As shown in Figure 7, the rest-set flip-flop in the control unit circuit satisfies following logical relation:
In specific embodiment, as shown in Figure 4, maximum duty cycle as power circuit is 95%, and the outer welding system of circuit to need the duty ratio of the square wave of input logic driver element in the power circuit be 97.5%, the 97.5% duty ratio implementation that outer welding system needs is: the duty ratio of the square wave D1 of input logic driver element is along with time go forward one by one (for the clock cycle) is followed successively by 95%, 95%, 95%, .... (N individual 95%), 100%, 100%, 100%... (N individual 100%), 95%, 95%...... and the like, wherein the number of N depends on V
EAOBe elevated to LDO pattern V
EAOThe time of threshold value, said method causes V in the circuit
EAOAmplitude of variation bigger, thereby the ripple of circuit output voltage is bigger, and the reaction of circuit is slower.As shown in Figure 8, adopt circuit of the present invention, the duty ratio of the square wave D1 of input logic driver element is followed successively by 100%, 95%, 100%, 95%, 100% and the like, V in the circuit
EAOAmplitude of variation less, thereby the ripple of circuit output voltage is less, the reaction of circuit is very fast, the output of the square wave of input logic driver element is stable.
Adopt this gross data of maximum duty cycle (95%) in the above-mentioned example in the duty ratio output sequence of square wave D1, main consideration is convenient to explain method of the present invention.In actual applications, the duty ratio output sequence of square wave D1 may be to occur two 100% duty ratios continuously, situation or other situation of the square wave of one 94% (or other is less than value of maximum duty cycle) duty ratio appears in the back, by ruuning situation decision in the side circuit.
Other are in the implementation of the duty ratio between maximum duty cycle (95%) and 100% duty ratio and said method in like manner.
The present invention is equally applicable to the improvement to circuit in the prior art shown in Figure 2.
In addition, above-mentioned control unit circuit can also be carried out the control circuit that duty ratio is adjusted to square-wave signal as a kind of, the square-wave signal that the first input end input is pending, second input input maximum duty cycle square-wave signal; The 3rd input input minimum duty cycle square-wave signal, its controlled function is as indicated above, repeats no more herein.
The present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making various corresponding changes and distortion according to the present invention, and these change and be out of shape the protection range that all should belong to the appended claim of the present invention accordingly.
Claims (8)
1. direct current switch power supply control circuit, comprise the pulse-width modulation comparator, control unit and the logical drive unit that link to each other successively, the first input end of described control unit is imported the output square-wave signal of described pulse-width modulation comparator, second input input maximum duty cycle square-wave signal, output links to each other with the input of described logical drive unit, it is characterized in that
Described control unit during greater than maximum duty cycle, is exported the very square wave of duty ratio in the duty ratio of the pulse-width modulation comparator output square wave of input;
Described control unit also comprises the 3rd input of an input minimum duty cycle square-wave signal, and described control unit comprises first rest-set flip-flop and second rest-set flip-flop, and the output signal of described control unit and the relation of input signal satisfy following formula:
Wherein, D1 represents the output signal of control unit at present clock period, and D represents the input signal of the first input end of described control unit, and max represents the input signal of second input of described control unit, min represents the input signal of the 3rd input of described control unit
Represent the Q output of first rest-set flip-flop in the output signal of last clock cycle,
Represent the Q output of second rest-set flip-flop in the output signal of last clock cycle, " " presentation logic operator " with ", "+" presentation logic operator " or ", "-" presentation logic operator " non-".
2. direct current switch power supply control circuit as claimed in claim 1 is characterized in that,
When described control unit is less than or equal to maximum duty cycle in the duty ratio of the square wave of the pulse-width modulation comparator output of input, output and the identical square wave of pulse-width modulation comparator output square wave.
3. direct current switch power supply control circuit as claimed in claim 1 or 2 is characterized in that,
Described control unit also comprises and door, or door, first not gate and second not gate, the described first not gate input is the first input end of described control unit, the output of first not gate links to each other with the S end of described second rest-set flip-flop, the R end of described second rest-set flip-flop is the 3rd input of described control unit, the input of described second not gate is second input of described control unit, the output of second not gate links to each other with an input of door with described, the inverse output terminal of described second rest-set flip-flop links to each other with another input of door with described, the described end with the S of first rest-set flip-flop with the output of door links to each other, the R end of first rest-set flip-flop links to each other with the 3rd input, the forward output of first rest-set flip-flop links to each other with an input described or door, the inverse output terminal of second rest-set flip-flop links to each other with another input described or door, and output described or door is the output of control unit.
4. direct current switch power supply control circuit as claimed in claim 3 is characterized in that,
Described rest-set flip-flop satisfies following logical relation:
Wherein, Q
N+1Be the output signal of the Q of rest-set flip-flop end at present clock period, S represents the input signal of rest-set flip-flop S end, and R represents the input signal of rest-set flip-flop R end, Q
nThe Q end of expression rest-set flip-flop is in the output signal of last clock cycle.
5. the control circuit that square-wave signal is carried out the duty ratio adjustment is characterized in that,
The pending square-wave signal of first input end input of described control circuit, second input input maximum duty cycle square-wave signal; Described control circuit during greater than the circuit maximum duty cycle, is exported the very square wave of duty ratio in the duty ratio of the square-wave signal of first input end input;
Described control circuit also comprises the 3rd input of an input minimum duty cycle square-wave signal, and described control circuit comprises first rest-set flip-flop and second rest-set flip-flop, and the output signal of described control circuit and the relation of input signal satisfy following formula:
Wherein, D1 represents the output signal of control circuit at present clock period, and D represents the input signal of the first input end of described control circuit, and A represents the input signal of second input of described control circuit, B represents the input signal of the 3rd input of described control circuit
Represent the Q output of first rest-set flip-flop in the output signal of last clock cycle,
Represent the Q output of second rest-set flip-flop in the output signal of last clock cycle, " " presentation logic operator " with ", "+" presentation logic operator " or ", "-" presentation logic operator " non-".
6. control circuit as claimed in claim 5 is characterized in that,
When described control circuit is less than or equal to the circuit maximum duty cycle in the duty ratio of the square-wave signal of first input end input, export the square wave identical with described square-wave signal.
7. as claim 5 or 6 described control circuits, it is characterized in that,
Described control circuit also comprises and door, or door, first not gate and second not gate, the described first not gate input is the first input end of described control circuit, the output of first not gate links to each other with the S end of described second rest-set flip-flop, the R end of described the 2nd Rs trigger is the 3rd input of described control circuit, the input of described second not gate is second input of described control circuit, the output of second not gate links to each other with an input of door with described, the inverse output terminal of described second rest-set flip-flop links to each other with another input of door with described, the described end with the S of first rest-set flip-flop with the output of door links to each other, the R end of first rest-set flip-flop links to each other with the 3rd input, the forward output of first rest-set flip-flop links to each other with an input described or door, the inverse output terminal of second rest-set flip-flop links to each other with another input described or door, and output described or door is the output of control circuit.
8. control circuit as claimed in claim 7 is characterized in that,
Described rest-set flip-flop satisfies following logical relation:
Wherein, S represents the input signal of rest-set flip-flop S end, and R represents the input signal of rest-set flip-flop R end, Q
nThe Q end of expression rest-set flip-flop is at the output signal of last clock cycle, Q
N+1Be the output signal of the Q of rest-set flip-flop end at present clock period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100578567A CN101227147B (en) | 2008-02-19 | 2008-02-19 | Direct current switch power supply control circuit |
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| CN2008100578567A CN101227147B (en) | 2008-02-19 | 2008-02-19 | Direct current switch power supply control circuit |
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| CN101227147A CN101227147A (en) | 2008-07-23 |
| CN101227147B true CN101227147B (en) | 2011-09-14 |
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Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5381014B2 (en) * | 2008-10-29 | 2014-01-08 | ミツミ電機株式会社 | DC-DC converter |
| CN101841226B (en) * | 2009-03-17 | 2012-09-19 | 立锜科技股份有限公司 | Power supply circuit for improving transient variation reaction, control circuit and method thereof |
| CN101860188B (en) * | 2010-06-07 | 2013-08-28 | 鸿富锦精密工业（深圳）有限公司 | Switch power supply circuit |
| CN101867299B (en) * | 2010-07-20 | 2012-03-21 | 周光友 | Circuit and method for switch power supply feedback voltage detection and sampling and holding |
| CN103311893B (en) * | 2012-03-12 | 2017-03-15 | 上海华虹集成电路有限责任公司 | The current foldback circuit of Switching Power Supply |
| CN102843828B (en) * | 2012-08-06 | 2014-05-14 | 电子科技大学 | Pulse width modulation (PMW) modulator circuit |
| CN102832800B (en) * | 2012-09-19 | 2015-02-04 | 北京新雷能科技股份有限公司 | Synchronous rectification converter |
| CN102933003B (en) * | 2012-11-20 | 2014-07-09 | 无锡中星微电子有限公司 | Dimming circuit |
| CN103151915A (en) * | 2013-02-20 | 2013-06-12 | 合肥京东方光电科技有限公司 | Direct current (DC)/DC convertor, voltage modulating method and display device |
| CN103227566B (en) * | 2013-04-22 | 2015-08-26 | 华为技术有限公司 | A kind of DC-DC converter |
| CN107404217B (en) * | 2017-08-18 | 2023-06-23 | 杰华特微电子股份有限公司 | Switching power supply control circuit and method and switching power supply |
| CN110112037B (en) * | 2019-04-18 | 2021-06-11 | 深圳南云微电子有限公司 | Contactor power-saving circuit |
| CN112467976B (en) * | 2019-09-09 | 2022-02-15 | 圣邦微电子（北京）股份有限公司 | Switch converter and control circuit and control method thereof |
| CN111124026B (en) * | 2019-12-31 | 2021-09-03 | 龙迅半导体（合肥）股份有限公司 | Data switch and data transmission system |
| CN113437874B (en) * | 2021-08-26 | 2021-11-23 | 上海泰矽微电子有限公司 | BUCK switch converter with inductance minimum current control circuit |
| CN113708626B (en) * | 2021-10-28 | 2022-02-08 | 南京模砾半导体有限责任公司 | Hundred percent duty cycle generating circuit suitable for COT voltage converter |
| CN115811207B (en) * | 2023-01-31 | 2023-05-09 | 深圳市思远半导体有限公司 | Switching power supply control circuit, and switching power supply, chip and equipment with switching power supply control circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6198264B1 (en) * | 1999-01-21 | 2001-03-06 | Fijitsu Limited | Maximum duty ratio setting circuit for a DC-DC converter |
| CN1435943A (en) * | 2002-02-01 | 2003-08-13 | 精工电子有限公司 | Pulse width modulating switch adjustor and electronic device |
| CN1897440A (en) * | 2006-06-30 | 2007-01-17 | 北京中星微电子有限公司 | Circuit for controlling switch power supply |
-
2008
- 2008-02-19 CN CN2008100578567A patent/CN101227147B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6198264B1 (en) * | 1999-01-21 | 2001-03-06 | Fijitsu Limited | Maximum duty ratio setting circuit for a DC-DC converter |
| CN1435943A (en) * | 2002-02-01 | 2003-08-13 | 精工电子有限公司 | Pulse width modulating switch adjustor and electronic device |
| CN1897440A (en) * | 2006-06-30 | 2007-01-17 | 北京中星微电子有限公司 | Circuit for controlling switch power supply |
Non-Patent Citations (3)
| Title |
|---|
| JP特开2002-9596A 2002.01.11 * |
| JP特开2006-101589A 2006.04.13 * |
| 全文. * |
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