CN102843828B - Pulse width modulation (PMW) modulator circuit - Google Patents

Pulse width modulation (PMW) modulator circuit Download PDF

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Publication number
CN102843828B
CN102843828B CN201210277070.2A CN201210277070A CN102843828B CN 102843828 B CN102843828 B CN 102843828B CN 201210277070 A CN201210277070 A CN 201210277070A CN 102843828 B CN102843828 B CN 102843828B
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input
comparator
output
nmos pipe
pipe
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CN201210277070.2A
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CN102843828A (en
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周泽坤
王鑫
张竹贤
吴传奎
石跃
明鑫
张波
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电子科技大学
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Abstract

The invention discloses a pulse width modulation (PMW) modulation circuit which specifically comprises a first transmission door, a first current comparer, a first alternative selector, a reset set (RS) trigger, two input nor gates, a phase inverter, a first N-channel metal oxide semiconductor (NMOS) tube, an error accumulation capacitor and a comparer with the selection function. The PMW modulator circuit can certainly modulate external input PWM signals according to current actually flowing through a light-emitting diode (LED), the duty ratio is adjusted, the duty ratio of the PWM signals actually participating in dimming in the circuit can be dynamically and correspondingly modulated as actual current change of the LED, and a signal driving switch of the LED is controlled to enable the luminance of the LED in all digital pulse periods to be equal to a preset value to improve PME dimming accuracy.

Description

A kind of PWM modulation circuit

Technical field

The invention belongs to integrated circuit fields, the design of a kind of PWM modulation circuit of specific design, improves the precision of PWM light modulation for LED-backlit chip.

Background technology

PWM light modulation is as a kind of important dimming mode of LED-backlit chip, has the advantage that application is simple, efficiency is high, and in addition, with respect to simulation light modulation, PWM light modulation also has precision high, and linearisation is good, without advantages such as colour casts.But there is following problem in traditional PWM light modulation:

(1), in the time that multi-string LED is applied, because the property difference of LED causes the upper electric current of every string LED different, make the brightness between LED lamp string within each light modulation cycle produce deviation.

(2) because the foundation of system loop needs the regular hour (as shown in Figure 1: wherein the output signal COMP of error amplifier represents system loop process of establishing), in the time opening LED, can inevitably introduce so the loss of brightness, cause PWM light modulation precision to reduce.

Summary of the invention

The object of the invention is the problems referred to above that exist in order to solve conventional P WM light modulation, proposed a kind of PWM modulation circuit.

Technical scheme of the present invention is: a kind of PWM modulation circuit, specifically comprise: the first transmission gate, the first current comparator, the first alternative selector, rest-set flip-flop, two are inputted NOR gate, inverter, a NMOS pipe, accumulation of error electric capacity and had the comparator of selection function, wherein

Outside pwm signal is as the input signal of described inverter, input termination first reference voltage source of described the first transmission gate, the output of control termination inverter of the first transmission gate and the grid of a NMOS pipe, the source electrode of the one NMOS pipe is received earth potential, the drain electrode of the one NMOS pipe, the output of the first transmission gate are connected with the first input end of the first current comparator, the sampled signal of the second input termination external loading of the first current comparator; The output of the first-class comparator of electricity is connected to earth potential by accumulation of error electric capacity lotus root, and the output of the first current comparator is connected with the first input end of the comparator with selection function, second input termination second reference voltage source with the comparator of selection function, the selecting side with the comparator of selection function is connected with the control end of alternative selector for inputting outside digital controlled signal; The output with the comparator of selection function is connected with the first input end of two input NOR gate, the pwm signal of the second input termination outside of two input NOR gate, S end and the first alternative selector first input end of rest-set flip-flop; The R end of rest-set flip-flop is connected with the output of two input NOR gate, and the output of rest-set flip-flop is connected with the second input of the first alternative selector, and the output of the first alternative selector is as the output of described PWM modulation circuit.

Further, described the first current comparator comprises the first operational amplifier, the second operational amplifier, the first resistance, the second resistance, a PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe and the 5th NMOS pipe, wherein, the positive input of the first operational amplifier is as the first input end of described the first current comparator, and the source electrode of the source electrode of the source electrode of a PMOS pipe, the 2nd PMOS pipe, the source electrode of the 3rd PMOS pipe and the 4th PMOS pipe is all connected with outside supply voltage; The grid of the one PMOS pipe is connected with grid, the drain electrode of a PMOS pipe and the drain electrode of the 5th NMOS pipe of the 2nd PMOS pipe; The drain electrode of the 2nd PMOS pipe is connected as the output of described the first current comparator with the drain electrode of the 3rd NMOS pipe; The grid of the 3rd PMOS pipe, the grid of the 4th PMOS pipe, the drain electrode of the 4th PMOS pipe and the drain electrode of the 2nd NMOS pipe are connected, the grid of the 2nd NMOS pipe is connected with the output of the second operational amplifier, the source electrode of the 2nd NMOS pipe is connected with the negative input of the second operational amplifier and is connected to earth potential by the second resistance lotus root, and the positive input of the second operational amplifier is as the second input of described the first current comparator; The drain electrode of the 3rd PMOS pipe, the grid of the 4th NMOS pipe, the drain electrode of the 4th NMOS pipe and the grid of the 3rd NMOS pipe link together; The source electrode lotus root of the source electrode of the 3rd NMOS pipe and the 4th NMOS pipe is connected to earth potential; The grid of the 5th NMOS pipe is connected with the output of the first operational amplifier, and the source electrode of the 5th NMOS pipe is connected with the negative input of the first operational amplifier and is connected to earth potential by the first resistance lotus root.

Further, the described comparator with selection function comprises: voltage comparator, the second out gate, the second alternative selector, the 3rd resistance and the 4th resistance, wherein, the negative input of voltage comparator be connected with the input of the second out gate and the first terminal of the 3rd resistance and as described in there is the second input of the comparator of selection function; The first input end of the second alternative selector is connected with the second terminal of the 3rd resistance and the first terminal of the 4th resistance, and the second terminal lotus root of the 4th resistance is connected to earth potential; The second input of the second alternative selector be connected with the output of the second out gate and as described in there is the first input end of the comparator of selection function; The control end of the second out gate be connected with the control end of the second alternative selector and as described in there is the Enable Pin of the comparator of selection function, second output of alternative selector and the positive input of voltage comparator are connected, and the output of voltage comparator is as the output of the described comparator with selection function.

Beneficial effect of the present invention: PWM modulation circuit of the present invention is on the basis of conventional P WM light modulation, the pwm signal of inputting to external world through the size of the upper electric current of LED according to actual flow carries out certain modulation, regulate its duty ratio, the variation that makes the duty ratio of the pwm signal of internal circuit actual participation light modulation follow the upper actual current of LED correspondingly obtains dynamic modulation, control again subsequently the switch that LED drives signal, make the brightness of LED in each digit pulse cycle equal preset value, improve PWM light modulation precision.In addition the LED lamp cross luma degree between all right balance multichannel of PWM modulation circuit of the present invention, making can be because of the difference of LED between multi-way LED lamp string, cause brightness to produce deviation, and the brightness of every paths of LEDs all equals preset value, thereby improved PWM light modulation precision.

Accompanying drawing explanation

Fig. 1 is system loop process of establishing schematic diagram.

Fig. 2 is PWM modulation circuit structural representation of the present invention.

Fig. 3 is current comparator structural representation in the embodiment of the present invention.

Fig. 4 is the comparator configuration schematic diagram in the embodiment of the present invention with selection function.

Fig. 5 is rest-set flip-flop input signal schematic diagram in embodiment.

Fig. 6 is modulated process and result schematic diagram in embodiment.

Embodiment

Two problems that the conventional P WM light modulation of mentioning based on background technology exists, have following consideration:

1,, in multichannel application, can dynamically regulate the duty of pwm signal recently to realize in any one light modulation cycle the brightness on every paths of LEDs according to the actual value of every paths of LEDs electric current and equate and be preset value: I lED× DT, wherein, I lEDaverage current when pwm signal is effective high level in the light modulation cycle on LED, T is the cycle of digit pulse pwm signal, D is its duty ratio.In addition suppose that LED electric current turn-off speed is very fast here, ignore pwm signal and turn-off the impact that the moment brings brightness.

2, can carry out the accurately duty ratio of the pwm signal of dynamic adjustments internal circuit actual participation light modulation according to the real-time luminosity of LED, reduce to eliminate even completely the light loss in system loop process of establishing, improve the light modulation precision of PWM light modulation.

Therefore the present invention proposes a kind of PWM modulation circuit, can regulate dynamically according to real-time current in load the duty ratio of extraneous PWM input signal, has well solved two problems that conventional P WM light modulation exists.

Below in conjunction with accompanying drawing, PWM modulation circuit of the present invention is described further.

As shown in Figure 2, PWM modulation circuit of the present invention comprises: current comparator A1, the comparator A2 of selection function, rest-set flip-flop RS, the first alternative selector MUX1, the first transmission gate TGS1, two input NOR gate NOR2, inverter INV, the one NMOS pipe MN1 and accumulation of error capacitor C 1, wherein, the A end of described transmission gate TGS is for the input of extraneous reference voltage signal VREF1, Y end is connected with the drain electrode of current comparator A1 input VIREF and a NMOS pipe, the source electrode of the one NMOS pipe is received earth potential, extraneous input pwm signal PWMD is oppositely connected with the control end of transmission gate TGS1 and the grid of NMOS pipe MN1 afterwards through inverter INV, another input of current comparator A1 is for inputting the sampled signal V of LED iSNSA, the output BCOM of current comparator A1 is connected with the input VBCOM, the forward end of accumulation of error capacitor C 1 of the comparator C OMPARE with selection function, and the negative end of accumulation of error capacitor C 1 is received earth potential, there is second input of comparator A2 of selection function for inputting the second reference voltage source VREF2, the input EN22 of comparator A2 and the control end C of the alternative selector MUX2 end with selection function are connected for the input of extraneous enable signal, the output ACU_DIM with the comparator A2 of selection function is connected with two input NOR gate NOR2 inputs, another input of NOR gate NOR2 is connected with the second input B of the S of rest-set flip-flop RS end, alternative selector MUX1, and the pwm signal PWMD of extraneous input is as the input signal of these 3 ports, in addition the R end of two input NOR gate NOR2 outputs and rest-set flip-flop RS is connected, the output of rest-set flip-flop RS is connected with the first input end A of alternative selector MUX1, and the output of alternative selector is the pwm signal ACU_PWM after the output output of PWM modulation circuit is modulated.

Fig. 3 has provided a kind of structural representation of current comparator, specifically comprise: the first operational amplifier OPA_1, the second operational amplifier OPA_2, resistance R 1, R2, PMOS pipe MP1, MP2, MP3, MP4, NMOS pipe MN2, MN3, MN5, wherein operational amplifier OPA_1, MP1, MN1, R1 composition negative feedback branch road, the current potential clamp of N1 being ordered by amplifier OPA_1 is V iREF, make reference current I rEFfor: I rEF=V iREF/ R 1; The second operational amplifier OPA_2, MP4, MN2, the negative feedback branch road of R2 composition, the current potential clamp of N2 being ordered by amplifier OPA_2 is V iSNSA, make reference current I sNSAfor: I sNSA=V iSNSA/ R 2, then pass through current mirror MP1, and MP2, MN3 image current IREF, through current mirror MP4, MP3, MN4 image current I sNSAafterwards two electric currents are carried out to subtraction.

Concrete annexation is as follows: the forward end of the first operational amplifier OPA_1 is as the first input end of current comparator, one end of the negative input of the first operational amplifier OPA_1 and resistance R 1, the source electrode of NMOS pipe MN5 is connected, the other end earthing potential of resistance, the grid of NMOS pipe MN5 is connected with the output of the first operational amplifier OPA_1, in addition the grid of the drain electrode of NMOS pipe MN5 and PMOS pipe MP1, drain electrode, the grid of PMOS pipe MP2 is connected, the source electrode of PMOS pipe MP1 and PMOS pipe MP2 meets extraneous power vd D, the drain electrode of PMOS pipe MP2 is connected as the output BCOM end of this module with the drain electrode of NMOS pipe MN3, the grid of NMOS pipe MN3, the grid of NMOS pipe MN4, drain electrode is connected with the drain electrode of PMOS pipe MP3, the source ground current potential of NMOS pipe MN3 and NMOS pipe MN4, in addition the grid of the grid of PMOS pipe MP3 and PMOS pipe MP4, drain electrode, the drain electrode of NMOS pipe MN2 is connected, the source electrode of PMOS pipe MP3 and PMOS pipe MP4 meets external power supply voltage VDD, the grid of NMOS pipe MN2 is connected with the output of the second operational amplifier OPA_2, the NMOS pipe source electrode of MN2 and one end of resistance R 2, the negative input of the second operational amplifier OPA_2 is connected, the other end earthing potential of resistance R 2, the positive input of the second operational amplifier OPA_2 is for inputting the sampled signal V of outside LED iSNSA.

The left side forms negative feedback branch road by amplifier OPA_1, MP1, MN1, R1, and the current potential clamp of N1 being ordered by amplifier OPA_1 is V iREF, make reference current I rEFfor: I rEF=V iREF/ R 1, the negative feedback branch road that the right is made up of amplifier MP4, MN2, R2, the current potential clamp of N2 being ordered by amplifier OPA_2 is V iSNSA, make reference current I sNSAfor: I sNSA=V iSNSA/ R 2, then pass through current mirror MP1, MP2, MN3 image current IREF, through current mirror MP4, MP3, MN4 image current I sNSAafterwards two electric currents are carried out to subtraction, it is poor that realization is done default reference current and the real-time current of flowing through on LED, the difference electric current obtaining discharges and recharges capacitor C 1 again, thereby the pwm signal in a PWM light modulation cycle is in high level time, the quantity of electric charge of the upper storage of C1 reflects the error of the upper brightness of actual LED in this light modulation cycle.Therefore the charging current IBCOM in capacitor C 1 can be expressed as:

Pwm signal in a PWM light modulation cycle is in high level time, and the quantity of electric charge of the upper storage of C1 is that the error on actual LED can be expressed as: Q ERR = I BCOM × T × D = ( V IREF R 1 - V ISNSA R 2 ) × T × D .

Fig. 4 has provided the structural representation of a kind of comparator A2 with selection function, specifically comprise: voltage comparator A3, out gate TGS2, the second alternative selector MUX2, the 3rd resistance R 3 and the 4th resistance R 4, wherein, the negative end of one end of the 3rd resistance R 3 and comparator A3, the A end of transmission gate TGS2 is connected, the second input of device A2 as a comparison, one end of the other end of the 3rd resistance R 3 and the 4th resistance R 4, the A input of alternative selector MUX2 are connected, the other end earthing potential of the 4th resistance R 4; The B of transmission gate TGS1 holds the first input end of device A2 as a comparison that is connected with the B input of alternative selector MUX2 to be used for inputting VBCOM, and the control end C of transmission gate TGS2 and the control end C of MUX2 are connected, for inputting outside digital controlled signal EN22's; The output of MUX2 is connected with the positive input of comparator A3, and the output of comparator A3 is designated as ACU_DIM.

Be connected with OPA_1 by transmission gate because of it for VREF1, as long as therefore meet the common-mode input range of VREF1 at OPA_1.For VREF2, this fixing reference voltage should be after chip soft start finishes, and when system loop is started working, the initial voltage in capacitor C 1, is generally the half of supply voltage VDD, is assumed to be 2.5V here.

The agent structure with the comparator A2 of selection function is a comparator, and additional digital selection function makes, within a PWM light modulation cycle, to select different comparison others according to different enable signals.Concrete effect has two: the one, and in the time that enable signal EN22 is high level, alternative selector MUX2 selects voltage V in capacitor C 1 bCOMoutput, comparator A3 compares the voltage V in capacitor C 1 bCOMand fixed reference potential (this fixing reference voltage should be after chip soft start finishes, and when system loop is started working, the voltage in capacitor C 1, is assumed to be 2.5V here), thereby reach the object that discharges LED error; The 2nd, the upper voltage of periodic reset capacitance C1, eliminates the impact of useless error on duty ratio modulation.Specific works situation is as follows: first, it is 2.3V that two electric resistance partial pressures in left side make N1 point voltage.In the time that enable signal EN22 is low level, MUX2 selects the level comparison of 2.5V and 2.3V, the output of this module does not regulate the duty ratio of extraneous input pwm signal PWMD, in addition the reference level of 2.5V (can be provided by LDO) is connected with capacitor C 1 by transmission gate, make voltage in capacitor C 1 be reset to 2.5V, the correctness that guarantees deviation accumulation in subsequent cycle, this process is initial value reseting procedure.

Comparator A3 can adopt collapsible amplifier structure, after connect two inverters and carry out shaping, the first operational amplifier OPA_1 and the second operational amplifier OPA_2 can adopt push-pull type export structure to increase output Slew Rate, make electric current I sNSAfollowing sampling voltage V that can be real-time iSNSA.Here, A3, OPA_1 and OPA_2's is the ordinary skill in the art, and its structure is not described in detail.

As shown in Figure 6, the specific works principle of whole PWM modulation circuit is as follows for specific works process:

In the time that extraneous pwm signal PWMD rising edge arrives, V rEFsignal is transferred to current comparator A1 by transmission gate TGS, and current comparator A1 is to electric current I rEFand I sNSAsignal does poor, and output discharges and recharges capacitor C 1, accumulates the upper luminance errors of actual LED, and this process is referred to as accumulation of error process.It is high level that EN22 meanwhile should be set, and the comparator A3 in A2 selects 2.5V and V bCOMrelatively, due to V bCOMnormal voltage value is 2.5V, and the output ACU_DIM of comparator A3 has just reflected the Real-time Error on LED so.When PWMD signal is while being low by hypermutation, V iREFbe pulled to low level, now current comparator A1 passes through electric current I sNSAcapacitor C 1 is discharged, if now the voltage in capacitor C 1 is greater than 2.5V, comparator A3 is output as height, after rear end digital logic gate and rest-set flip-flop effect, the pwm signal ACU_PWM of actual participation light modulation is still high, therefore the pwm signal PWMD of extraneous input is broadened to the duty ratio of the pwm signal ACU_PWM of internal circuit actual participation light modulation, and this process is referred to as error dispose procedure, and this process is maintained to V bCOMbe discharged to and be less than 2.5V, comparator output switching activity, rest-set flip-flop upset is electronegative potential, and modulation finishes, and the pwm signal ACU_PWM upset of internal circuit reality is low level.After modulation finishes, EN22 is set to low level, completes the initial value homing action of voltage in capacitor C 1, guarantees the correctness of subsequent cycle modulation.

Known according to principle of charge conservation, there is following relation in the duty ratio D after regulating before duty ratio D' and the adjusting of digit pulse:

I SNSA × T × D ′ = I SNSA × T × D + Q ERR ⇒ D ′ = D + I REF - I SNSA I SNSA D = I REF I SNSA × D

Wherein, Q eRRthe error quantity of electric charge, T is the cycle of extraneous input pwm signal.

Can find out, in the time that the electric current on LED changes, sample rate current I sNSAfollow variation, thereby change the duty ratio of the pwm signal of inner actual participation light modulation, as shown in Figure 6, suppose that LED electric current turn-off speed is very fast, ignore pwm signal and turn-off the impact that the moment brings brightness, thereby guarantee that the electric current of flowing through on LED obtains accurate PWM modulation.

Can find out:

(1) loop set up stable before by LED on electric current be less than reference current I rEFthe duty ratio that the reduction of the PWM light modulation precision causing can be inputted pwm signal to external world by this kind of modulation compensates and reduces even to eliminate the PWM light modulation loss of significance causing in start-up course.

(2), in the time that multichannel is applied, because every paths of LEDs characteristic difference can cause the brightness difference to some extent of LED under same pwm signal, the current average of establishing the first via is I sNSA1, the electric current average out to I on the second tunnel sNSA2, I sNSA1be not equal to I sNSA2.But after the modulation circuit proposing through the present invention, can being expressed as of the current average of two paths of LED:

I SNSA 1 × T × D ′ = I SNSA 1 × T × ( D + I REF - I SNSA 1 I SNSA 1 D ) = I REF × T × D

I SNSA 2 × T × D ′ = I SNSA 2 × T × ( D + I REF - I SNSA 2 I SNSA 2 D ) = I REF × T × D

Can be found by above-mentioned two formulas: the current average on every road equates, and the brightness that all equals systemic presupposition is as shown in Figure 6, I rEFand I sNSAthe area surrounding with time shaft equates.

The design of digital controlled signal EN22:

Analysis by A2 can find out, outside digital controlled signal EN22 is designed with 2 requirements:

(1) A2 is operated in error zero clearing process, the trailing edge of requirement EN22 is discharged to voltage on it in capacitor C 1 and is less than (equaling) 2.5V, being that the whole release of error is complete carries out zero clearing to error afterwards again, if the voltage on electric capacity is greater than 2.5V just to its zero clearing, will make the duty ratio compensation of pwm signal not.

(2) A2 is operated in deviation accumulation process, require the rising edge of EN22 and the rising edge of PWMD signal synchronous, once opening, namely PWM light modulation will carry out deviation accumulation, if otherwise the hysteresis of the rising edge of EN22, error can not completely totally be made the duty ratio compensation of pwm signal inadequate; If the rising edge of EN22 in advance, although now due to V iSNSAbe 0 voltage, V iREFvoltage is also pulled to 0 voltage, even if now start cumulative errors, do not have impact yet, but for fear of impacts such as noises, still require enable signal and the deviation accumulation of deviation accumulation to start, the rising edge of external PWM signal and the rising edge of EN22 are synchronous simultaneously.

According to the above description, outside digital controlled signal EN22 can have 2 kinds of methods to realize:

Realize with rest-set flip-flop: putting number end using the pwm signal PWMD of external world's input as rest-set flip-flop, the pulse signal CLK of a fixed cycle is as the clear terminal of rest-set flip-flop, as long as guarantee its phase relation (as shown in Figure 5), output just can be used as control signal EN22 like this; In addition, can be found out by above-mentioned analysis, ACU_PWM also meets above-mentioned requirements, therefore also can directly use ACU_PWM as digital controlled signal EN22.

In summary it can be seen that modulation circuit of the present invention is on the basis of conventional P WM light modulation, the pwm signal inputted to external world through the size of the upper electric current of LED according to actual flow (representing with PWMD) carries out certain modulation, mainly to regulate its duty ratio, the variation that makes the duty ratio of the pwm signal (representing with ACU_PWM) of internal circuit actual participation light modulation follow the upper actual current of LED correspondingly obtains dynamic modulation, control again subsequently the switch that LED drives signal, make the brightness of LED in each digit pulse cycle equal preset value, improved PWM light modulation precision.In addition the LED lamp cross luma degree between all right balance multichannel of modulation circuit of the present invention, making can be because of the difference of LED between multi-way LED lamp string, causes brightness to produce deviation, and the brightness of every paths of LEDs all equals preset value, the precision of raising PWM light modulation.

Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should be understood to that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not depart from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (2)

1. a PWM modulation circuit, specifically comprises: the first transmission gate, the first current comparator, the first alternative selector, rest-set flip-flop, two are inputted NOR gate, inverter, a NMOS pipe, accumulation of error electric capacity and had the comparator of selection function, wherein,
Outside pwm signal is as the input signal of described inverter, input termination first reference voltage source of described the first transmission gate, the output of control termination inverter of the first transmission gate and the grid of a NMOS pipe, the source electrode of the one NMOS pipe is received earth potential, the drain electrode of the one NMOS pipe, the output of the first transmission gate are connected with the first input end of the first current comparator, the sampled signal of the second input termination external loading of the first current comparator; The output of the first current comparator is connected to earth potential by accumulation of error electric capacity lotus root, and the output of the first current comparator is connected with the first input end of the comparator with selection function, second input termination second reference voltage source with the comparator of selection function, the selecting side with the comparator of selection function is connected with the control end of alternative selector for inputting outside digital controlled signal; The output with the comparator of selection function is connected with the first input end of two input NOR gate, the pwm signal of the second input termination outside of two input NOR gate, S end and the first alternative selector first input end of rest-set flip-flop; The R end of rest-set flip-flop is connected with the output of two input NOR gate, and the output of rest-set flip-flop is connected with the second input of the first alternative selector, and the output of the first alternative selector is as the output of described PWM modulation circuit;
Described the first current comparator comprises the first operational amplifier, the second operational amplifier, the first resistance, the second resistance, a PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe and the 5th NMOS pipe, wherein, the positive input of the first operational amplifier is as the first input end of described the first current comparator, and the source electrode of the source electrode of the source electrode of a PMOS pipe, the 2nd PMOS pipe, the source electrode of the 3rd PMOS pipe and the 4th PMOS pipe is all connected with outside supply voltage; The grid of the one PMOS pipe is connected with grid, the drain electrode of a PMOS pipe and the drain electrode of the 5th NMOS pipe of the 2nd PMOS pipe; The drain electrode of the 2nd PMOS pipe is connected as the output of described the first current comparator with the drain electrode of the 3rd NMOS pipe; The grid of the 3rd PMOS pipe, the grid of the 4th PMOS pipe, the drain electrode of the 4th PMOS pipe and the drain electrode of the 2nd NMOS pipe are connected, the grid of the 2nd NMOS pipe is connected with the output of the second operational amplifier, the source electrode of the 2nd NMOS pipe is connected with the negative input of the second operational amplifier and is connected to earth potential by the second resistance lotus root, and the positive input of the second operational amplifier is as the second input of described the first current comparator; The drain electrode of the 3rd PMOS pipe, the grid of the 4th NMOS pipe, the drain electrode of the 4th NMOS pipe and the grid of the 3rd NMOS pipe link together; The source electrode lotus root of the source electrode of the 3rd NMOS pipe and the 4th NMOS pipe is connected to earth potential; The grid of the 5th NMOS pipe is connected with the output of the first operational amplifier, and the source electrode of the 5th NMOS pipe is connected with the negative input of the first operational amplifier and is connected to earth potential by the first resistance lotus root.
2. PWM modulation circuit according to claim 1, it is characterized in that, the described comparator with selection function comprises: voltage comparator, the second out gate, the second alternative selector, the 3rd resistance and the 4th resistance, wherein, the negative input of voltage comparator be connected with the input of the second out gate and the first terminal of the 3rd resistance and as described in there is the second input of the comparator of selection function; The first input end of the second alternative selector is connected with the second terminal of the 3rd resistance and the first terminal of the 4th resistance, and the second terminal lotus root of the 4th resistance is connected to earth potential; The second input of the second alternative selector be connected with the output of the second out gate and as described in there is the first input end of the comparator of selection function; The control end of the second out gate be connected with the control end of the second alternative selector and as described in there is the Enable Pin of the comparator of selection function, second output of alternative selector and the positive input of voltage comparator are connected, and the output of voltage comparator is as the output of the described comparator with selection function.
CN201210277070.2A 2012-08-06 2012-08-06 Pulse width modulation (PMW) modulator circuit CN102843828B (en)

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