CN113437874B - BUCK switch converter with inductance minimum current control circuit - Google Patents

BUCK switch converter with inductance minimum current control circuit Download PDF

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Publication number
CN113437874B
CN113437874B CN202110984734.8A CN202110984734A CN113437874B CN 113437874 B CN113437874 B CN 113437874B CN 202110984734 A CN202110984734 A CN 202110984734A CN 113437874 B CN113437874 B CN 113437874B
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output
imin
power tube
circuit
main power
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CN113437874A (en
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丁德彬
陈立新
熊海峰
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Nanjing Taisi Microelectronics Co ltd
Shanghai Taisi Microelectronics Co ltd
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Nanjing Taisi Microelectronics Co ltd
Shanghai Taisi Microelectronics Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output

Abstract

The invention discloses a BUCK switch converter with an IMIN control circuit, which comprises: the step-down peripheral circuit and the control circuit, one end of the inductance L is loaded on the connecting line between the main power tube PM and the auxiliary power tube NM, and the other end is coupled with the output end for switching the step-down output of the converter, the control circuit comprises: error amplifier EA, PWM comparator, ramp generation circuit, logic control circuit, clock, drive level circuit and sampling circuit, logic control circuit includes: flip-flop, AND gate AND1, OR gate OR1, inverter INV1, AND gate AND 2. According to the invention, the switching mode and the direct-through mode of the BUCK switch converter can be freely switched through the state of the output QA of the PWM comparator; when the input voltage and the output voltage are close to each other, the switching period is controlled, and low switching ripples can be obtained under heavy load and light load.

Description

BUCK switch converter with inductance minimum current control circuit
Technical Field
The invention relates to the technical field of switching power supplies, in particular to a BUCK switching converter with an IMIN (inductance minimum current) control circuit.
Background
With the widespread use of electronic devices, the input voltage of the buck converter may be lower than the target output voltage, which results in the buck converter not only operating in a buck switching mode with a smaller output than input, but also supporting a 100% duty cycle pass-through mode. For example, in devices for lithium battery applications, the voltage of the lithium battery continues to decrease with prolonged use, and when the target output is higher than the input voltage, the entire switching converter is required to support the pass-through mode. In the switching process of the switching mode and the through mode, in the process of switching the duty ratio from the maximum duty ratio state where the whole switching converter can work to the 100% duty ratio, most of the buck switching converters on the market at present do not perform any control method treatment, such as the TPS62811, so that the output ripple wave becomes large in the switching process, and the whole switching converter with the psm (power Save mode) has the efficiency far lower than the condition of the same load when the whole switching converter works at the duty ratio smaller than the maximum duty ratio due to the fact that the inductance current is negative when the whole switching converter is in light load.
The existing buck converter cannot realize free switching of low ripple between a switching mode and a through mode, and output voltage ripple is high, and on the other hand, conversion efficiency is low in a critical state of the switching mode and the through mode;
the prior art can not meet the requirements of people at the present stage, and the prior art is urgently needed to be reformed based on the current situation.
Disclosure of Invention
It is an object of the present invention to provide a BUCK switching converter with an IMIN control circuit to solve the problems set forth in the background above.
In one aspect, the present invention provides a BUCK switching converter, including: a voltage reduction peripheral circuit and a control circuit;
the voltage reduction peripheral circuit comprises a main power tube PM, an auxiliary power tube NM, an inductor L and an output capacitor COUTThe voltage division feedback circuit;
preferably, one end of the inductor L is loaded on a connection line between the main power tube PM and the auxiliary power tube NM, and the other end of the inductor L is coupled to the output end for switching the step-down output of the converter;
the control circuit includes: the circuit comprises an error amplifier EA, a PWM comparator, a ramp generating circuit, a logic control circuit, a clock, a driving stage circuit and a sampling circuit;
preferably, a non-inverting input terminal of the error amplifier EA is loaded with a reference source VREFAnd the inverting input terminal of the error amplifier EA is loaded with the feedback value V of the output voltageFBThe error amplifier EA is used for converting the feedback value V of the output voltageFBAnd a reference source VREFAmplified to generate a voltage VCOMP；
Preferably, the output terminal of the error amplifier EA is coupled to the inverting input terminal of the PWM comparator, and V is set to beCOMPInput to the PWM comparator.
Preferably, a positive phase input end of the PWM comparator is coupled to a ramp generating circuit and a sampling circuit, the ramp generating circuit generates a ramp compensation signal, and the sampling circuit samples a voltage signal of the main power transistor PM and superimposes the ramp compensation signal generated by the ramp generating circuit to generate a voltage VSLOPELoaded at the positive phase input end of a PWM comparator, and the PWM comparator passes through the opposite positive phase input end VSLOPEAnd an inverting input terminal VCOMPGenerating a state QA after comparison and outputting the state QA to a logic control circuit;
the logic control circuit includes: a flip-flop, an AND gate AND1, an OR gate OR1, an inverter INV1, AND an AND gate AND 2;
preferably, the S terminal of the flip-flop is loaded with a clock control signal CLK, the R terminal of the flip-flop is coupled to an AND gate AND1, one input terminal of the AND gate AND1 is loaded with a QA control terminal, the other input terminal of the AND gate AND1 is coupled to an OR gate OR1, one input terminal of the OR gate OR1 is loaded with a control signal Ton _ long, AND the other input terminal of the OR gate OR1 is loaded with a control signal IMIN;
preferably, the output end of the flip-flop is loaded to the input end of the AND gate AND2 through a coupling inverter INV1, the other input end of the AND gate AND2 is loaded with the control signal IMIN _ L, the flip-flop is divided into two output ends, one output end outputs an NCH control signal through the AND gate AND2, AND the other output end outputs a PCH control signal.
In another aspect, the present invention provides another alternative solution as follows, in which the IMIN control circuit includes: power tubes PW11, PW12 and PW13, power tubes PW11, PW12 and PW13 are combined to form a mirror image differential pair transistor for differentially comparing the input voltage with the voltage of a comparison point;
preferably, the IMIN control circuit further includes: one end of each of the sampling resistor Rsense1 and the sampling resistor Rsense2 is coupled to an input terminal VIN of the buck converter, and the other end of each of the sampling resistor Rsense1 and the sampling resistor Rsense2 is coupled to the source electrodes of the power tubes PW11 and PW12, respectively;
preferably, the IMIN control circuit further includes: and a resistor R1 is loaded at the non-inverting input end of the output comparator COMP, a resistor R2 is loaded at the inverting input end of the output comparator COMP, and the input voltage VIN is compared with the difference value of SW and then amplified to a resistor R1 and a resistor R2.
Has the advantages that:
(1) the switching mode and the through mode of the BUCK switching converter can be freely switched through the state of the output QA of the PWM comparator;
(2) when the input voltage and the output voltage are close to each other, the switching period is controlled, and low switching ripples can be obtained under heavy load and light load;
(3) after the IMIN _ L is added, when the input and the output are close, the inductive current is prevented from flowing away, and the highest conversion efficiency can still be kept when the load is light;
(4) increasing Ton _ long can close the main power tube PM after reaching the maximum conduction time of the main power tube even if the inductive current does not reach the inductive minimum current, so that the ripple of the output voltage during frequency hopping is reduced, the switching frequency during heavy load is reduced, and the switching ripple of the output voltage is also reduced.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a circuit diagram of a conventional logic control circuit;
FIG. 3 is a circuit diagram of the logic control circuit of the present invention;
fig. 4 is a circuit diagram of the IMIN control circuit of the main power transistor PM of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the invention without making any creative effort, shall fall within the protection scope of the invention.
Referring to fig. 1, the present invention provides a BUCK switching converter, including a BUCK peripheral circuit and a control circuit;
the step-down peripheral circuit comprises a main circuitPower tube PM, auxiliary power tube NM, inductor L and output capacitor COUTOne end of the inductor L is loaded on a connecting line between the main power tube PM and the auxiliary power tube NM, the other end of the inductor L is coupled with the output end and used for the step-down output of the switching converter, the voltage division feedback circuit comprises a voltage division circuit consisting of a voltage division resistor R1 and a voltage division resistor R2, and the voltage division feedback circuit further comprises an output feedback voltage VFBAnd the output feedback voltage VFBThe feedback point of (2) is loaded between a voltage dividing resistor R1 and a voltage dividing resistor R2, and is loaded at the inverting input end of the error amplifier EA through a feedback line, and the feedback point is fed back to the error amplifier EA for amplification, and the voltage of the feedback point is equal to the reference voltage, so that the output voltage value is determined.
The control circuit includes: the circuit comprises an error amplifier EA, a PWM comparator, a ramp generating circuit, a logic control circuit, a clock, a driving stage circuit and a sampling circuit;
a reference source V is loaded at the positive phase input end of the error amplifier EAREFAnd the inverting input terminal of the error amplifier EA is loaded with the feedback value V of the output voltageFBThe error amplifier EA is used for converting the feedback value V of the output voltageFBAnd a reference source VREFAmplified to generate a voltage VCOMP；
The output end of the error amplifier EA is coupled with the inverting input end of the PWM comparator, and V is converted into the voltageCOMPInput to the PWM comparator.
The positive phase input end of the PWM comparator is coupled with a slope generation circuit and a sampling circuit, the slope generation circuit generates a slope compensation signal, and the sampling circuit samples a voltage signal of the main power tube PM and superposes the slope compensation signal generated by the slope generation circuit to generate a voltage VSLOPELoaded at the positive phase input end of a PWM comparator, and the PWM comparator passes through the opposite positive phase input end VSLOPEAnd an inverting input terminal VCOMPAfter the comparison, a state QA is generated and output to the logic control circuit, and QA may be 0 (low level) or1 (high level).
Referring to fig. 3, the output terminal of the logic control circuit is coupled to a driver stage circuit, wherein one path of the driver stage circuit is coupled to the master power transistor PM, and the other path is coupled to the auxiliary power transistor NM, the logic control circuit has a flip-flop, the S terminal of the flip-flop is loaded with the clock control signal CLK, AND the R terminal of the flip-flop is coupled to an AND gate AND1, one input end of the AND gate AND1 loads the QA control end, the other input end is coupled to an OR gate OR1, one input end of the OR gate OR1 is loaded with the control signal Ton _ long, the other input end is loaded with the control signal IMIN, the output end of the flip-flop is loaded at the input end of the AND gate AND2 by coupling an inverter INV1, AND the other input terminal of the AND gate AND2 is loaded with a control signal IMIN _ L, the flip-flop is divided into two output terminals, one output end outputs an NCH control signal through an AND gate 2, AND the other output end outputs a PCH control signal.
The invention also has an input/output comparator respectively coupled with the input end and the output end of the buck switch converter and used for comparing the voltage of the input end with the voltage of the output end;
(1) when the output voltage is lower than the input voltage and is smaller than the maximum duty ratio of the fixed switching period, the whole switching converter works in a switching control mode, the output voltage is stable, the switching ripple is very small, and the invention does not need to intervene;
(2) when the output voltage is close to the input voltage, the duty ratio of the main power tube PM in a fixed switching period is infinitely close to 1, and when the opening time of the main power tube PM is long and the opening time of the auxiliary power tube NM is short, the control signal Ton _ long and the control signal IMIN _ L are added to intervene.
Before a control signal Ton _ long is not added, in light load, after a main power tube PM is started, inductive current is controlled by IMIN, only after the inductive current reaches the minimum, the main power tube PM can be switched off, and then an auxiliary power tube NM is started, so that output ripples are large; after the control signal Ton _ long is added, when the main power tube PM is started, the control signal Ton _ long is not only controlled by the IMIN, but also controlled by the Ton _ long, and as the Ton _ long is a signal with fixed time, the time is set in 2-3 fixed periods; if the inductive current does not reach the inductive minimum current within the maximum conduction time of the main power tube, the PM of the main power tube is allowed to be closed, the response speed during frequency hopping can be improved, the switching ripple is reduced, and the control of Ton _ long is increased, in order to avoid the situation that the inductive current is smaller within the maximum conduction time of the main power tube, the zero-crossing detection comparator cannot respond in time after the NM of the auxiliary power tube is opened, and the switching conversion efficiency is reduced, the invention also increases the control signal IMIN _ L to prevent the inductive current from going negative and increase the switching conversion efficiency, IMIN _ L is a comparison point of the inductive current, the comparison point is defined as that the NM of the auxiliary power tube is opened after the inductive current reaches the minimum, the zero-crossing detection comparator can respond in time and close the NM of the auxiliary power tube, therefore, when the inductive current does not reach the minimum within the maximum conduction time of the main power tube, the NM of the auxiliary power tube is not opened, the inductor freewheels from a substrate diode attached inside the power tube NM; when the inductive current exceeds the minimum current within the maximum conduction time of the main power tube, the PM of the main power tube and the auxiliary power tube is started, so that the output ripple is very small;
further, under the heavy load condition, when the inductive current exceeds the minimum current, after the main power tube PM is turned on to _ long, the auxiliary power tube NM is turned on, the switching period can be stabilized at the maximum conduction time of the main power tube, and the controllable lower ripple is realized by outputting the switching ripple.
(3) When the target output voltage exceeds the input voltage, the control loop is controlled by the output state QA of the PWM comparator, the main power tube PM is in a normally open state, the output ripple wave is equal to the input voltage ripple wave, and the lost power consumption is only the static power consumption of the whole switching converter; when the input voltage is increased again, the QA state of the PWM comparator is changed, the whole switching converter enters the switching mode again, the switching mode and the through mode are freely switched only through the change of the output state QA of the PWM comparator, when the output QA =0 of the PWM comparator, the whole switching converter still continues to work in the switching state, and the main power tube PM is started when the next clk is waited; when QA =1, the set value is lower than the input value, and the linear current-limiting through working mode of the NMOS tube is entered, so that seamless free switching between the through working mode and the switch working mode is realized.
In another aspect, the present invention provides another alternative embodiment, an IMIN control circuit, configured to output and control a control signal IMIN or a control signal IMIN _ L, where IMIN is an output control terminal of a current sampling comparator of a main power transistor PM, IMIN _ L is an output of a power transistor PM current comparator smaller than IMIN;
the method comprises the following steps: power tubes PW11, PW12 and PW13, power tubes PW11, PW12 and PW13 are combined to form a mirror image differential pair transistor for differentially comparing the input voltage with the voltage of a comparison point;
the IMIN control circuit further comprises a sampling resistor Rsense1 and a sampling resistor Rsense2, one end of the sampling resistor Rsense1 and one end of the sampling resistor Rsense2 are coupled with an input end VIN of the buck converter, the other end of the sampling resistor Rsense2 are coupled with the sources of the power tubes PW11 and PW12 respectively, the sampling resistors Rsense1 and Rsense2 are resistors formed by sampling devices matched with the main power tube PM, a comparison point SW is arranged between the main power tube PM and the auxiliary power tube NM and an inductor L, the comparison point SW is coupled with the PW13 of the control signal IMIN realization circuit, and the larger Rsense1 is, the higher the comparison point SW of the inversion of the comparison circuit is; the control signal IMIN implementation circuit further comprises an output comparator COMP, a non-inverting input end of the output comparator COMP is loaded with a resistor R1, an inverting input end of the output comparator COMP is loaded with a resistor R2, a difference value between VIN and SW is compared and amplified to the resistor R1 and the resistor R2, and then the comparison is performed by the output comparator COMP to output IMIN or IMIN _ L.
The alternative embodiment aims at the improvement of output switch ripple and conversion efficiency when the input voltage and the output voltage are close;
referring to fig. 2, CLK of the logic control circuit of the conventional technical means is connected to the S terminal of the RS flip-flop, and when CLK =1, PCH =1, the main power transistor PM is turned on; the IMIN is output of a current sampling comparator of the main power tube PM, when the main power tube PM is turned on in a light load, when the current of the inductor L exceeds the minimum current, the logic output IMIN =1, the IMIN and the output QA of the PWM comparator are connected to the R terminal of the RS flip-flop after passing through an and gate, and when the main power tube PM is turned off after QA =1, the conversion efficiency is too low when the light load is caused.
Referring to fig. 3 AND 4, after Ton _ long AND IMIN in the logic control circuit disclosed in this alternative embodiment pass through OR gate OR1, AND pass through AND gate AND1 to R terminal of RS flip-flop with QA, Ton _ long =1 OR IMIN =1, when QA =1, the control signal PCH of the main power transistor PM is turned off, AND the control signal NCH of the slave power transistor NM is controlled by IMIN _ L, when IMIN _ L =0, i.e. the inductor current does not reach the set value IMIN _ L, the state of IMIN _ L is necessarily 1 when the main power transistor PM is turned off, the slave power transistor NM control signal NCH =0, the slave power transistor NM remains off, the inductor freewheel passes through the parasitic diode, it is known from reference to fig. 3 AND 4 that when the inductor current can reach the minimum current, the state of IMIN _ L is necessarily 1, the voltage difference generated by sampling the current of PM is compared, AND when the current exceeds the comparison point, the output state is 1, wherein IB is the bias current of the comparison circuit, rsense1 and Rsense2 are resistors formed by sampling devices matched with the main power tube PM, the larger Rsense1 and Rsense2 are, the higher the comparison point of the inversion of the comparison circuit is, the difference value between VIN and SW is amplified to the resistor of R1 after being compared, and IMIN or IMIN _ L is output through the comparison of an output comparator COMP;
in addition, Ton _ long disclosed in this alternative embodiment is a signal for controlling the time by a timer controlled by PCH, timing starts when PCH =1, and Ton _ long =1 when PCH is still 1 at the end of timing, and at this time, the main power transistor PM can be turned off as long as QA =1, so that the switching period when the input voltage and the output voltage are infinitely close to each other during heavy load is equal to the maximum time for turning on the main power transistor. After Ton _ long is added, even if the inductor current does not reach the minimum current, the main power tube PM can be still closed after the maximum conduction time of the main power tube is reached, the ripple of the output voltage during frequency hopping is reduced, the switching frequency during heavy load is reduced, and the switching ripple of the output voltage is also reduced.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or modifications of the invention can be made, and equivalents and modifications of some features of the invention can be made without departing from the spirit and scope of the invention.

Claims (6)

1. A BUCK switching converter, comprising: a voltage reduction peripheral circuit and a control circuit;
the voltage reduction peripheral circuit comprises a main power tube PM, an auxiliary power tube NM, an inductor L and an output capacitor COUTThe voltage division feedback circuit;
one end of the inductor L is loaded on a connecting line between the main power tube PM and the auxiliary power tube NM, and the other end of the inductor L is coupled with the output end and is used for the step-down output of the switching converter;
the control circuit includes: the circuit comprises an error amplifier EA, a PWM comparator, a ramp generating circuit, a logic control circuit, a clock, a driving stage circuit and a sampling circuit;
a reference source V is loaded at the positive phase input end of the error amplifier EAREFAnd the inverting input terminal of the error amplifier EA is loaded with the feedback value V of the output voltageFBThe error amplifier EA is used for converting the feedback value V of the output voltageFBAnd a reference source VREFAmplified to generate a voltage VCOMP；
The output end of the error amplifier EA is coupled with the inverting input end of the PWM comparator, and V is converted into the voltageCOMPInputting the signal to a PWM comparator;
the positive phase input end of the PWM comparator is coupled with a slope generation circuit and a sampling circuit, the slope generation circuit generates a slope compensation signal, and the sampling circuit samples a voltage signal of the main power tube PM and superposes the slope compensation signal generated by the slope generation circuit to generate a voltage VSLOPELoaded at the positive phase input end of a PWM comparator, and the PWM comparator passes through the opposite positive phase input end VSLOPEAnd an inverting input terminal VCOMPGenerating a state QA after comparison and outputting the state QA to a logic control circuit;
the logic control circuit includes: a flip-flop, an AND gate AND1, an OR gate OR1, an inverter INV1, AND an AND gate AND 2;
the S end of the trigger loads a clock control signal CLK, the R end of the trigger is coupled with an AND gate AND1, one input end of the AND gate AND1 loads a QA control end, AND the other input end of the AND gate AND1 is coupled with an OR gate OR 1;
one input end of the OR gate OR1 is loaded with a control signal Ton _ long, the other input end is loaded with a control signal IMIN, the output end of the flip-flop is loaded with the input end of the AND gate AND2 through the coupling inverter INV1, AND the other input end of the AND gate AND2 is loaded with a control signal IMIN _ L, wherein the control signal IMIN AND the control signal IMIN _ L are both inductor minimum current control signals, AND the inductor minimum current of the control signal IMIN _ L is smaller than the control signal IMIN;
the trigger is divided into two paths of output ends, wherein one path of output end outputs an NCH control signal through an AND gate 2, AND the other path of output end outputs a PCH control signal.
2. The BUCK switching converter according to claim 1, wherein: the change of the output state QA of the PWM comparator can switch the whole switching converter to work in a switching mode or a through mode;
when the output QA =0 of the PWM comparator, the whole switching converter works in a switching mode, and the main power tube PM is started when the next clk is waited;
when QA =1, the whole switching converter enters a straight-through operation mode of linear current limiting of the NMOS tube.
3. The BUCK switching converter according to claim 1, wherein: after the main power tube PM is started, the main power tube PM is controlled not only by the IMIN but also by the Ton _ long.
4. The BUCK switching converter according to claim 1, wherein: when the main power tube is conducted for the maximum time, the inductive current does not reach the inductive minimum current, the main power tube PM is allowed to be closed, the response speed during frequency hopping can be improved, and the switching ripple is reduced.
5. The BUCK switching converter according to claim 1, wherein: when the inductive current does not reach the inductive minimum current within the maximum conduction time of the main power tube, the auxiliary power tube NM is not started, and the inductor L continues current from the substrate diode in the auxiliary power tube NM;
when the inductive current exceeds the IMIN _ L current within the maximum conduction time of the main power tube, the PM of the main power tube and the auxiliary power tube is started, so that the output ripple is small.
6. An inductor minimum current control circuit, for implementing logic control of IMIN or IMIN _ L in a BUCK switching converter, comprising: power tubes PW11, PW12 and PW13, wherein the power tubes PW11, PW12 and PW13 are combined to form a mirror image differential pair tube for differentially comparing an input voltage with a voltage of a comparison point; wherein IMIN and IMIN _ L are inductance minimum current, and the inductance minimum current of IMIN _ L is smaller than IMIN;
the inductance minimum current control circuit further includes: the voltage-reducing circuit comprises a sampling resistor Rsense1 and a sampling resistor Rsense2, wherein one end of the sampling resistor Rsense1 and one end of the sampling resistor Rsense2 are coupled to an input end VIN of a buck converter, and the other ends of the sampling resistor Rsense1 and the sampling resistor Rsense2 are respectively coupled to sources of power tubes PW11 and PW 12; and the number of the first and second electrodes,
the sampling resistors Rsense1 and Rsense2 are resistors formed by sampling devices matched with the main power tube PM, a comparison point SW is arranged between the main power tube PM and the auxiliary power tube NM and between the main power tube PM and the inductor L, the comparison point SW is coupled with PW13 of the control signal IMIN realization circuit, and the larger the Rsense1 is, the higher the comparison point SW of the turnover of the comparison circuit is;
the inductance minimum current control circuit further includes: the output comparator COMP is provided, and a non-inverting input end of the output comparator COMP is loaded with a resistor R1, and an inverting input end of the output comparator COMP is loaded with a resistor R2; wherein the content of the first and second substances,
the difference value of the input voltage VIN and SW is compared and amplified to a resistor R1 and a resistor R2, and then IMIN or IMIN _ L is output after comparison by an output comparator COMP, wherein IMIN is output by a current sampling comparator of the main power tube PM, and when the main power tube PM is in light load, and when the current of an inductor L exceeds the current of IMIN, the logic output IMIN = 1.
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Publication number Priority date Publication date Assignee Title
CN113890393A (en) * 2021-09-27 2022-01-04 成都芯源系统有限公司 Switching power supply circuit and control circuit and method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101227147A (en) * 2008-02-19 2008-07-23 北京中星微电子有限公司 Direct current switch power supply control circuit
CN101471603A (en) * 2007-12-27 2009-07-01 英业达股份有限公司 DC-DC decompression converter and ripple improving circuit
EP2933911A1 (en) * 2014-04-16 2015-10-21 Dialog Semiconductor GmbH Switching mode power supply with negative current clocking

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8823352B2 (en) * 2011-07-11 2014-09-02 Linear Technology Corporation Switching power supply having separate AC and DC current sensing paths

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101471603A (en) * 2007-12-27 2009-07-01 英业达股份有限公司 DC-DC decompression converter and ripple improving circuit
CN101227147A (en) * 2008-02-19 2008-07-23 北京中星微电子有限公司 Direct current switch power supply control circuit
EP2933911A1 (en) * 2014-04-16 2015-10-21 Dialog Semiconductor GmbH Switching mode power supply with negative current clocking

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