JP2008043086A - Power supply device and control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain high conversion efficiency at light load and further suppress output voltage fluctuation, such as output ripples, at light load and at a time of switching. <P>SOLUTION: A power supply device 40 is provided with a DC-DC converter 1 and LDO (Low Drop Out regulator) 2. The DC-DC converter 1 is provided with: an error amplifier 11, a phase compensation circuit 12, a triangular wave generation circuit 13, a pulse width modulation circuit 14, a pre-driver 15, a monitor amplifier 16, a sample-hold circuit 17, a reference voltage generation circuit 19, a p-channel MOS transistor PT1, a p-channel MOS transistor PT2, an n-channel MOS transistor NT1, resistors R1 to R3, an inductor L1, and a capacitor C1. The LDO 2 is provided with an offset generation circuit 21, a reference voltage generation circuit 22, a differential amplifier circuit 23, a p-channel MOS transistor PT11, a resistor R11, and a resistor R12. When the output current is small, the offset generation circuit 21 sets the output voltage to a higher value than when the output current is large. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power supply device.

  In a system using a battery as a power source such as a PDA (Personal Digital Assistant) or a mobile terminal such as a portable terminal, the efficiency of the power supply device is more important than other systems. In devices that use batteries, such as mobile terminals, heavy loads such as transmission / reception operations even at light loads where the current consumption is extremely low, such as sleep mode and standby mode, such as sleep mode and standby mode, in order to keep the battery longer. The power supply device is required to have a high voltage conversion efficiency equivalent to the time (see, for example, Patent Document 1).

  In a power supply device described in Patent Document 1 or the like, a DC-DC converter using a PWM (Pulse Width Modulation) system operates at a heavy load, and intermittent operation is performed from a PWM DC-DC converter at a light load. Conversion efficiency is improved by switching to a DC-DC converter using a PFM (Pulse Frequency Modulation) system.

However, when the PFM method is used, there is a problem that it is difficult to output a stable power supply output voltage with a large voltage fluctuation and little output ripple. In addition, there is a problem that output voltage fluctuations such as output ripple due to switching occur when switching from the PWM system to the PFM system or switching from the PFM system to the PWM system. Even if the DC-DC converter using the PFM method is changed to a series regulator such as LDO (Low Drop Out regulator), there is a problem that output voltage fluctuation such as output ripple occurs due to switching.
JP 2003-9515 A (Page 7, FIG. 3)

  An object of the present invention is to provide a power supply apparatus capable of suppressing output voltage fluctuations such as output ripple at the time of light load and switching while maintaining high conversion efficiency at the time of light load, and a control method thereof.

  A power supply device according to one embodiment of the present invention includes a differential amplifier circuit and an offset generation circuit, receives an input voltage, and the first feedback voltage input to the differential amplifier circuit is changed by the offset generation circuit. A first output voltage higher than the rated output voltage is output in a light load region that is a load below a predetermined value, and a second output voltage that is lower than the rated output voltage is output in a heavy load region that is a load above a predetermined value. A series regulator that outputs and outputs the rated output voltage when changing from the light load region to the heavy load region; and an error amplifier; the input voltage is input; the first output voltage; the second output voltage; Alternatively, the second feedback voltage generated by the rated output voltage is input to the error amplifier, and the operation is stopped based on the first output voltage in the light load region. A switching regulator that starts an operation based on the rated output voltage or the second output voltage when changing from a region to the heavy load region, and outputs the rated output voltage in the heavy load region. It is characterized by.

  Furthermore, a control method for a power supply device according to an aspect of the present invention is a control method for a power supply circuit including a step-down switching regulator and an LDO that operate in a PWM method, and in a light load region that is a load of a predetermined value or less. A step of outputting from the LDO a first output voltage higher than the rated output voltage, and when changing from the light load region to a heavy load region that is a load of a predetermined value or more, the LDO outputs the rated output voltage; Alternatively, a PWM signal is output from the pulse width modulation circuit of the switching regulator based on a second output voltage lower than the rated output voltage, and the switching regulator starts operation by the PWM signal; and the PWM signal A step of stopping the operation of the LDO by an LDO mode release signal generated based on Characterized in that it.

  ADVANTAGE OF THE INVENTION According to this invention, the power supply device which can suppress output voltage fluctuations, such as an output ripple, can be provided at the time of a light load and switching, maintaining a high conversion efficiency at the time of a light load, and its control method.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a power supply device according to Embodiment 1 of the present invention will be described with reference to the drawings. 1 is a circuit diagram showing a configuration of a power supply device, FIG. 2 is a diagram showing a relationship of an output voltage with respect to an output current of the LDO, and FIG. 3 is a diagram showing an operating state of the LDO and the DC-DC converter in a load region of the power supply device. It is. In this embodiment, a step-down DC-DC converter using an LDO (Low Drop Out regulator) having a slope in output current-output voltage and a PWM (Pulse Width Modulation) method is used for the power supply device.

  As shown in FIG. 1, the power supply device 40 is provided with a DC-DC converter 1 and an LDO 2. The input power supply (input voltage) Vin input to the DC-DC converter 1 is stepped down by the DC-DC converter 1, and the stepped down output voltage Vout is output to the load 18. The input power supply (input voltage) Vin input to the LDO 2 is stepped down by the LDO 2, and the stepped down output voltage Vout is output to the load 18. The power supply device 40 is used in, for example, a mobile terminal where conversion efficiency is important and low output ripple is required.

  The DC-DC converter 1 is a switching regulator using a PWM method in a synchronous rectification method. The DC-DC converter 1 includes an error amplifier 11, a phase compensation circuit 12, a triangular wave generation circuit 13, a pulse width modulation circuit 14, a pre-driver 15, a monitor amplifier 16, a sample hold circuit 17, a reference voltage generation circuit 19, and a Pch MOS transistor. PT1, Pch MOS transistor PT2, Nch MOS transistor NT1, resistors R1 to R3, an inductor L1, and a capacitor C1 are provided. The MOS transistor is also referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  The Pch MOS transistor PT1 has a source connected to the input power supply (input voltage) Vin, a drain connected to the node LX, a gate connected to the node N5, and a control output from the node N5 on the output side of the predriver 15. This is a high-side switching element that operates “ON” and “OFF” in response to a signal.

  The Nch MOS transistor NT1 has a drain connected to the node LX, a source connected to the low potential side power supply Vss, a gate connected to the node N6, and a control signal output from the node N6 on the output side of the pre-driver 15. This is a low-side switching element that operates “ON” and “OFF”. Here, the Pch MOS transistor PT1 or the Nch MOS transistor NT1 operates (synchronous rectification method), and an output voltage Vout having a constant voltage is output from the node LX.

  The resistor R3 has one end connected to the input power source (input voltage) Vin and the other end connected to the source of the Pch MOS transistor PT2. The Pch MOS transistor PT2 has a drain connected to the node LX, a gate connected to the node N5, and operates “ON” and “OFF” by a control signal output from the node N5 on the output side of the predriver 15.

  Here, the Pch MOS transistor PT2 is turned on and off under the same conditions as the Pch MOS transistor PT1 by the control signal output from the node N5 on the output side of the pre-driver 15, for example, with the Pch MOS transistor PT1. The same shape and the same threshold voltage (Vth) are preferable.

  The inductor L1 has one end connected to the node LX and the other end connected to the output voltage Vout side. The capacitor C1 is an output smoothing capacitor having one end connected to the output voltage Vout side and the other end connected to the low potential side power source Vss. The resistor R1 has one end connected to the output voltage Vout side and the other end connected to the node N1. The resistor R2 has one end connected to the node N1 and the other end connected to the low potential side power source Vss. From node N1, feedback voltage VS1 divided by resistors R1 and R2 is generated.

  The reference voltage generation circuit 19 is provided between the + side of the error amplifier 11 and the low potential side power source Vss, and generates the reference voltage Vref1. The error amplifier 11 is provided between the resistor R1 and the resistor R2, and between the reference voltage generation circuit 19 and the phase compensation circuit 12, and inputs the feedback voltage VS1 to the-side and the reference voltage Vref1 to the + side, and outputs an output signal that is compared and amplified. Are output from the node N2 on the output side. Here, they are expressed as + side and − side, but they are also expressed as inverting input terminals or non-inverting input terminals (hereinafter, expressed as + side and − side).

  Here, when the feedback voltage VS1 is lower than the reference voltage Vref1, an output signal of “High” level is output from the error amplifier 11, and when the feedback voltage VS1 is higher than the reference voltage Vref1, the error amplifier 11 outputs “ A low "level output signal is output.

  The phase compensation circuit 12 is provided between the pulse width modulation circuit 14 and the error amplifier 11, and receives an output signal output from the output-side node N2 of the error amplifier 11, and outputs the phase-compensated output signal as an output-side node. Output from N3. The triangular wave generation circuit 13 generates a triangular wave. The pulse width modulation circuit 14 is provided between the phase compensation circuit 12 and the triangular wave generation circuit 13 and the pre-driver 15, and inputs an output signal output from the node N3 on the output side of the phase compensation circuit 12 to the negative side, thereby obtaining a triangular wave. A triangular wave signal output from the generation circuit 13 is input to the + side, and a pulse width modulated PWM signal is output from the output side node N4.

  The pre-driver 15 is provided between the sample and hold circuit 17, the Pch MOS transistor PT 1, the Pch MOS transistor PT 2, the Nch MOS transistor NT 1 and the pulse width modulation circuit 14. Then, the PWM signal output from the output side node N4 of the pulse width modulation circuit is input, and the control signal for controlling the operation of the Pch MOS transistors PT1 and PT2 is sent from the output side node N5 to the sample hold circuit 17, Pch MOS. A control signal for controlling the operation of the Nch MOS transistor NT1 is outputted from the output side node N6 to the gate of the Nch MOS transistor NT1 and outputted to the gate of the transistor PT1 and the gate of the Pch MOS transistor PT2.

  The monitor amplifier 16 is provided between the resistor R3 and the sample hold circuit 17, and monitors the current flowing through the resistor R3 when the Pch MOS transistor PT2 is "ON".

  The sample and hold circuit 17 is provided between the pre-driver 15 and the monitor amplifier 16 and the offset generation circuit 21 of the LDO 2, inputs the monitor current output from the monitor amplifier 16, and outputs it to the node N 5 on the output side of the pre-driver 15. The Pch MOS transistors PT1 and PT2 are sampled and held by a control signal for driving, and a voltage signal corresponding to the current level is output from the node N12 on the output side. Specifically, the signal level of the voltage signal increases as the value of the current flowing through the resistor R3 increases.

  Here, the resistor R 3, the Pch MOS transistor PT 2, the monitor amplifier 16, and the sample hold circuit 17 function as a current detection unit, and monitor the current flowing through the resistor R 3 that is proportional to the output current Iout of the power supply device 40. Instead of the current detection unit, for example, a voltage detection unit that monitors the voltage across the resistor R3 may be used.

  LDO2 is a step-down series regulator. The LDO 2 includes an offset generation circuit 21, a reference voltage generation circuit 22, a differential amplifier circuit 23, a Pch MOS transistor PT11, a resistor R11, and a resistor R12.

  The Pch MOS transistor PT11 has a source connected to the input power supply (input voltage) Vin, a drain connected to the node N13, a gate connected to the node N11, and output from the node N11 on the output side of the differential amplifier circuit 23. "ON" and "OFF" are operated by the control signal.

  The resistor R11 has one end connected to the node N13 and the other end connected to the node N10. The resistor R12 has one end connected to the node N10 and the other end connected to the low potential side power source Vss. From node N10, feedback voltage VS2 divided by resistors R11 and R12 is generated.

  The offset generation circuit 21 is provided between the sample hold circuit 17, the resistor R11, the resistor R12, and the positive side of the differential amplifier circuit 23, receives the feedback voltage VS2, and outputs it from the node N12 on the output side of the sample hold circuit. The offset feedback voltage VS2a is output between the positive sides of the differential amplifier circuit 23 based on the voltage signal.

  Specifically, the offset generation circuit 21 has, for example, two MOS transistors having different drive capabilities that form a differential pair, and the feedback voltage VS2 is input to the gate of one MOS transistor, and the gate of the other MOS transistor is input to the other MOS transistor. A voltage signal output from the sample hold circuit 17 is input, and a feedback voltage VS2a to which an offset value is added is output from the output side. When the current flowing through the resistor R3 is small (light load), a feedback voltage VS2a (VS2a> VS2) higher than the feedback voltage VS2 is output, and when the current flowing through the resistor R3 is large (when heavy load), the feedback voltage A feedback voltage VS2a (VS2a <VS2) lower than VS2 is output.

  The reference voltage generation circuit 22 is provided between the negative side of the differential amplifier circuit 23 and the low potential side power supply Vss, and generates the reference voltage Vref2. The differential amplifier circuit 23 is a non-inverting comparison type comparator, is provided between the offset generation circuit 21 and the reference voltage generation circuit 22 and the Pch MOS transistor PT11, and receives the feedback voltage VS2a offset to the + side, The reference voltage Vref2 is input to the side and a signal amplified and compared is output from the output-side node N11 to the gate of the Pch MOS transistor PT11.

  Specifically, when the feedback voltage VS2a is higher than the reference voltage Vref2, an output signal of “High” level is output from the differential amplifier circuit 23. When the feedback voltage VS2a is lower than the reference voltage Vref2, the differential amplifier circuit 23 outputs a “Low” level output signal.

  Here, unlike the conventional series regulator, the LDO 2 is provided with an offset generation circuit 21. For this reason, as shown in FIG. 2, the output voltage Vout characteristic with respect to the output current Iout of the LDO 2 is larger than the rated output voltage (Vout (typ.)) In the light load region (the output current Iout is largest near zero). In the heavy load region, it is set smaller than the rated output voltage (Vout (typ.)) (The output current Iout is the smallest at the maximum value). Moreover, the output voltage Vout decreases linearly as the output current Iout increases, and the output voltage Vout is set to the rated output voltage (Vout (typ.)) Between the light load region and the heavy load region. . The DC-DC converter 1 outputs a rated output voltage (Vout (typ.)) That is a constant output voltage.

  This is because the output current Iout is small (or zero), that is, when the Pch MOS transistor PT1 is “ON” and a relatively small current flows through the resistor R3 (or zero), the output is output from the offset generation circuit 21. This is because the feedback voltage VS2a is set larger than the feedback voltage VS2 input to the offset generation circuit 21 (VS2a-VS2> 0), while the output current Iout is large, that is, the Pch MOS transistor PT1 is turned “ON”. When a relatively large current flows through the resistor R3, the feedback voltage VS2a output from the offset generation circuit 21 is set to be smaller than the feedback voltage VS2 input to the offset generation circuit 21 (VS2a−VS2> 0). This is because that.

  Since the output voltage Vout output from the LDO 2 is higher than the rated output voltage (Vout (typ.)) In the light load region, the feedback voltage VS1 of the DC-DC converter 1 is set larger than the reference voltage Vref1, and It is set larger than the feedback voltage VS1 at the rated output voltage (Vout (typ.)). For this reason, an “Low” level output signal is output from the error amplifier 11, a PWM signal is not output from the pulse width modulation circuit 14, and the DC-DC converter 1 does not start.

  Therefore, as shown in FIG. 3, only the LDO 2 operates in the light load region, and the DC-DC converter 1 does not operate. On the other hand, the LDO 2 and the DC-DC converter 1 operate in the heavy load region.

  Here, the light load region refers to a region where the load is a predetermined value or less. The heavy load region refers to a region where the load is a predetermined value or more. Since the DC-DC converter 1 that is a switching regulator operates by a PWM signal that intermittently changes to a “High” level or a “Low” level, the predetermined value here is, for example, an inductor L1 of the DC-DC converter 1 This is a value when the inductor current flowing through the terminal changes from a positive value (flowing toward the load 18 side) to zero. The light load region refers to a region where the inductor current includes zero and − values (flows on the opposite side to the load 18 side direction), for example, and refers to a region of about 10% or less of the maximum output current. The heavy load region refers to, for example, a region where the inductor current has a positive value (flows in the direction toward the load 18).

  As described above, in the power supply device of the present embodiment, the DC-DC converter 1 and the LDO 2 are provided. The DC-DC converter 1 includes an error amplifier 11, a phase compensation circuit 12, a triangular wave generation circuit 13, a pulse width modulation circuit 14, a pre-driver 15, a monitor amplifier 16, a sample hold circuit 17, a reference voltage generation circuit 19, and a Pch MOS transistor. PT1, Pch MOS transistor PT2, Nch MOS transistor NT1, resistors R1 to R3, an inductor L1, and a capacitor C1 are provided. The LDO 2 includes an offset generation circuit 21, a reference voltage generation circuit 22, a differential amplifier circuit 23, a Pch MOS transistor PT11, a resistor R11, and a resistor R12. Based on the voltage signal output from the sample-and-hold circuit 17 of the DC-DC converter 1, the offset generation circuit 21 has a feedback voltage VS2a (higher than the feedback voltage VS2 when the current flowing through the resistor R3 is small (light load)). (Positive offset amount) is output to the + side of the differential amplifier circuit 23, and when the current flowing through the resistor R3 is large (during heavy load), the feedback voltage VS2a (negative offset amount) lower than the feedback voltage VS2 is differentially output. Output to the + side of the amplifier circuit 23. For this reason, the output voltage Vout characteristic with respect to the output current Iout of the LDO 2 is set larger than the rated output voltage in the light load region and smaller than the rated output voltage in the heavy load region. Since the output voltage Vout output from the LDO2 is higher than the rated output voltage in the light load region, the feedback voltage VS1 of the DC-DC converter 1 is set larger than the reference voltage Vref1 (and the feedback voltage VS1 at the rated output voltage). The Therefore, an “Low” level output signal is output from the error amplifier 11 and the DC-DC converter 1 does not start. When changing from the light load region to the heavy load region, the feedback voltage VS1 of the DC-DC converter 1 gradually decreases, and the DC-DC converter 1 starts to be activated when it begins to decrease below the reference voltage Vref1.

  Therefore, only the LDO 2 operates in the light load region, and the DC-DC converter 1 does not operate. On the other hand, the LDO 2 and the DC-DC converter 1 operate in the heavy load region. Since only the LDO 2 operates in the light load region, generation of output ripple of the power supply device 40 can be significantly suppressed. Since the DC-DC converter 1 gradually rises when changing from the light load region to the heavy load region, generation of output ripple of the power supply device 40 is significantly suppressed when switching from the light load region to the heavy load region. be able to.

  In this embodiment, a Pch MOS transistor is used as the high-side switching element and an Nch MOS transistor is used as the low-side switching element. However, an Nch MOS transistor is used as the high-side switching element and an Nch MOS transistor is used as the low-side switching element. A transistor may be used. Further, a Pch MOS transistor may be used as the high-side switching element, and a Pch MOS transistor may be used as the low-side switching element. Further, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate insulating film may be used instead of the MOS transistor.

  Next, a power supply device and a control method thereof according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing the configuration of the power supply apparatus. In this embodiment, the operation of the LDO is stopped under heavy load.

  As illustrated in FIG. 4, the power supply device 40 a includes a DC-DC converter 1, an LDO 2, and an LDO mode release unit 3. The input power supply (input voltage) Vin input to the DC-DC converter 1 is stepped down by the DC-DC converter 1, and the stepped down output voltage Vout is output to the load 18. The input power supply (input voltage) Vin input to the LDO 2 is stepped down by the LDO 2, and the stepped down output voltage Vout is output to the load 18.

  The power supply device 40a is used in, for example, a mobile terminal where conversion efficiency is important and low output ripple is required. The DC-DC converter 1 is a switching regulator using a PWM method in a synchronous rectification method. Note that the configurations of the DC-DC converter 1 and the LDO 2 are the same as those in the first embodiment, and a description thereof is omitted.

  The LDO mode release unit 3 is provided with a flip-flop 31, a notch filter 32, and a gate potential setting circuit 33.

  The flip-flop 31 is an RS flip-flop, is provided between the pulse width modulation circuit 14 and the notch filter 32, and is output from a node N4 on the output side of the pulse width modulation circuit 14 of the DC-DC converter 1. Is input to the S side (set side), for example, a trigger signal output from an oscillator or the like is input to the R side (reset side), and an LDO mode signal is output from the node N21 on the output side (Q side). Here, the LDO mode signal becomes “High” which is “Active” when the PWM signal is input and reset by the trigger signal.

  The notch filter 32 is also called a comb filter, and is provided between the flip-flop 31 and the gate potential setting circuit 33, attenuates the noise of the LDO mode signal output from the node N21 on the output side of the flip-flop 31, and outputs The node L22 outputs an LDON mode signal in which the noise of the LDO mode signal is attenuated.

  The gate potential setting circuit 33 is provided between the notch filter 32 and the Pch MOS transistor PT11, and receives an LDON mode signal output from the node N22 on the output side of the notch filter 32. Based on this signal, the “Vin” level is input. Is output to the gate of the Pch MOS transistor PT11.

  Next, the operation of the power supply apparatus will be described with reference to FIGS. FIG. 5 is a timing chart showing the operation of the power supply device, and FIG. 6 is a diagram showing the operation state of the LDO and the DC-DC converter in the load region of the power supply device. Here, the operation of the power supply device shown in FIG. 5 is when the output current gradually changes from the light load state to the heavy load state.

  As shown in FIG. 5, when the output current is small in the light load state (period until time T1), the LDO2 operates because the feedback voltage VS2a input to the differential amplifier circuit 23 is higher than the reference voltage Vref2, Moreover, since the feedback voltage VS2a is higher than the feedback voltage VS2, the output voltage Vout that is output is higher than the rated output voltage (Vout (typ.)). On the other hand, since the feedback voltage VS1 input to the error amplifier 11 of the DC-DC converter 1 is higher than the reference voltage Vref1, an output signal of “Low” level is output from the error amplifier 11, and the DC-DC converter does not operate. .

  Next, when the output current Iout increases and the feedback voltage VS1 becomes smaller than the reference voltage Verf1 (period Ta from time T1 to time T2), the output signal level of the error amplifier 11 gradually increases. Note that LDO2 operates in the period Ta (VS2a> Vref2).

  Subsequently, at time T2 when the output current Iout increases and the comparatively amplified output signal output from the error amplifier 11 becomes equal to or higher than a predetermined level, a PWM signal is output from the pulse width modulation circuit 14, and the DC-DC converter 1 Starts operation. On the other hand, the PWM signal is output to the LDO mode release unit 3, the LDO mode signal output from the flip-flop 31 becomes “Active” based on the trigger signal, and the LDO mode release signal Sen is output from the LDO mode release unit 3 to LDO 2. As a result, the gate of the Pch MOS transistor PT11 of the LDO2 becomes the “Vin” level which is the “High” level. As a result, the Pch MOS transistor PT11 is “OFF” and the LDO2 stops operating.

  Here, the error amplifier 11 starts operating at the time T1 when the output voltage of the LDO2 is the rated output voltage at the time when the error amplifier 11 changes from the light load region to the heavy load region, but the output voltage of the LDO2 May become lower than the rated output voltage, and the operation of the error amplifier 11 may be started when the feedback voltage VS1 generated based on the lowered output voltage is input.

  As the signal level of the comparatively amplified output signal output from the error amplifier 11 increases, the duty of the PWM signal output from the pulse width modulation circuit 14 increases (the ratio of time in the “High” level period increases). ). Thereafter, the duty of the PWM signal is changed according to the level of the output current Iout.

  Here, unlike the power supply device of the first embodiment, the power supply device 40a described above is provided with the LDO mode release unit 3. For this reason, as shown in FIG. 6, only the LDO 2 operates in the light load region, and the DC-DC converter 1 does not operate. On the other hand, only the DC-DC converter 1 operates in the heavy load region. Note that the output voltage Vout in the light load region has an output current Iout-output voltage Vout characteristic of the LDO 2 shown in FIG. The output voltage in the heavy load region becomes the rated output voltage (Vout (typ.)) Of a constant output voltage.

  Since only the LDO 2 operates in the light load region, generation of output ripple of the power supply device 40a can be significantly suppressed. Since the LDO 2 does not operate in the heavy load region and only the DC-DC converter 1 operates, high efficiency can be achieved. Then, when changing from the light load region to the heavy load region, the DC-DC converter 1 gradually rises (the feedback voltage VS1 gradually decreases, and the difference between the reference voltage Vref1 and the feedback voltage VS1 gradually increases). Therefore, when the light load region is switched to the heavy load region, the generation of output ripple of the power supply device 40a can be significantly suppressed.

  Next, the operation when the power supply device 40a changes from the heavy load state to the light load state will be described. When the output current Iout is large in the heavy load region, a PWM signal is output from the pulse width modulation circuit by the comparatively amplified output signal output from the error amplifier 11, the DC-DC converter 1 operates, and the LDO 2 stops operating. ing.

  Next, when the output current Iout gradually decreases in the heavy load region, the signal level of the comparatively amplified output signal output from the error amplifier 11 decreases, and the duty of the PWM signal output from the pulse width modulation circuit decreases. To do. In this period, the DC-DC converter 1 operates and the LDO 2 stops operating.

  Subsequently, when changing from the heavy load region to the light load region, if the output signal level of the error amplifier 11 falls below a predetermined level, the PWM signal is not output from the pulse width modulation circuit, and the DC-DC converter 1 operates. The LDO 2 is stopped and the LDO mode release signal Sen is not output, so that the LDO 2 starts its operation.

  When the output current Iout is small in the light load region, the DC-DC converter 1 does not operate and the LDO 2 operates. That is, the operation when the power supply device 40a changes from the heavy load state to the light load state is the same as the operation when the power supply device 40a changes from the light load state to the heavy load state. Efficiency can be achieved.

  As described above, in the power supply device and the control method thereof according to the present embodiment, the DC-DC converter 1, the LDO 2, and the LDO mode release unit 3 are provided. The DC-DC converter 1 includes an error amplifier 11, a phase compensation circuit 12, a triangular wave generation circuit 13, a pulse width modulation circuit 14, a pre-driver 15, a monitor amplifier 16, a sample hold circuit 17, a reference voltage generation circuit 19, and a Pch MOS transistor. PT1, Pch MOS transistor PT2, Nch MOS transistor NT1, resistors R1 to R3, an inductor L1, and a capacitor C1 are provided. The LDO 2 includes an offset generation circuit 21, a reference voltage generation circuit 22, a differential amplifier circuit 23, a Pch MOS transistor PT11, a resistor R11, and a resistor R12. The LDO mode release unit 3 is provided with a flip-flop 31, a notch filter 32, and a gate potential setting circuit 33. Based on the voltage signal output from the sample-and-hold circuit 17 of the DC-DC converter 1, the offset generation circuit 21 has a feedback voltage VS2a (higher than the feedback voltage VS2 when the current flowing through the resistor R3 is small (light load)). (Positive offset amount) is output to the + side of the differential amplifier circuit 23, and when the current flowing through the resistor R3 is large (during heavy load), the feedback voltage VS2a (negative offset amount) lower than the feedback voltage VS2 is differentially output. Output to the + side of the amplifier circuit 23. For this reason, the output voltage Vout characteristic with respect to the output current Iout of the LDO 2 is set larger than the rated output voltage in the light load region and smaller than the rated output voltage in the heavy load region. Since the output voltage Vout output from the LDO2 is higher than the rated output voltage in the light load region, the feedback voltage VS1 of the DC-DC converter 1 is set larger than the reference voltage Vref1. For this reason, an output signal is not output from the error amplifier 11, and the DC-DC converter 1 does not start. When changing from the light load region to the heavy load region, the feedback voltage VS1 of the DC-DC converter 1 gradually decreases, and the DC-DC converter 1 starts to be activated when it begins to decrease below the reference voltage Vref1. When the PWM signal is output from the pulse width modulation circuit 14, the LDO mode release unit 3 outputs an LDO mode release signal Sen for stopping the operation of the LDO 2 to the gate of the Pch MOS transistor PT 11 of the LDO 2. The LDO 2 stops operating in response to the LDO mode release signal Sen.

  Therefore, only the LDO 2 operates in the light load region, and the DC-DC converter 1 does not operate. On the other hand, in the heavy load region, the LDO 2 stops operating and only the DC-DC converter 1 operates. Since only the LDO 2 operates in the light load region, generation of output ripple of the power supply device 40 can be significantly suppressed. Since the DC-DC converter 1 gradually rises when changing from the light load region to the heavy load region, generation of output ripple of the power supply device 40 is significantly suppressed when switching from the light load region to the heavy load region. be able to. Further, since the LDO 2 stops operating in the heavy load region, the conversion efficiency is improved as compared with the first embodiment.

  In this embodiment, the DC-DC converter 1 uses a synchronous rectification type switching regulator. However, the asynchronous rectification method in which the Nch MOS transistor NT1 which is a switching element on the low side is replaced with, for example, a diode or a Schottky diode. The switching regulator may be used.

  Next, a power supply device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram showing the configuration of the power supply device, and FIG. 8 is a diagram showing the relationship of the output voltage with respect to the output current of the DC-DC converter. In the present embodiment, the DC-DC converter having a slope in the output current-output voltage using the PWM method operates at the heavy load, and the LDO operates at the light load.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 7, the power supply device 40b is provided with a DC-DC converter 1b, an LDO 2b, and an LDO mode release unit 3. The input power supply (input voltage) Vin input to the DC-DC converter 1 b is stepped down by the DC-DC converter 1 b, and the stepped down output voltage Vout is output to the load 18. The input power supply (input voltage) Vin input to the LDO 2 b is stepped down by the LDO 2 b, and the stepped down output voltage Vout is output to the load 18. The power supply device 40b is used in, for example, a mobile terminal where conversion efficiency is regarded as important and low output ripple is required.

  The DC-DC converter 1b is a switching regulator using a PWM method in a synchronous rectification method. The DC-DC converter 1b includes an error amplifier 11, a phase compensation circuit 12, a triangular wave generation circuit 13, a pulse width modulation circuit 14, a pre-driver 15, a monitor amplifier 16, a sample hold circuit 17, a reference voltage generation circuit 19, and an offset generation circuit. 21b, a Pch MOS transistor PT1, a Pch MOS transistor PT2, an Nch MOS transistor NT1, resistors R1 to R3, an inductor L1, and a capacitor C1 are provided.

  The sample hold circuit 17 is provided between the pre-driver 15 and the monitor amplifier 16 and the offset generation circuit 21b, receives the monitor current output from the monitor amplifier 16, and outputs the monitor current to the node N5 on the output side of the pre-driver 15. The control signal for driving the Pch MOS transistors PT1 and PT2 is sampled and held, and a voltage signal corresponding to the current level is output from the node N14 on the output side to the offset generation circuit 21b. Specifically, the signal level of the voltage signal increases as the value of the current flowing through the resistor R3 increases.

  The offset generation circuit 21b is provided between the resistors R1 and R2 and between the sample hold circuit 17 and the negative side of the error amplifier 11, receives the feedback voltage VS1, and is output from the node N14 on the output side of the sample hold circuit. Based on the signal, the offset feedback voltage VS1a is output to the negative side of the error amplifier.

  Specifically, the offset generation circuit 21b has, for example, a MOS transistor with a different driving capability that forms a differential pair (the driving capability setting is reversed from that of the offset generation circuit 21), and the gate of one of the MOS transistors The voltage signal output from the sample hold circuit 17 is input to the gate, the feedback voltage VS1 is input to the gate of the other MOS transistor, and the feedback voltage VS1a added with the offset value is output from the output side. When the current flowing through the resistor R3 is small (light load), a feedback voltage VS1a (VS1a> VS1) higher than the feedback voltage VS1 is output, and when the current flowing through the resistor R3 is large (when heavy load), the feedback voltage A feedback voltage VS1a (VS1a <VS1) lower than VS1 is output.

  The error amplifier 11 is provided between the reference voltage generation circuit 19 and the offset generation circuit 21b and the phase compensation circuit 12, and inputs the feedback voltage VS1a to the negative side and the reference voltage Vref1 to the positive side, and outputs a comparison amplified output signal. From the side node N2.

  Here, when the feedback voltage VS1a is lower than the reference voltage Vref1, an output signal that is compared and amplified is output from the error amplifier 11, and when the feedback voltage VS1a is higher than the reference voltage Vref1, an output of “Low” level is output from the error amplifier 11. A signal is output.

  The LDO 2b is a step-down type series regulator. The LDO 2b is provided with a reference voltage generation circuit 22, a differential amplifier circuit 23, a Pch MOS transistor PT11, a resistor R11, and a resistor R12. Here, the LDO 2b outputs a rated output voltage (Vout (typ.)), Which is a constant output voltage, as in the conventional step-down series regulator.

  The differential amplifier circuit 23 is a non-inverting comparison type comparator, which is provided between the resistor R11, the resistor R12, and the reference voltage generation circuit 22 and the Pch MOS transistor PT11, and receives the feedback voltage VS2 on the + side, Is supplied with the reference voltage Vref2 and outputs a differentially amplified signal from the node N11 on the output side to the gate of the Pch MOS transistor PT11.

  Specifically, when the feedback voltage VS2 is higher than the reference voltage Vref2, an output signal of “High” level is output from the differential amplifier circuit 23. When the feedback voltage VS2 is lower than the reference voltage Vref2, the differential amplifier circuit 23 outputs a “Low” level output signal. Note that the configuration and operation of the LDO mode canceling unit 3 are the same as those in the second embodiment, and a description thereof is omitted.

  Here, unlike the conventional DC-DC converter, the DC-DC converter 1b is provided with an offset generation circuit 21b. For this reason, as shown in FIG. 8, the output voltage Vout characteristic with respect to the output current Iout of the DC-DC converter 1b is lower than the rated output voltage (Vout (typ.)) In the light load region (the output current Iout is near zero). In the heavy load region, it is set higher than the rated output voltage (Vout (typ.)) (The output current Iout is the highest at the maximum value). Moreover, the output voltage Vout increases linearly as the output current Iout increases, and the output voltage Vout is set to the rated output voltage (Vout (typ.)) Between the light load region and the heavy load region.

  This is because in a light load state where the output current Iout is small (or zero), the feedback voltage VS1a output from the offset generation circuit 21b is set smaller than the feedback voltage VS1 input to the offset generation circuit 21b (VS1a <VS1). On the other hand, in the heavy load region where the output current Iout is large, the feedback voltage VS1a output from the offset generation circuit 21b is set larger than the feedback voltage VS1 input to the offset generation circuit 21b (VS1a> This is because VS1).

  In the light load region, only the LDO 2b operates. In the heavy load region, the DC-DC converter 1b operates, the PWM signal output from the pulse width modulation circuit 14 is input to the LDO mode release unit 3, and the LDO mode release signal Sen is input to the LDO 2b. Then, the LDO 2b stops operating.

  It should be noted that the output voltage Vout in the light load region is a rated output voltage Vout (typ.) That is a constant output voltage. The output voltage Vout in the heavy load region has an output current Iout-output voltage Vout characteristic of the DC-DC converter 1b shown in FIG.

  For this reason, in the light load region, the generation of output ripple of the power supply device 40b can be significantly suppressed. Since the DC-DC converter 1b gradually rises when changing from the light load region to the heavy load region, generation of output ripple of the power supply device 40b is greatly suppressed when switching from the light load region to the heavy load region. be able to. Since only the DC-DC converter 1b operates in the heavy load region, the conversion efficiency can be increased.

  As described above, in the power supply unit of the present embodiment, the DC-DC converter 1b, the LDO 2b, and the LDO mode release unit 3 are provided. The DC-DC converter 1b includes an error amplifier 11, a phase compensation circuit 12, a triangular wave generation circuit 13, a pulse width modulation circuit 14, a pre-driver 15, a monitor amplifier 16, a sample hold circuit 17, a reference voltage generation circuit 19, and an offset generation circuit. 21b, a Pch MOS transistor PT1, a Pch MOS transistor PT2, an Nch MOS transistor NT1, resistors R1 to R3, an inductor L1, and a capacitor C1 are provided. The LDO 2b is provided with a reference voltage generation circuit 22, a differential amplifier circuit 23, a Pch MOS transistor PT11, a resistor R11, and a resistor R12. The LDO mode release unit 3 is provided with a flip-flop 31, a notch filter 32, and a gate potential setting circuit 33. Based on the voltage signal output from the sample and hold circuit 17, the offset generation circuit 21b applies the feedback voltage VS1a higher than the feedback voltage VS1 to the negative side of the error amplifier 11 when the current flowing through the resistor R3 is small (light load). When the current flowing through the resistor R3 is large (when the load is heavy), the feedback voltage VS1a lower than the feedback voltage VS1 is output to the negative side of the differential amplifier circuit 23. For this reason, the output voltage Vout characteristic with respect to the output current Iout of the DC-DC converter 1b is set smaller than the rated output voltage in the light load region and larger than the rated output voltage in the heavy load region. Since the output voltage Vout of the DC-DC converter 1b is lower than the rated output voltage in the light load region, no output signal is output from the error amplifier 11, and the DC-DC converter 1b does not start. When changing from the light load region to the heavy load region, the feedback voltage VS1a of the DC-DC converter 1b gradually decreases, and when starting to decrease below the reference voltage Vref1, the DC-DC converter 1b starts to start. When the PWM signal is output from the pulse width modulation circuit 14, the LDO mode release unit 3 outputs an LDO mode release signal Sen for stopping the operation of the LDO 2b to the gate of the Pch MOS transistor PT11 of the LDO 2b. The LDO 2b stops operating in response to the LDO mode release signal Sen.

  Therefore, only the LDO 2b operates in the light load region, and the DC-DC converter 1b does not operate. On the other hand, in the heavy load region, the LDO 2b stops operating and only the DC-DC converter 1b operates. Since only the LDO 2b operates in the light load region, generation of output ripple of the power supply device 40b can be significantly suppressed. Since the DC-DC converter 1b gradually rises when changing from the light load region to the heavy load region, generation of output ripple of the power supply device 40b is greatly suppressed when switching from the light load region to the heavy load region. be able to. In addition, since the LDO 2b stops operating in the heavy load region, the conversion efficiency is improved as compared with the first embodiment.

  Next, a power supply device according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 9 is a circuit diagram showing the configuration of the power supply apparatus, and FIG. 10 is a diagram showing the relationship of the output voltage with respect to the output current of the LDO and the DC-DC converter. In this embodiment, an LDO having a slope in output current-output voltage and a DC-DC converter using a PWM system having a reverse slope in output current-output voltage are used for LDO.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 9, the power supply device 40c is provided with a DC-DC converter 1b, an LDO 2, and an LDO mode release unit 3. The input power supply (input voltage) Vin input to the DC-DC converter 1 b is stepped down by the DC-DC converter 1 b, and the stepped down output voltage Vout is output to the load 18. The input power supply (input voltage) Vin input to the LDO 2 is stepped down by the LDO 2, and the stepped down output voltage Vout is output to the load 18. The power supply device 40c is used for, for example, a mobile terminal where conversion efficiency is regarded as important and low output ripple is required. The DC-DC converter 1b is a switching regulator using a PWM method in a synchronous rectification method.

  The configuration and operation of the DC-DC converter 1b are the same as those of the third embodiment, the configuration and operation of the LDO 2 are the same as those of the first embodiment, and the configuration and operation of the LDO mode release unit 3 are the same as those of the second embodiment. The description is omitted.

  Here, unlike the conventional DC-DC converter, the DC-DC converter 1b is provided with an offset generation circuit 21b. Further, unlike the conventional series regulator, the LDO 2 is provided with an offset generation circuit 21.

  Therefore, as shown in FIG. 10, the output voltage Vout characteristic with respect to the output current Iout of the DC-DC converter 1b is lower than the rated output voltage (Vout (typ.)) In the light load region (the output current Iout is near zero). In the heavy load region, it is set higher than the rated output voltage (Vout (typ.)) (The output current Iout is the highest at the maximum value). Further, the output voltage Vout characteristic with respect to the output current Iout of the LDO2 is higher than the rated output voltage (Vout (typ.)) In the light load region (the output current Iout is highest near zero), and the rated output in the heavy load region. It is set lower than the voltage (Vout (typ.)) (The output current Iout is the lowest at the maximum value).

  This is because, in the DC-DC converter 1b, in a light load state where the output current Iout is small (or zero), the feedback voltage VS1a output from the offset generation circuit 21b is greater than the feedback voltage VS1 input to the offset generation circuit 21b. In contrast, in the heavy load region where the output current Iout is large, the feedback voltage VS1a output from the offset generation circuit 21b is the feedback voltage VS1 input to the offset generation circuit 21b. This is because it is set higher (VS1a> VS1).

  On the other hand, in the LDO2, when the output current Iout is small (or zero), that is, when the Pch MOS transistor PT1 is “ON” and a relatively small current flows through the resistor R3 (or zero), the output is generated from the offset generation circuit 21. This is because the feedback voltage VS2a to be set is set higher than the feedback voltage VS2 input to the offset generation circuit 21 (VS2a-VS2> 0). On the other hand, the output current Iout is large, that is, the Pch MOS transistor PT1 is “ When a relatively large current flows through the resistor R3 after being turned ON, the feedback voltage VS2a output from the offset generation circuit 21 is set lower than the feedback voltage VS2 input to the offset generation circuit 21 (VS2a−VS2> 0). Because it is done.

  In the light load region, only LDO2 operates. In the heavy load region, the DC-DC converter 1b operates, the PWM signal output from the pulse width modulation circuit 14 is input to the LDO mode canceling unit 3, and the LDO mode canceling signal Sen is input to LDO2. To stop. Note that the output voltage Vout in the light load region has an output current Iout-output voltage Vout characteristic of the LDO 2 shown in FIG. In the heavy load region, the output current Iout-output voltage Vout characteristic of the DC-DC converter 1b shown in FIG. 10 is obtained.

  For this reason, generation | occurrence | production of the output ripple of the power supply device 40c can be suppressed significantly in a light load area | region. Since the DC-DC converter 1b gradually rises when changing from the light load region to the heavy load region, generation of output ripple of the power supply device 40c is greatly suppressed when switching from the light load region to the heavy load region. be able to. Since only the DC-DC converter 1b operates in the heavy load region, the conversion efficiency can be increased.

  A straight line having a positive slope representing the relationship of the output voltage Vout with respect to the output current Iout of the DC-DC converter 1b and a straight line having a negative slope representing the relationship of the output voltage Vout to the output current Iout of the LDO2 are light load regions. It is preferable to cross between heavy load areas.

  As described above, in the power supply device according to the present embodiment, the DC-DC converter 1b, the LDO 2, and the LDO mode release unit 3 are provided. The DC-DC converter 1b includes an error amplifier 11, a phase compensation circuit 12, a triangular wave generation circuit 13, a pulse width modulation circuit 14, a pre-driver 15, a monitor amplifier 16, a sample hold circuit 17, a reference voltage generation circuit 19, and an offset generation circuit. 21b, a Pch MOS transistor PT1, a Pch MOS transistor PT2, an Nch MOS transistor NT1, resistors R1 to R3, an inductor L1, and a capacitor C1 are provided. The LDO 2 includes an offset generation circuit 21, a reference voltage generation circuit 22, a differential amplifier circuit 23, a Pch MOS transistor PT11, a resistor R11, and a resistor R12. The LDO mode release unit 3 is provided with a flip-flop 31, a notch filter 32, and a gate potential setting circuit 33. Based on the voltage signal output from the sample-and-hold circuit 17 of the DC-DC converter 1, the offset generation circuit 21 has a feedback voltage VS2a (higher than the feedback voltage VS2 when the current flowing through the resistor R3 is small (light load)). (Positive offset amount) is output to the + side of the differential amplifier circuit 23, and when the current flowing through the resistor R3 is large (during heavy load), the feedback voltage VS2a (negative offset amount) lower than the feedback voltage VS2 is differentially output. Output to the + side of the amplifier circuit 23. For this reason, the output voltage Vout characteristic with respect to the output current Iout of the LDO 2 is set larger than the rated output voltage in the light load region and smaller than the rated output voltage in the heavy load region. On the other hand, the offset generation circuit 21b generates a feedback voltage VS1a higher than the feedback voltage VS1 when the current flowing through the resistor R3 is small (light load) based on the voltage signal output from the sample hold circuit 17. When the current flowing through the resistor R3 is large (heavy load), the feedback voltage VS1a lower than the feedback voltage VS1 is output to the − side of the differential amplifier circuit 23. For this reason, the output voltage Vout characteristic with respect to the output current Iout of the DC-DC converter 1b is set smaller than the rated output voltage in the light load region and larger than the rated output voltage in the heavy load region. Since the output voltage Vout of the DC-DC converter 1b is lower than the rated output voltage in the light load region, no output signal is output from the error amplifier 11, and the DC-DC converter 1b does not start. When changing from the light load region to the heavy load region, the feedback voltage VS1a of the DC-DC converter 1b gradually decreases, and when it begins to decrease below the reference voltage Vref1, the DC-DC converter 1b starts to start. When the PWM signal is output from the pulse width modulation circuit 14, the LDO mode release unit 3 outputs an LDO mode release signal Sen for stopping the operation of the LDO 2 to the gate of the Pch MOS transistor PT 11 of the LDO 2. The LDO 2 stops operating in response to the LDO mode release signal Sen.

  Accordingly, only the LDO2 operates in the light load region, and the DC-DC converter 1b does not operate. On the other hand, in the heavy load region, the LDO 2 stops operating and only the DC-DC converter 1b operates. Since only the LDO2 operates in the light load region, the generation of output ripple of the power supply device 40c can be significantly suppressed. Since the DC-DC converter 1b gradually rises when changing from the light load region to the heavy load region, generation of output ripple of the power supply device 40c is greatly suppressed when switching from the light load region to the heavy load region. be able to. Further, since the LDO 2 stops operating in the heavy load region, the efficiency is improved as compared with the first embodiment.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the present invention is applied to a power supply device for a mobile terminal in which conversion efficiency is regarded as important. Further, although applied to a power supply device composed of a step-down switching regulator and an LDO, a step-up switching regulator, an inverting switching regulator, or a step-up / step-down switching regulator may be used for the power supply device. In that case, it is preferable to change the configuration of the series regulator to be compatible with the switching regulator.

Further, PFM (Pulse Frequency Modulation) control may be used instead of PWM control.

The present invention can be configured as described in the following supplementary notes.
(Additional remark 1) The input voltage is input, the first output voltage higher than the rated output voltage in a light load region that is a load below a predetermined value, and the above-mentioned rated output voltage in a heavy load region that is a load above a predetermined value A series having a low second output voltage and an output current-output voltage characteristic comprising the rated output voltage when changing from the light load region to the heavy load region and outputting the first and second output voltages A regulator, a third output voltage lower than the rated output voltage in the light load state, a fourth output voltage higher than the rated output voltage in the heavy load state, and the light load. An output current-output voltage characteristic composed of the rated output voltage when changing from a region to the heavy load region, the operation is stopped in the light load region, and the fourth output voltage is output in the heavy load region. A power supply device comprising a switching regulator that operates.

(Supplementary Note 2) The switching regulator operates in a PWM system, receives a PWM signal output from the switching regulator, and outputs a signal for stopping the operation of the series regulator by the PWM signal in the heavy load region to the series regulator. The power supply device according to appendix 1, further comprising a mode release unit for outputting.

(Supplementary Note 3) When an input voltage is input, a feedback voltage is input, and when the output current is small, a first feedback voltage added by a positive offset voltage is generated. When the output current is large, only a negative offset voltage is generated. An offset generation circuit for generating the added second reference voltage, and outputs a first output voltage higher than the rated output voltage in a light load region that is a load of a predetermined value or less based on the offset generation circuit; A series regulator that outputs a second output voltage lower than the rated output voltage in a heavy load region that is a load of a predetermined value or more, and the input voltage is input and a current proportional to the output current is monitored, A current detection unit that outputs a signal obtained by converting a current into a voltage to the offset generation circuit, and stops operation based on the first output voltage in the light load region; It said power supply apparatus comprising a switching regulator that outputs the rated output voltage by operating on the basis of the second output voltage in heavy load region.

(Supplementary Note 4) When a feedback voltage is input and the output current is small, a first feedback voltage added by a positive offset voltage is generated, and when the output current is large, a second feedback voltage is added by a negative offset voltage. Has an offset generation circuit for generating a reference voltage, inputs an input voltage, and outputs a first output voltage higher than the rated output voltage in a light load region that is a load of a predetermined value or less based on the offset generation circuit In a heavy load region that is a load of a predetermined value or more, a series regulator that outputs a second output voltage lower than the rated output voltage, and the input voltage is input and a current proportional to the output current is monitored. A current detection unit that outputs a signal obtained by converting a current into a voltage to the offset generation circuit; in the light load region, the operation is stopped based on the first output voltage; In the heavy load region, the operation is based on the second output voltage to output the rated output voltage, a switching regulator that operates in a PWM system, and a PWM signal that is output from the switching regulator are input. And a mode release unit that outputs a signal for stopping the operation of the series regulator to the series regulator by the PWM signal in a region.

(Supplementary note 5) The power supply device according to any one of supplementary notes 1 to 4, wherein the series regulator is an LDO, and the switching regulator is a step-down switching regulator.

(Supplementary Note 6) A method for controlling a power supply circuit including a step-down switching regulator that operates in a PWM system and an LDO, in a heavy load region that is a load of a predetermined value or more, from a pulse width modulation circuit of the switching regulator A PWM signal is output, the switching regulator is operated by the PWM signal, and the operation of the LDO is stopped by an LDO mode release signal generated based on the PWM signal; The output of the PWM signal is stopped, the operation of the switching regulator is stopped, the output of the LDO mode release signal is stopped, and the operation of the LDO is started. A method for controlling a power supply apparatus comprising:

1 is a circuit diagram showing a configuration of a power supply device according to Embodiment 1 of the present invention. The figure which shows the relationship of the output voltage with respect to the output current of LDO which concerns on Example 1 of this invention. The figure which shows the operation state of LDO and the DC-DC converter in the load state of the power supply device which concerns on Example 1 of this invention. The circuit diagram which shows the structure of the power supply device which concerns on Example 2 of this invention. The timing chart which shows operation | movement of the power supply device which concerns on Example 2 of this invention. The figure which shows the operation state of LDO and the DC-DC converter in the load state of the power supply device which concerns on Example 2 of this invention. The circuit diagram which shows the structure of the power supply device which concerns on Example 3 of this invention. The figure which shows the relationship of the output voltage with respect to the output current of the DC-DC converter which concerns on Example 3 of this invention. The circuit diagram which shows the structure of the power supply device which concerns on Example 4 of this invention. The figure which shows the relationship of the output voltage with respect to the output current of LDO and the DC-DC converter which concerns on Example 4 of this invention.

Explanation of symbols

1, 1b DC-DC converter 2, 2b LDO
3 LDO mode release unit 11 Error amplifier 12 Phase compensation circuit 13 Triangular wave generation circuit 14 Pulse width modulation circuit 15 Pre-driver 16 Monitor amplifier 17 Sample hold circuit 18 Loads 19 and 22 Reference voltage generation circuits 21 and 21b Offset generation circuit 23 Differential amplification Circuit 31 Flip-flop 32 Notch filter 33 Gate potential setting circuit 40, 40a, 40b, 40c Power supply device C1 Capacitor L1 Inductors N1-14, N21-23, LX node NT1 Nch MOS transistors PT1, PT2, PT11 Pch MOS transistors R1-3 , R11, R12 Resistor Sen LDO mode release signal Vin Input power supply (input voltage)
Vout Output voltage Vref1, Vref2 Reference voltage VS1, VS1a, VS2, VS2a Feedback voltage Vss Low potential side power supply

Claims (5)

A light load region comprising a differential amplifier circuit and an offset generation circuit, wherein an input voltage is input, and a first feedback voltage input to the differential amplifier circuit is changed by the offset generation circuit and is a load of a predetermined value or less Outputs a first output voltage higher than the rated output voltage, outputs a second output voltage lower than the rated output voltage in a heavy load region that is a load of a predetermined value or more, and outputs the second output voltage from the light load region. A series regulator that outputs the rated output voltage when changing to the load region; and
An error amplifier, the input voltage is input, and the first output voltage, the second output voltage, or the second feedback voltage generated by the rated output voltage is input to the error amplifier, and in the light load region The operation is stopped based on the first output voltage, and when changing from the light load region to the heavy load region, the operation is started based on the rated output voltage or the second output voltage. A switching regulator that outputs the rated output voltage in the load region;
A power supply device comprising: A series regulator that receives the input voltage and outputs the rated output voltage;
An error amplifier and an offset generation circuit are provided, the input voltage is input, a feedback voltage input to the error amplifier is changed by the offset generation circuit, and in a light load region that is a load of a predetermined value or less, the output voltage is higher than the rated output voltage. A low first output voltage, a second output voltage higher than the rated output voltage in a heavy load region that is a load of a predetermined value or more, and the rated output voltage when changing from the light load region to the heavy load region. Output current-voltage characteristics, and when the light load region stops operation based on the first output voltage and changes from the light load region to the heavy load region, the rated output voltage or the A switching regulator that starts an operation based on a second output voltage and outputs the second output voltage in the heavy load region;
A power supply device comprising: The switching regulator operates in a PWM system,
And a mode canceling unit configured to input a PWM signal output from the switching regulator and output a signal for stopping the operation of the series regulator to the series regulator by the PWM signal in the heavy load region. Item 3. The power supply device according to Item 1 or 2.   4. The power supply device according to claim 1, wherein the series regulator has a characteristic that an output voltage linearly decreases as an output current increases. 5. A method of controlling a power supply circuit having a step-down switching regulator and an LDO that operates in a PWM system,
Outputting a first output voltage higher than the rated output voltage from the LDO in a light load region that is a load of a predetermined value or less;
When switching from the light load region to a heavy load region that is a load greater than or equal to a predetermined value, the switching is performed based on the rated output voltage or a second output voltage lower than the rated output voltage. A step in which a PWM signal is output from the pulse width modulation circuit of the regulator, and the switching regulator starts operation by the PWM signal;
A step of stopping the operation of the LDO by an LDO mode release signal generated based on the PWM signal;
A control method for a power supply device comprising:

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