CN101226882B - 无须采用额外掩模以相同工艺制造存储与逻辑元件的方法 - Google Patents
无须采用额外掩模以相同工艺制造存储与逻辑元件的方法 Download PDFInfo
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Abstract
一种制造逻辑和非易失存储器件的方法,可通过一些额外步骤,利用公知CMOS工艺制造逻辑与存储器件。然而,这些额外步骤无须增加掩模。由此,该工艺可以在同样的衬底上,降低制造逻辑与存储器件的复杂度、时间、以及成本,对于嵌入应用尤其显著。
Description
技术领域
本发明的多个实施例所公开的内容涉及非易失存储器件,尤其涉及于采用相同工艺同时制造嵌入非易失存储器件与互补金属氧化物半导体(CMOS)逻辑器件。
背景技术
许多非易失半导体存储器采用公知的金属氧化物半导体(MOS)型结构。换句话说,这些结构包含栅极结构,并通过介质层与衬底分离,而扩散区域则植入栅极结构角落下的衬底区域。施加适当电压至扩散区域与控制栅极时,即可在衬底顶部的扩散区域之间与栅极结构下造成沟道。例如电子等载流子,即可经过沟道,流动于扩散区域之间。
若在栅极结构的方向上具有足够的电场分量,则例如电子等载流子,即会被吸引到栅极结构中。若电子具有足够的能量来克服介质层的能障高度,载流子就会隧穿穿过介质层。
非易失存储器件的一个例子是闪存存储器件。闪存存储器已经广泛应用于相当数量的非易失存储器应用之中。闪存元件最初用以取代紫外光可擦除可编程只读存储器(EPROM);然而,现在闪存存储器不但已经占据一次编程与EPROM的大部分市场,同时成为电可编程可擦除只读存储器(EEPROM)的强大竞争对手,甚至威胁某些随机存取存储器(RAM)的应用。
由于闪存存储器原为EPROM的替代品,多数闪存存储器设计由EPROM或EEPROM技术的单元衍生而来。由此,许多闪存单元的概念存有某些缺陷,就嵌入应用尤其显著。这些缺陷包含低编程速度、高能量消耗、高编程电压、过度擦除的问题、软写入问题、以及高度复杂的工艺。
此外,这个问题在嵌入应用中尤其显著,因存储单元常与CMOS逻辑和其他电路紧密整合;而闪存除了工艺复杂外,通常更具有无法与公知CMOS工艺相容的问题。因此,将闪存存储器包含在嵌入应用中,可能会大幅增加制造的时间与成本。
为解决上述闪存存储器的缺点,已经发展出几种新的存储器型式,尤其可针对嵌入应用;然而,这些新设计大多仍无法与公知CMOS工艺相容。有些较新的设计,可以部分与公知CMOS工艺相容,然而这些新设计仍然需要几道额外掩模。由此,相比于公知CMOS工艺,这些新设计仍然会增加时间、成本、与制造复杂度。
发明内容
一种半导体工艺,可同时制造存储电路与CMOS逻辑电路,而无须增加额外掩模。一种公知CMOS制造流程,可以用于形成CMOS逻辑电路与存储电路两者。存储电路需要额外制造步骤,但这些额外制造步骤无须增加掩模,因此可以大幅减低制造嵌入电路的时间、成本、与复杂度。
根据本发明的一方面,提供一种制造逻辑和非易失存储器件的方法,包含:形成氧化层于衬底上;形成氮化层于所述衬底上;施加高热处理,其至少足以造成某些氮原子由所述氮化层移动至所述衬底中;移除所述氮化层与所述氧化层;以及生长栅极氧化层于所述衬底之上,其中生长所述栅极氧化层造成所述衬底中捕获的这些氮原子移动至所述栅极氧化层中。
本发明的一种目的,为操作利用上述公开的方法所制造的非易失存储器件。
根据本发明的另一方面,提供一种编程可作为逻辑元件或者非易失存储器件中的一个元件的方法,所述元件包含形成于衬底上的栅极介质层,所述栅极介质层包含多个深空穴陷阱,形成于所述栅极介质层上的栅极电极,以及形成于所述衬底上的多个源极或漏极扩散区域,所述源极或漏极扩散区域邻接于所述栅极介质层,其步骤包含:施加负电压至所述栅极电极;施加衬底电压至所述衬底;以及施加扩散电压至所述源极与所述漏极扩散区域。
根据本发明的另一方面,提供一种擦除可作为逻辑元件或非易失存储器件中的一个元件的方法,所述元件包含形成于衬底上的栅极介质层,所述栅极介质层包含多个深空穴陷阱,形成于所述栅极介质层上的栅极电极,以及形成于所述衬底上的多个源极与漏极扩散区域,所述源极与所述漏极扩散区域邻接于所述栅极介质层,其步骤包含:施加正电压至所述栅极电极;施加衬底电压至所述衬底;以及施加扩散电压至所述源极与所述漏极扩散区域。
根据本发明的另一方面,提供一种读取可作为逻辑元件或非易失存储器件中的一个元件的方法,所述元件包含形成于衬底上的栅极介质层,所述栅极介质层包含多个深空穴陷阱,形成于所述栅极介质层上的栅极电极,以及形成于所述衬底上的多个源极与漏极扩散区域,所述源极与所述漏极扩散区域邻接于所述栅极介质层,其步骤包含:施加栅极电压至所述栅极电极;施加衬底电压至所述衬底;施加漏极电压至所述漏极扩散区域;以及施加源极电压至所述源极扩散区域。
根据本发明的再一方面,提供一种元件,可作为逻辑元件或存储器件,包含:形成于衬底上的栅极介质层,所述栅极介质层包含多个深空穴陷阱;形成于所述栅极介质层上的栅极电极;以及形成于所述衬底中的多个源极与漏极扩散区域。
本发明的这些与其他特征功能、目的、与实施例公开露于下列实施方式。
附图说明
本发明的特征功能、目的、与实施例参照下列附图共同说明:
图1A、图1B、图1C、图1D、图1E、图1F为剖面示意图,显示依据本发明一种实施例制造非易失存储器件的工艺。
图2A为流程图,显示制造CMOS逻辑元件的制造步骤。
图2B为流程图,显示依据本发明的一种实施例,制造非易失存储器或CMOS元件的范例工艺。
图3为示意图,显示依据图1A、图1B、图1C、图1D、图1E、图1F与图2的流程步骤所制造的元件。
图4为示意图,显示编程图3的元件的范例方法。
图5为示意图,显示一种擦除图3元件的方法范例。
图6A与图6B为示意图,显示读取图3元件的范例流程。
图7为图表,显示依据图1A、图1B、图1C、图1D、图1E、图1F与图2的制造流程所设定的非易失存储器件的持久程度。
图8为图表,显示依据图1A、图1B、图1C、图1D、图1E、图1F与图2的流程所制造的非易失存储器件的电流-电压(IV)曲线。
图9为示意图,显示依据图1A、图1B、图1C、图1D、图1E、图1F与图2的制造流程所设定的非易失存储器件的保持数据的情况。
主要元件符号说明
102、302 衬底
104、308 氧化层
106 氮化硅层
108、110、312氮原子或氮化硅原子
112 栅极氧化层
114 深洞陷阱
202、204、206、208、210、212、214、216、218、220、222、224、226 工艺步骤
300 元件
304 源极区域
306 漏极区域
310 栅极电极
314 空穴电荷
具体实施方式
以下实施例涉及利用公知CMOS制造流程,以及无须增加掩模的几道额外工艺步骤,制造非易失存储器与CMOS元件的方法。此处公开的某些实施例涉及嵌入应用,然而,应理解为此处所公开实施例不仅限于嵌入应用。
应理解为任何尺寸、量测、范围、测试结果、数据等,均以近似值为原则,除非另行指明,否则均不是精确数值。近似的方法种类将依据讨论的数据本质、内容、以及特定实施例或者执行方法而定。
图1A至图1F为剖面图,显示依据本发明的一种实施例,制造元件的工艺步骤范例示意图。如稍后会详加叙述,图1A至图1F所示的步骤可作为公知CMOS工艺的一部分步骤,而无须额外掩模。该工艺开始于图1A的衬底102。如下述,衬底102可为P型衬底或者N型衬底,依据制造元件的需求而定。此外,衬底102可包含N型阱或者P型阱,也是依据制造的特定元件需求而定。如图1B所示,氧化层104生长于衬底102之上。举例而言,氧化层104的厚度可介于约10埃(angstrom)至100埃之间。如图1C,氧化层104可作为衬底102与氮化硅层106间的缓冲层。举例而言,氧化层104可为二氧化硅(SiO2)层,其利用衬底102的热氧化而形成。
稍后,如图1C所示,氮化硅(SiN)层106可形成于氧化层104上。举例而言,SiN层106可利用化学气相沉积法(CVD)沉积于氧化层104上。
图1D中,随后可施以高热处理。举例而言,该热处理可包含在介于约800℃至1200℃的温度之间,进行诸如大约30分钟至2小时之间的热处理。此种高热处理将造成某些氮(N)或氮化硅(SiN)的原子108,移动穿越氧化层104而进入衬底102,如图1D所示。如图1E所示,此时可利用诸如湿蚀刻或干蚀刻等方法,移除氧化层104与SiN层106。这样,将可在衬底102上层的部分,保留许多的N或SiN原子110。
稍后,如图1F所示,栅极氧化层112可生长于衬底102上。举例而言,如同氧化层104,氧化层112可利用衬底102的热氧化生长于衬底102上。氧化层112的厚度范围,可介于约50埃至250埃间。
氧化层112可作为最终被制造的存储器件中的栅极氧化层。因此,图1F中所示的步骤,可实际包含部分公知CMOS制造程序,具体如下述。然而,在氧化层112形成期间,如图1F所示,衬底102中的N或SiN原子110(如图1E)可移动进入氧化层112。这些N或SiN原子110将在氧化层112中形成深洞陷阱114,具体如下述。
图2A为显示公知CMOS工艺的范例步骤的流程图。如稍后将理解的,公知CMOS工艺以硅衬底为开始,衬底必为N型或P型衬底。步骤202中,衬底中形成可供多个元件利用的活性区域。举例而言,因为嵌入应用具有高密度与微小尺寸的需求,所以通常使用浅沟槽隔离(STI)工艺以界定不同元件的活性区域。
步骤204可形成阱。如稍后将理解的,CMOS技术需要同时将N沟道(NMOS)与P沟道(PMOS)晶体管制造于同一晶片衬底上。为了同时安置NMOS与PMOS元件,必须在衬底上建立不同于衬底型态的另一型态特别区域。举例而言,P型阱可建立于N型衬底中,而N型阱可以建立于P型衬底中,其中PMOS晶体管建立于N型阱中,而该阱位于P型衬底上。在某些应用中,可在相同工艺中同时采用N型阱与P型阱。
N型阱和/或P型阱利用杂质值入至衬底上。由此,在步骤204中,N型阱和/或P型阱可利用公知光刻技术定义,随后可在衬底上的定义区域中值入而形成N型或P型阱。
稍后,在步骤216中,栅极氧化层可生长于衬底上。在公知CMOS工艺中,步骤206先洗净衬底,然后才能利用诸如热氧化衬底等方法,生长栅极氧化层。稍后在步骤218中,可以决定元件的沟道长度。沟道长度的定义通过在衬底上的栅极氧化层上沉积多晶硅层。随后利用公知光刻技术图案化多晶硅层,举例而言,多晶硅层可利用CVD法沉积。接着利用湿蚀刻或者干蚀刻等技术方法,蚀刻前述定义的多晶硅层与栅极氧化层,以在蚀刻的多晶硅层上形成栅极电极,而该多晶硅层通过栅极氧化层与衬底分隔,形成于蚀刻的栅极氧化层上。
如稍后将理解的,栅极多晶硅与栅极氧化层的蚀刻,将会使得部分衬底被裸露。裸露的衬底部分将会形成元件的源极与漏极结,由此决定元件的沟道长度。
然而,在形成源极与漏极之前,可先在栅极结构的两侧形成侧壁隔离;步骤220沉积侧壁隔离氧化物,可利用公知光刻技术界定侧壁隔离氧化物,随后蚀刻所定义的侧壁隔离氧化物。一旦侧壁隔离形成,即可形成源极与漏极区域;步骤222通过扩散或离子值入方法,将高浓度杂质掺杂至裸露的衬底表面(可为N型或P型杂质),并随后以诸如快速热处理(RTP)退火等方式进行退火处理。
随后可在步骤224中制造源极与漏极的连接点。举例而言,氧化层可形成于衬底上,再利用公知光刻技术图案化;此时可蚀刻该图案化的氧化物层,以提供源极和漏极结的接触窗口。接着可利用诸如自对准硅化物工艺等方法,在接触窗口中形成源极和漏极的连接点。最后,可图案化金属层并且将其蚀刻,以在步骤226中,在表面上完成元件互连。可以理解的是,步骤226可依据特定应用的需求,形成实际包含多个金属层所组成。
由此,图2A中的工艺可用以形成CMOS逻辑元件。然而,图2B的工艺,可在同一元件中同时形成CMOS与存储器两种元件。如步骤202、204、206与216-226所示,其内容与图2A所显示的CMOS工艺范例相同。然而,图2B中,包含额外步骤208-214。这些步骤对应图1A至图1E中所显示的步骤。由此,在步骤204形成阱后,可在步骤206清洗衬底表面,同时诸如氧化层104的氧化层,可于步骤208中形成于衬底上。例如SiN层206的氮化硅层,可于步骤210中沉积于氧化层上。步骤212中可施以高热处理,其可使N或SiN原子由SiN层移动至衬底中。步骤208与210中所形成的氧化物与SiN层可随后在步骤214中,经由蚀刻等方式移除。此时,衬底表面可完成清理,并在步骤216中生长栅极氧化层。如图1F所示,移动至衬底中的N或SiN原子,可在氧化生长步骤中移动至氧化层,即形成陷阱114处。
如图2B所示,由图1A至图1F中显示的额外步骤,并不需要就图2A中所示的CMOS工艺增加额外的掩模。由此,利用图2B中所增加的额外步骤,却无须额外掩模,即可用相同工艺来形成CMOS逻辑元件与存储器件;举例而言,利用图2B的工艺所制造的元件,可通过施加不同的操作偏压,来作为CMOS元件或者存储器件。稍后会有更详细的介绍。制造这种可以作为CMOS元件或者是存储器件的元件,可大幅降低复杂度、时间、与成本,在嵌入应用中尤其显著。
图3为依据图2的工艺所制造的元件300的示意图。如所示,元件300包含源极与漏极区域304与306,其形成于衬底302上。包含N或SiN原子312的氧化层308形成于衬底302上,其介于源极与漏极区域304及306间。栅极电极310形成于栅极氧化层308上。
N或SiN原子312可在存储器应用之中为整个氧化层308提供均匀的空穴陷阱;通常而言,此对存储器应用有益。此外,这些陷阱为深空穴陷阱,故一旦空穴进入陷阱,即无法在小电场时轻易跃迁,对于非易失存储应用而言属良好性质。换句话说,N或SiN原子312仅在高度垂直电场下为活性陷阱,即表示在通常CMOS工作下具有较小的干扰,其对于CMOS逻辑元件有利。因此,图2中所显示的工艺,可利用相同工艺,形成存储器件或CMOS逻辑元件,无须任何关于公知CMOS工艺的额外掩模。此外,工艺可轻易地与标准CMOS逻辑工艺结合。
由此,图3中的元件300可通过施加适当的CMOS工作偏压,依据公知CMOS工作原则,而作为CMOS逻辑元件工作。由于CMOS工作中所采用的电压并不会产生足够的电场,以活化栅极氧化层中的氮陷阱312,因此N或SiN原子312不会影响CMOS逻辑工作。但此外,通过施加适当偏压,元件300可作为存储器件工作,例如该偏压可活化N或SiN原子312。
图4与图5为示意图,显示元件300作为存储器件时,其编程与擦除的方法。作为存储器件时,N或SiN原子312作为氧化层308中的深空穴陷阱。通过建立巨大的负垂直电场,可造成空穴,并且可被捕获于陷阱312中,为建立此种巨大的负垂直电场,可如图4般施加巨大负电压至栅极电极310。如图4的范例,栅极电极310施以约为-20伏特的电压,而衬底302、源极304与漏极306可维持在0V。
如图4所示,施加于NMOS元件的电压,可在栅极310、衬底302、源极304与漏极306间造成巨大的负垂直电场。巨大的负电场,可利用以下两种机制之一,使空穴被氮陷阱312捕获。第一种机制为隧穿,其中空穴因为穿越栅极310与衬底302的巨大负电场,聚集在栅极310与衬底302的结附近。此时某些空穴即会自衬底302产生Fowler-Nordheim隧穿,进入氮陷阱312并被捕获。第二机制则为阳极热空穴注入。于此,高能量电子由栅极310隧穿进入衬底302可产生过剩空穴,其通过高能冲击离子化而产生。巨大的负电场可提供足够能量,使这些少数载流子隧穿进入氧化层308,并使其在此陷入氮陷阱312。由此,例如将空穴捕获于氮陷阱312中,元件300可通过Fowler-Nordheim隧穿与阳极热空穴注入被编程。如图4的下半所示,编程元件会捕获正电荷。
应理解者,图4所示相关电压仅作为范例,而实际电压将会依据特定应用的需求决定。举例而言,如前述栅极电极电压为-20V,实际电压的范围能为-15V至-30V。
如图5所示,进入陷阱的空穴电荷314,可通过在栅极310与衬底302间建立巨大正电场,脱离陷阱。巨大正电场可让进入陷阱的空穴314跃迁,回到衬底302。因此,如图5下半部所示,施加如图5上半部所示的巨大正电场,即可擦除元件300,因其可使陷入陷阱的空穴电荷314,跃迁回到衬底302,离开栅极介质层308的氮陷阱312。
如图5范例所示,栅极电极310受到大约为15V的巨大正电压,而衬底、源极与漏极扩散区域则维持在0V。然而,应理解为图5所示的相关电压,仅供作为范例,而实际电压则需依据特定应用的需求而决定。举例而言,如前述栅极电极的电压为15V,其实际电压可位在10V到20V的范围间。
图6A和图6B显示元件300作为存储器件时的读取操作。如图6A和图6B所示,读取电压可施加于栅极电极310,也可施加于漏极306。衬底302与源极304可维持在0V。读取操作的栅极偏压(Vg)与漏极偏压(Vd),也应进行设定,以在元件编程时,制造巨大的电流(例如临界电压(Vt)由于陷阱空穴的出现而较低),而在元件未编程时,制造较低的电流(例如陷阱空穴不存在而造成较高Vt)。同时,栅极偏压(Vg)不应干扰编程状态。由此,Vg应高于Vt,但低于应用于编程与擦除操作的栅极偏压。
如图6A所示,若元件300被擦除(例如空穴未被氮陷阱312捕获),施加读取电压将在漏极306与漏极304间产生小电流(Ids),其可指示被擦除的元件。如图6B所示,若空穴314陷入栅极介质层308,则施加读取电压将产生较大的Ids,其可指示编程的元件。由此,元件300可设定为储存一位,诸如0或1。举例而言,擦除状态可与0状态具有关连,而编程状态则可与1状态相关。
如图7至图9所示,当空穴314被介质层308捕获时,元件300的临界电压会改变。这种临界电压的改变,会使施加于元件300的读取电压造成不同的Ids。因此,举例而言,元件300在1状态时的临界电压约为0.5V,而在0状态时则约为3.0V。
应理解者,上述临界电压电平仅供参考,同时不应视为将元件限制于任何特定的临界电压阶层。
如图7至图9所示,经过一定数量的检测循环后,元件300仍然显示非常好的耐久度,同时也维持良好的编程状态。由于元件300可抵抗多次循环的应力,所以元件300除一次编程(OTP)应用外,也可用作多次编程(MTP)应用。元件300的I-V曲线范例如图8所示,显示不同编程-擦除数的测试结果。图9则显示存储器持久度检验的测试结果:四条曲线分别代表未处理单元、10次编程-循环擦除后,烘烤测试前、置于250℃,24小时烘烤测试后、与置于250℃,48小时烘烤测试后等状态下的I-V曲线。
由此,前述实施例公开一种工艺,可供CMOS逻辑与存储器件之用,其可大幅降低诸如嵌入应用的制造时间、成本、与复杂度。此外,依此制造的存储器件,具有良好的耐久度与数据维持能力,使其适于OTP与MTP应用。
前述内容公开本发明的几种实施例,应理解上述实施例仅作为范例。因此,本发明的范畴不应限于上述实施例所公开的内容,而本发明于此公开的范围,仅应受到权利要求的限制,同时应参考实施方式与附图的内容。
Claims (16)
1.一种制造逻辑和非易失存储器件的方法,包含:
形成氧化层于衬底上;
形成氮化层于所述衬底上;
施加热处理,其至少足以造成某些氮原子由所述氮化层移动至所述衬底中;
移除所述氮化层与所述氧化层;以及
生长栅极氧化层于所述衬底之上,其中生长所述栅极氧化层造成所述衬底中捕获的这些氮原子移动至所述栅极氧化层中。
2.如权利要求1所述的方法,其中所述热处理包含施加在800℃至1200℃之间的温度。
3.如权利要求2所述的方法,其中施加所述温度的时间在0.5小时至2小时之间。
4.如权利要求1所述的方法,其中形成所述氧化层包含利用热氧化所述衬底生长所述氧化层。
5.如权利要求3所述的方法,其中所述氧化层的厚度范围在10埃(angstrom)至100埃之间。
6.如权利要求1所述的方法,其中生长所述栅极氧化层包含利用热氧化所述衬底生长所述栅极氧化层。
7.如权利要求6所述的方法,其中所述栅极氧化层的厚度范围在50埃至250埃之间。
8.如权利要求1所述的方法,其中还包含形成活性区域于所述衬底中。
9.如权利要求8所述的方法,其中形成所述活性区域包含利用浅沟槽隔离工艺形成所述活性区域。
10.如权利要求1所述的方法,其中还包含形成多个阱区域于所述衬底中。
11.如权利要求1所述的方法,还包含定义所述逻辑或所述存储器件的沟道长度。
12.如权利要求1所述的方法,还包含为所述逻辑或所述存储器件在所述衬底中形成多个扩散区域。
13.如权利要求1所述的方法,还包含为所述逻辑或所述存储器件形成多个源极与漏极接触。
14.如权利要求1所述的方法,其中还包含形成金属内连接层。
15.一种元件,可作为逻辑元件或存储器件,包含:
形成于衬底上的栅极介质层,所述栅极介质层包含多个深空穴陷阱;
形成于所述栅极介质层上的栅极电极;以及
形成于所述衬底中的多个源极与漏极扩散区域;
其中所述深空穴陷阱为多个氮或氮化硅陷阱,其在形成所述栅极介质层时形成于所述栅极介质层中。
16.如权利要求15所述的元件,其中所述栅极介质层的厚度范围在50埃至250埃之间。
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US11/609,747 US7888272B2 (en) | 2006-12-12 | 2006-12-12 | Methods for manufacturing memory and logic devices using the same process without the need for additional masks |
US11/609,747 | 2006-12-12 |
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US6545314B2 (en) * | 1997-11-13 | 2003-04-08 | Micron Technology, Inc. | Memory using insulator traps |
CN1501458A (zh) * | 2002-10-29 | 2004-06-02 | ��������˹�����տ����� | 透过覆层对隧道结器件的隧道阻挡层进行的紫外光处理 |
CN1735972A (zh) * | 2002-12-06 | 2006-02-15 | 康乃尔研究基金会有限公司 | 使用背侧捕获的可缩放纳米晶体管和存储器 |
CN1853258A (zh) * | 2003-09-04 | 2006-10-25 | 先进微装置公司 | 具有电荷损失减少的氮化物层的存储单元结构及其制造方法 |
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US5596218A (en) * | 1993-10-18 | 1997-01-21 | Digital Equipment Corporation | Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation |
US5896315A (en) | 1997-04-11 | 1999-04-20 | Programmable Silicon Solutions | Nonvolatile memory |
US6800830B2 (en) * | 2000-08-18 | 2004-10-05 | Hitachi Kokusai Electric, Inc. | Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication |
US6678190B2 (en) | 2002-01-25 | 2004-01-13 | Ememory Technology Inc. | Single poly embedded eprom |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6545314B2 (en) * | 1997-11-13 | 2003-04-08 | Micron Technology, Inc. | Memory using insulator traps |
CN1501458A (zh) * | 2002-10-29 | 2004-06-02 | ��������˹�����տ����� | 透过覆层对隧道结器件的隧道阻挡层进行的紫外光处理 |
CN1735972A (zh) * | 2002-12-06 | 2006-02-15 | 康乃尔研究基金会有限公司 | 使用背侧捕获的可缩放纳米晶体管和存储器 |
CN1853258A (zh) * | 2003-09-04 | 2006-10-25 | 先进微装置公司 | 具有电荷损失减少的氮化物层的存储单元结构及其制造方法 |
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CN101226882A (zh) | 2008-07-23 |
TW200826235A (en) | 2008-06-16 |
US20080138998A1 (en) | 2008-06-12 |
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