CN101217124B - A low temperature flip chip welding method of macromolecule electric conducting material of template printing - Google Patents
A low temperature flip chip welding method of macromolecule electric conducting material of template printing Download PDFInfo
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- CN101217124B CN101217124B CN2008100563913A CN200810056391A CN101217124B CN 101217124 B CN101217124 B CN 101217124B CN 2008100563913 A CN2008100563913 A CN 2008100563913A CN 200810056391 A CN200810056391 A CN 200810056391A CN 101217124 B CN101217124 B CN 101217124B
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- 238000007639 printing Methods 0.000 title claims abstract description 61
- 239000004020 conductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 37
- 229920002521 macromolecule Polymers 0.000 title claims description 46
- 238000003466 welding Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000005516 engineering process Methods 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 11
- 238000012545 processing Methods 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000002245 particle Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 238000005323 electroforming Methods 0.000 claims description 4
- 238000006056 electrooxidation reaction Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 5
- 229920001940 conductive polymer Polymers 0.000 abstract description 4
- 229920000642 polymer Polymers 0.000 abstract 2
- 239000002861 polymer material Substances 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000005476 soldering Methods 0.000 description 11
- 239000011295 pitch Substances 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000010931 gold Substances 0.000 description 8
- 238000013461 design Methods 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 239000004411 aluminium Chemical group 0.000 description 4
- 229910052782 aluminium Chemical group 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
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- 239000000126 substance Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 241000500881 Lepisma Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910000756 V alloy Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
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- 230000007613 environmental effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 231100000614 poison Toxicity 0.000 description 1
- 230000007096 poisonous effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- Engineering & Computer Science (AREA)
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a low-temperature flip chip bonding method by using a template printing polymer conductive material, which pertains to the encapsulation technology, in particular to the flip chip technical field of an integrated circuit and a micro-electro-mechanical system (MEMS), the invention is characterized in that a template is used for printing the polymer conductive material on a chip and a pad of a substrate to form convex points, then the chip and the pad of the substrate are aligned and are arranged in a temperature keeping furnace with the temperature of less than 150 DEG C for curing, the chip and the substrate realize the conductive connection and form a whole body, finally the non-conductive polymer material is filled between the chip and the substrate to form a whole system. The invention has the advantages that the invention does not need to produce a metalizing layer under the convex points, the process temperature is low, the mechanical performances are good and the reliability is high, at the same time, the invention also reduces or eliminates equipment for post-treatment of washing residues.
Description
Technical field
The invention belongs to flip chip bonding field in integrated circuit and MEMS (micro electro mechanical system) (MEMS) device package, be particularly suitable for to carry out the device of high-temperature process.
Background technology
IC design, chip manufacturing and packaging and testing also are called three big industries of semi-conductor industry.Statistics shows that China will become one of the IC packaging base in the world.Therefore for Packaging Technique, the development of the semi-conductor industry of China is had great importance.The effect of encapsulation is given between tube core (chip) and the printed circuit board (PCB) (PCB) exactly electrical interconnection, mechanical support, machinery and environmental protection and heat dissipation channel is provided.Along with reducing of integrated circuit characteristic size, require packaging density more and more higher, thereby the reliability of encapsulation is proposed higher requirement.Simultaneously, along with the continuous reduction of integrated circuit (IC) chip cost, the ratio of cost in the components and parts cost that causes encapsulating constantly rises.Therefore, semiconductor industry is had higher requirement for the encapsulation technology of low cost and high reliability.
Traditionally, carry out the connection of chip with tiny gold, copper or aluminium bonding wire, this bonding wire is guided on the wire bond pads of plastics or ceramic packaging near the contact pad that is provided with the semiconductor chip surface periphery, realizes chip and extraneous being electrically connected.Because lead-in wire bonding cost is low, efficient is high, at present in industrial quarters still extensive use.Yet along with dwindling of integrated circuit characteristic size, the exit of chip is more and more, can only use the Wire Bonding Technology of peripheral pad to be challenged.Simultaneously, even on short relatively distance, thin bonding wire also will inevitably be introduced unwanted inductance and electric capacity in the interconnection, and reduces the bandwidth and the operation rate of electronic device thus.Along with the signal processing of microprocessor and higher frequency and the development of communicator faster, the defective of lead-in wire bonding becomes more and more obvious.
Face-down bonding technique is exactly in order to solve that chip is drawn problems such as terminal number is more and more, operating frequency is more and more higher and a kind of interconnection technique of growing up.With respect to traditional Wire Bonding Technology, face-down bonding technique uses welded ball array to realize between the chip or the interconnection between chip and the substrate.Face-down bonding technique density height, pitch is little and be the face array, increases greatly and draws terminal number, and have short interconnection vias (about 50 to 100 microns), can reduce interconnection inductance and electric capacity greatly, has in high-frequency device preferably and uses.
The technical process of flip chip bonding routine is such.At first, making metal layer under the salient point on the bonding pads.Secondly, in bonding pads or prepared and prepare salient point on the pad of metal layer under the salient point.At last, realize between the chip or the flip-chip interconnection between chip and the substrate.
Bonding pads is aluminium, copper or other metal material normally, is distributed in the surface of chip according to certain rules.Convex point material is generally various electric conducting materials, as gold, scolder etc.General convex point material can not directly be produced on the pad, thereby and in order to prevent that spreading, react the generation intermetallic compound between convex point material and the pad reduces the reliability that salient point is connected with pad metal, needs to make metal layer under one deck salient point.Metal layer has Cr-CuCr-Cu, TiW-Cu, Al-NiV-Au, TiW-Au, Ni (P)-Au etc. under the common salient point, and its corresponding manufacture method comprises that evaporation, sputter, chemical nickel plating add and soaks gold etc.
The salient point technology of preparing has been developed a variety of, as evaporation, SBB (Stud Bump Bonding) technology, plating, printing etc.Evaporation technology need adopt metal mask, the cost height, and complex process, application limitations is more.The SBB technology adopts existing lead-in wire bonding apparatus and technology to realize the salient point of single bonding region, and based on au bump, but production efficiency is relatively low.The salient point quality of electroplating technology preparation is better, can realize the salient point preparation of narrow pitch, but owing to need evaporation or sputtering technology to prepare metal layer under the salient point, and need thick resist lithography technology formation plating mask and electroplate figure, problems such as cost height, complex process caused.The mould printing technology prepares flipchip bump, owing to have processing compatibility preferably with existing surface mounting technology, so the production efficiency height, cost is lower.But because at present that is that all right is ripe to the research of numerous technological parameters in the mould printing process, cause the salient point of mould printing preparation to have various defectives, relatively poor as homogeneity, problems such as hole or bridge joint, reliability be relatively poor appear, make mould printing flip chip bonding particularly the application in the face-down bonding technique of narrow pitch be restricted.
Use comparatively extensively, study many mould printings that is to use soldering paste at present in industrial quarters.Soldering paste commonly used can be divided into again usually lead welding cream (as slicker solder eutectic soldering paste) and lead-free solder paste (as Sn4%Ag0.5%Cu, Sn3.5%Ag).Require the electronic device realization unleaded because European Union and other countries have put into effect relevant regulations, therefore use the mould printing technology to realize the preparation of unleaded salient point, obtain extensive studies and application.Authorizing to have narrated in people's such as Chen Zhenghao the Chinese patent 03142416.3 of " the little spacing flip-chip bump mould printing technology of preparing of lead/tin and lead-free solder " uses mould printing to prepare the technology of flipchip bump.This technology comprises the steps: to adopt nickel-vanadium alloy and lift-off technology to prepare ubm layer and backflow guide wire layer; According to size of solder ball and technological requirement, design preparation printing stencil; Use printing machine to print soldering paste on wafer; According to the solder paste material requirement, refluxing at a certain temperature forms soldered ball.Since soldering paste backflow balling-up, so the homogeneity of salient point is better, and reliability is higher, and can realize the salient point preparation of fine pith by optimizing technological parameter.To use chemical nickel plating and mould printing to prepare pitch be the unleaded salient point of 120 microns face arrays to the exercise question of the proceeding of the IMAPS 2004Long Beach that published in 2004 people such as Dionysios Manessis in order to have disclosed in " Accomplishments in Lead-FreeFlip Chip Wafer Bumping using Stencil Printing Technology " paper, it highly is distributed as 41.6 ± 2.8 microns, has reached homogeneity preferably.Simultaneously, the shearing force experiment shows that the shear strength of Sn4%Ag0.5%Cu salient point is 4.26g/mil
2, Sn3.5%Ag salient point shear strength is 3.07g/mil
2, reliability is better.But because the fusing point of lead-free solder paste is higher, be about 217～218 ℃, bring restriction for the application of lead-free solder paste as the SAC of Indium company series leadless soldering paste fusing point.
Summary of the invention
The objective of the invention is to adopt stencilization technology and macromolecule conducting material to realize the flip chip bonding of low temperature.
The invention is characterized in that described method contains following steps successively:
Step (1) is made the printing stencil of perforate;
The position of the position of perforate and pad on the chip and the pad on the substrate will be distinguished corresponding one by one,
The area of perforate compares greater than 0.6, described area ratio=S/S
Side, S is the area of perforate, S
SideBe the sidewall area of perforate,
The width of perforate is greater than 1.5 than W/t, and for square hole, W is the length of side of perforate, and for circular hole, W is the diameter of perforate, and t is the thickness of template,
The area of perforate is less than the area of pad;
Step (2) is cleaned described chip and the substrate that needs upside-down mounting, removes the organic pollution on described chip and substrate bonding pads surface;
Step (3) uses described template to print macromolecule conducting material on the pad of described chip surface, form salient point, the isotropism electric conducting material that described macromolecule conducting material is made up of thermoplasticity or heat cured mixed with resin conductive particle, conductive particle can be a silver powder particles;
Step (4) is put into holding furnace to the chip that is printed with described macromolecule conducting material and is solidified, and curing temperature is less than 150 ℃;
Step (5) is used described template to print described macromolecule conducting material on described substrate and is formed salient point;
Step (6) is printed with described macromolecule conducting material to the chip after solidifying through step (4) and step (5) but fits together after the still uncured substrate alignment;
Step (7) is solidified putting into described holding furnace through the chip after step (6) upside-down mounting and substrate, curing temperature＜150 ℃;
Step (8) uses nonconducting macromolecular material to remove to fill the flip-chip that has solidified by step (7) from the bottom;
Flip-chip after step (9) is filled the middle bottom of step (8) is put into described holding furnace and is solidified, and curing temperature forms last system less than 150 ℃.
The print speed printing speed of described masterplate is between the 7mm/s to 25mm/s when mould printing.
The bottom of described template and the chip face that is printed salient point when mould printing, perhaps the distance of the upper surface of substrate is zero.
The shape of described template is any among square, the circle.
The area of perforate is less than the area of pad on the described template.
With respect to the mould printing technology of using soldering paste, use the mould printing technology of macromolecule conducting material to have following advantage:
Need not make metal layer under the salient point.Macromolecule conducting material and most of pad metal such as aluminium, copper, gold etc. have wettability preferably, in conjunction with better, do not need to prepare metal layer under the salient point earlier as the printing soldering paste, thereby simplify technical process, reduce cost.
Curing temperature is low.For most macromolecule conducting material, high temperature can be reduced to the damage that semiconductor chip brings in curing temperature＜150 ℃, is specially adapted to the encapsulation of some semiconductor detectors.Because whole technological temperature is lower, the thermal stress of generation is less relatively, has improved the reliability of system.
Good mechanical property.Macromolecule conducting material is mixed and made into by thermoplasticity or thermosetting resin and conducting metal particles such as silver powder usually.Because resin material toughness is better, thermal stress resistance, mechanical stress are better, fatigue life height.
For the macromolecule conducting material of being made up of thermosetting resin, printing can not be flowed after solidifying, the last handling process better reliability, and the while also can reduce or cancel the wash residue equipment of reprocessing.
The unleaded poisonous metal that waits can the better protection environment.
Along with the template construct development of technology, use the mould printing technology of macromolecule conducting material can realize narrow pitch salient point array, satisfy chip and draw the increasing requirement of terminal number.
Description of drawings
Fig. 1 wants the upside-down mounting chip together and the profile of substrate among the embodiment.
Fig. 2 is the vertical view of printing stencil.
Profile when Fig. 3 is to use the template among Fig. 2 to print macromolecule conducting material on Fig. 1 chips.
Fig. 4 be take away after the template be printed with macromolecule conducting material and solidify after chip profile figure.
Fig. 5 is that the substrate among Fig. 1 has printed the profile behind the macromolecule conducting material.
Fig. 6 is that Fig. 4 and Fig. 5 aim at the schematic diagram that the back preparation fits together.
Fig. 7 be chip after aiming at and substrate fit together and solidify after profile.
Fig. 8 is that chip after solidifying and substrate use the profile after fill macromolecule non-conducting material bottom.
Wherein, the implication of each Digital ID representative is among the figure:
1: semiconductor chip, 2: the pad of semiconductor chip front surface
3: the passivation layer of semiconductor chip front surface, 4: substrate
5: the passivation layer on the substrate front surface, 6: the pad of making on the substrate front surface
7: macromolecule conducting material, 8: the macromolecule non-conducting material that uses is filled in the bottom
9: the template of printing usefulness, 10: the perforate on the template
Embodiment
The concrete process implementing step of this elite embodiment is:
1, manufacture and design printing stencil 9;
2, clean the chip 1 and the substrate 4 that need upside-down mounting, remove pad 2,6 surfaces and go up contaminations such as organic substance;
3, use template 9 on the pad 2 on chip 1 surface, to print macromolecule conducting material 7, form salient point;
4, the chip 1 that is printed with macromolecule conducting material is put into holding furnace solidify;
5, use template 9 on substrate 4, to print macromolecule conducting material 7, form salient point;
6, chip 1 after solidifying and substrate 4 upside-down mountings that are printed with macromolecule conducting material but do not have to solidify are in the same place;
7, the chip after the upside-down mounting 1 and substrate 4 are put into holding furnace solidify;
8, use nonconducting macromolecular material 8 bottoms to fill the flip-chip that has cured;
9, the flip-chip after fill the bottom is put into holding furnace and is solidified, and forms last system;
Perforate 10 shapes on the template 9 can adopt circle, ellipse or have rectangle of fillet etc.Common round hole, demolding performace is better; The salient point volume of rectangle printing that has fillet is big; Oval aperture then is suitable for the printing of the less salient point array of pitch.Suppose the perforate 10 wide W of being on the template 9, length is L, and area is S, and the perforate sidewall area is S
Side, template 9 is thick to be t, then can be defined as follows two parameter: flakiness ratio=W/t, area ratio=S/S
SideRequire flakiness ratio＞1.5 during stencil design, area is than＞0.6.The template processing method mainly contains three kinds: electrochemical corrosion, laser processing and electroforming processing.The electrochemical corrosion cost is minimum, generally uses copper coin as template, and perforate is second-rate, and is more suitable for the situation of pitch bigger (＞1 millimeter).Laser processing uses steel plate as template, and the perforate quality is better, is applicable to that pitch is greater than 150 microns face-down bonding technique.More when template perforate quantity, the laser processing cost is higher.When perforate pitch during less than 150 microns, the second-rate printing effect that causes of perforate sidewall is relatively poor, therefore needs to adopt electroforming processing mould plate technique.Electroforming processing template perforate sidewall is steep, best in quality.According to the requirement of printing salient point array, select suitable template process technology, template perforate parameter reasonable in design, thus obtain high-quality printing salient point array.
Macromolecule conducting material, normally the isotropism electric conducting material of forming by thermoplasticity or heat cured mixed with resin conductive particle.Conductive particle is silver powder particles normally, and mass fraction is up to 80%.
When the printing macromolecule conducting material, need to select rational printing parameter to obtain the salient point array that homogeneity is better, reliability is higher.Common printing parameter comprises print speed printing speed, squeegee pressure, from plate height, stripping rate etc.Print speed printing speed can not be too fast, otherwise cause the template perforate can't complete filling, and print speed printing speed is generally 7mm/s to 25mm/s.The pressure of printing scraper can not be too big, otherwise cause the wearing and tearing of scraper and template, and cause printing material to around flow and cause defective such as bridge joint; The pressure of printing scraper can not be too little, otherwise scraper is when scraping, and printing material remains on the template.The distance of the bottom of template and the upper surface of chip that is printed salient point or substrate when plate height is defined as printing.During the printing macromolecule conducting material, be generally 0 from plate height.Stripping rate influences the quality of conductive polymer salient point, and too fast stripping rate reduces conductive polymer salient point homogeneity.Print salient point preferably in order to obtain homogeneity, reduce stripping rate as far as possible.
Salient point need be assembled after chip and substrate are completed for printing, be about to chip with substrate upside-down mounting be in the same place.Owing to can not flow again after macromolecule conducting material solidifies,, need the mounting equipment of the special use adopted so need guarantee higher alignment precision during assembling.
Chip and substrate adopt after the macromolecule conducting material upside-down mounting, in order to strengthen the mechanical performance of upside-down mounting, adopt dielectric macromolecular material to carry out the bottom and fill.Because the present invention requires technological temperature not surpass 150 ℃, the macromolecular material curing temperature that therefore is used for filling the bottom can not be above 150 ℃.
The invention is characterized in and use macromolecule electric conducting material of template printing to realize the low temperature flip chip technology, rather than use the especially face-down bonding technique of lead-free solder paste of soldering paste.Use the especially face-down bonding technique of lead-free solder paste of soldering paste, the technical process maximum temperature is not less than 240 ℃, and the whole technical process temperature of the present invention is not higher than 150 ℃, is adapted to some for the relatively responsive semiconductor device of temperature, as special semiconductor detector etc.
In order to introduce the present invention better, illustrate in conjunction with a specific embodiment.It should be noted that this embodiment does not constitute the restriction to invention, its principle and feature can be used for various embodiment and do not depart from the scope and spirit of the present invention.
Claims (8)
1. use the low temperature flip chip method of macromolecule electric conducting material of template printing, it is characterized in that described method contains following steps successively:
Step (1), the printing stencil of making perforate:
The position of the position of perforate and pad on the chip and the pad on the substrate will be distinguished corresponding one by one,
The area of perforate compares greater than 0.6, described area ratio=S/S
Side, S is the area of perforate, S
SideBe the sidewall area of perforate,
The width of perforate is greater than 1.5 than W/t, and for square hole, W is the length of side of perforate, and for circular hole, W is the diameter of perforate, and t is the thickness of template,
The area of perforate is less than the area of pad;
Step (2) is cleaned described chip and the substrate that needs upside-down mounting, removes the organic pollution on described chip and substrate bonding pads surface;
Step (3), use described template on the pad of described chip surface, to print macromolecule conducting material, form salient point, the isotropism electric conducting material that described macromolecule conducting material is made up of thermoplasticity or heat cured mixed with resin conductive particle, conductive particle can be a silver powder particles;
Step (4) is put into holding furnace to the chip that is printed with described macromolecule conducting material and is solidified, and curing temperature is less than 150 ℃;
Step (5) is used described template to print described macromolecule conducting material on described substrate and is formed salient point;
Step (6), the chip after solidifying through step (4) is printed with described macromolecule conducting material with step (5) but after the still uncured substrate alignment mutually upside-down mounting be in the same place;
Step (7) is solidified putting into described holding furnace through the chip after step (6) upside-down mounting and substrate, curing temperature＜150 ℃;
Step (8) uses nonconducting macromolecular material to remove to fill the flip-chip that has solidified by step (7) from the bottom;
Step (9) is put into described holding furnace to the flip-chip after fill the bottom in the step (8) and is solidified, and curing temperature forms last system less than 150 ℃.
2. the low temperature flip chip method of use macromolecule electric conducting material of template printing according to claim 1 is characterized in that, the print speed printing speed of described template is between the 7mm/s to 25mm/s when mould printing.
3. the low temperature flip chip method of use macromolecule electric conducting material of template printing according to claim 1 is characterized in that, the bottom of described template and the chip face that is printed salient point when mould printing, and perhaps the distance of the upper surface of substrate is zero.
4. the low temperature flip chip method of use macromolecule electric conducting material of template printing according to claim 1 is characterized in that, the shape of described template is any among square, the circle.
5. the low temperature flip chip method of use macromolecule electric conducting material of template printing according to claim 1 is characterized in that, the pitch between described pad is made template with copper coin during greater than 1 millimeter, is processed to form by electrochemical corrosion.
6. the low temperature flip chip method of use macromolecule electric conducting material of template printing according to claim 1 is characterized in that, the pitch between described pad is made template with copper coin during greater than 150 microns, forms by laser processing technology.
7. the low temperature flip chip method of use macromolecule electric conducting material of template printing according to claim 1 is characterized in that, the pitch between described pad is during less than 150 microns, and described template adopts electroforming processing template method to form.
8. the low temperature flip chip method of use macromolecule electric conducting material of template printing according to claim 1 is characterized in that, is limited to 80% on the silver powder particles mass fraction in the described macromolecule conducting material.
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| CN102089251B (en) * | 2008-07-16 | 2014-06-11 | 费罗公司 | Hot-melt sealing glass compositions and methods of making and using the same |
| CN107371325A (en) * | 2017-07-13 | 2017-11-21 | 安捷利电子科技（苏州）有限公司 | A kind of method that sensor and printed circuit board are connected using conductive silver paste |
| CN107492534A (en) * | 2017-08-03 | 2017-12-19 | 中南大学 | Pitch list IC chip packaging part and preparation method thereof |
| US11165010B2 (en) | 2019-02-11 | 2021-11-02 | International Business Machines Corporation | Cold-welded flip chip interconnect structure |
| CN116944759A (en) * | 2023-09-20 | 2023-10-27 | 武汉高芯科技有限公司 | Flip-chip bonding processing method with low contact resistance and flip-chip interconnection structure |
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