CN101510515B - Circuit board, manufacturing method thereof and chip packaging structure - Google Patents
Circuit board, manufacturing method thereof and chip packaging structure Download PDFInfo
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- CN101510515B CN101510515B CN 200910128522 CN200910128522A CN101510515B CN 101510515 B CN101510515 B CN 101510515B CN 200910128522 CN200910128522 CN 200910128522 CN 200910128522 A CN200910128522 A CN 200910128522A CN 101510515 B CN101510515 B CN 101510515B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses a lines board and manufacturing method thereof and a chip enveloping structure. The manufacturing method of the lines board is following: providing a substrate, a leaning mat, a leaning welding layer and a bottom-protecting welding layer; the leaning welding layer and the bottom-protecting welding layer are respectively distributed on the top surface and the bottom surface of the substrate; the leaning welding layer and the bottom-protecting welding layer are electrically connected; the leaning welding layer and the bottom-protecting welding layer are respectively distributed on the top surface and the bottom surface; the leaning welding layer has a first opening exposing to the leaning mat; the bottom-protecting welding layer has a second opening exposing to the leaning mat. The bottom surface is formed with a conductive layer of the leaning mat with the leaning welding layer electrically connected to the leaning welding layer. The conductive layer is formed with a plating-resisted layer of a third opening; then the third opening is applied with the currency of the conductive layer leaning against the protruding block; the plating-resisted layer and the conductive layer are removed. According to the invention the distant of the size of the protruding block and the block can be effectively decreased.
Description
Technical field
The present invention relates to a kind of wiring board and preparation method thereof and chip-packaging structure thereof, and particularly relate to less wiring board of a kind of bump pitch and preparation method thereof and chip-packaging structure thereof.
Background technology
Along with the increase of the integrated level of integrated circuit, the encapsulation technology of chip is also more and more diversified.Because flip-chip bonded technology (Flip Chip Interconnect Technology) has advantages such as the Chip Packaging of dwindling volume and shortening signal transmission path, so be widely used in the Chip Packaging field at present.
Yet, in the technology of flip-chip bonded, be subject to chip when the melted by heating in order to the solder projection of joint chip and chip support plate and push and subside, to cause the decline of technology yield.Therefore, known technology proposes a kind of so-called control collapsed chip interconnection technique (Controlled Collapse Chip Connection C4) overcomes the problem that projection subsides.
A kind of control collapsed chip interconnection technique is on chip support plate, to form the solder projection that outstanding preparatory projection connects chip.The practice of above-mentioned preparatory projection is following.At first on chip support plate, form Seed Layer comprehensively; It covers welding resisting layer and by the connection pad that opening exposed of welding resisting layer; And on Seed Layer, form patterning photoresist layer, wherein a plurality of openings of patterning photoresist layer are communicated in welding resisting layer on the chip support plate respectively in order to expose a plurality of openings of connection pad.Then, in the opening of the opening of welding resisting layer and patterning photoresist layer, insert metal through Seed Layer and plating mode to form preparatory projection.
Because aforementioned preparatory projection can support the solder projection of fusion in the technology of flip-chip bonded, the problem of subsiding so can avoid the solder projection of fusion in the known technology to receive the extruding of chip.
Yet; In the technology of the preparatory projection of aforementioned making; Because the opening of patterning photoresist layer needs with the open communication of welding resisting layer and exposes the opening of welding resisting layer fully; So when forming the opening of patterning photoresist layer, can receive the restriction of contraposition precision on the technology, and make the A/F of patterning photoresist layer greater than the A/F of welding resisting layer.Thus, not only can't dwindle the size of the opening of patterning photoresist layer, also cause the size of preparatory projection and solder projection and bump pitch (bumppitch) to dwindle.In addition because bump pitch can't dwindle, so the chip connecting pad spacing on the chip also correspondence can't dwindle.
Summary of the invention
The present invention provides a kind of manufacture method of wiring board, can reduce the spacing of the preparatory projection on the wiring board.
The present invention provides a kind of wiring board, and its bump pitch is less.
The present invention provides a kind of chip-packaging structure, and the contactor density of its chip and wiring board is higher.
The manufacture method that the present invention proposes a kind of wiring board is described below.At first; Substrate, at least one apical grafting pad, connection pad of at least one end, prevention layer and end welding resisting layer are provided; Wherein apical grafting pad and end connection pad are disposed at respectively on the relative end face and bottom surface of substrate, and apical grafting pad and the electric connection of end connection pad, and top welding resisting layer and end welding resisting layer are disposed at respectively on end face and the bottom surface; The top welding resisting layer has first opening that exposes part apical grafting pad, and end welding resisting layer has second opening that exposes connection pad at the bottom of the part.Then, on the bottom surface, form conductive layer, conductive layer covers end welding resisting layer and end connection pad, and electrically connects with end connection pad.Then, on conductive layer, form resistance coating, resistance coating has the 3rd opening, and the 3rd opening exposes the partially conductive layer.Afterwards, see through the 3rd opening conductive layer is applied electric current, to electroplate preparatory projection on the apical grafting pad.Then, remove resistance coating.Then, remove conductive layer.
The present invention also proposes a kind of wiring board, and it comprises substrate, at least one apical grafting pad, top welding resisting layer, preparatory projection, connection pad of at least one end and end welding resisting layer.Substrate has relative end face and bottom surface.The apical grafting pad is disposed on the end face.The top welding resisting layer is disposed on the end face and cover part apical grafting pad, and the top welding resisting layer has first opening that exposes part apical grafting pad.Projection is disposed on the apical grafting pad and is arranged in first opening in advance, and projection has the protuberance that protrudes in the top welding resisting layer in advance, and the Breadth Maximum of protuberance is less than or equal to the width of apical grafting pad.End connection pad is disposed on the bottom surface, and is electrically connected to the apical grafting pad.End welding resisting layer be disposed on the bottom surface and the cover part at the bottom of connection pad, end welding resisting layer has second opening that exposes connection pad at the bottom of the part.
The present invention reintroduces a kind of chip-packaging structure, and it comprises wiring board, chip and at least one solder projection.Wiring board comprises substrate, at least one apical grafting pad, top welding resisting layer, preparatory projection, connection pad of at least one end and end welding resisting layer.Substrate has relative end face and bottom surface.The apical grafting pad is disposed on the end face.The top welding resisting layer is disposed on the end face and cover part apical grafting pad, and the top welding resisting layer has first opening that exposes part apical grafting pad.Projection is disposed on the apical grafting pad and is arranged in first opening in advance, and projection has the protuberance that protrudes in the top welding resisting layer in advance, and the Breadth Maximum of protuberance is less than or equal to the width of apical grafting pad.End connection pad is disposed on the bottom surface, and is electrically connected to the apical grafting pad.End welding resisting layer be disposed on the bottom surface and the cover part at the bottom of connection pad, end welding resisting layer has second opening that exposes connection pad at the bottom of the part.Chip configuration and disposes the corresponding chip connecting pad of projection in advance at least one position on the chip on wiring board.Solder projection is disposed between chip and the wiring board, to connect preparatory projection and chip connecting pad.
Based on above-mentioned, the present invention be utilize be positioned at substrate form preparatory projection as plating seed layer on the connection pad of the end face of substrate, to electroplate with respect to the conductive layer on the bottom surface of the end face that is provided with connection pad.Therefore; The present invention receives the restriction of contraposition precision on the technology in the time of can avoiding in the known technology on the end face of chip support plate, forming the opening of patterning photoresist layer, and can't dwindle the problem of size, size of lug and bump pitch of the opening of patterning photoresist layer.Thus, the present invention can effectively dwindle the size and the bump pitch of preparatory projection.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Figure 1A to Fig. 1 D illustrates the process section of the wiring board of the embodiment of the invention.
Fig. 2 illustrates the profile of the chip-packaging structure of the embodiment of the invention.
Description of reference numerals
100: wiring board 110: substrate
112: end face 114: bottom surface
116: core layer 116a: upper surface
116b: lower surface 118: core conductive channel
122: apical grafting pad 122a: top line layer
124: end connection pad 124a: end line layer
132: top welding resisting layer 132a: opening
134a: opening 134: end welding resisting layer
140: conductive layer 150: resistance coating
152: opening 160: preparatory projection
162: protuberance 162a: convex globoidal
172: surface-treated layer 174: surface-treated layer
210: chip 212: chip connecting pad
220: solder projection 230: bump bottom metal layer
240: soldered ball
C1: go up conductive channel C2: following conductive channel
D1: upper dielectric layer D2: following dielectric layer
W1, W2, W3: width θ: contact angle
Embodiment
Figure 1A to Fig. 1 D illustrates the process section of the wiring board of the embodiment of the invention.At first, please with reference to Figure 1A, substrate 110, a plurality of apical grafting pad 122, connection pad of a plurality of ends 124, top welding resisting layer 132 and end welding resisting layer 134 are provided.Apical grafting pad 122 is disposed at respectively on the relative end face 112 and bottom surface 114 of substrate 110 with end connection pad 124, and apical grafting pad 122 electrically connects with end connection pad 124.It should be noted that in Figure 1A, be convenient explanation, only illustrate apical grafting pad 122 and be example with end connection pad 124.In addition, using the term on " top " and " end ", only is convenient explanation, and its expression is positioned at relative two sides of substrate, and the substantial limitation on the non-space.
In detail, in the present embodiment, top line layer 122a and end line layer 124a are disposed at respectively on the end face 112 and bottom surface 114 of substrate 110, and top line layer 122a and end line layer 124a electric connection.The top line layer 122a of part constitutes apical grafting pad 122, and the end line layer 124a of part constitutes end connection pad 124.
Top welding resisting layer 132 is disposed at respectively on end face 112 and the bottom surface 114 with end welding resisting layer 134, but and top welding resisting layer 132 cover part top line layer 122a, but line layer 124a at the bottom of end welding resisting layer 134 cover parts.Top welding resisting layer 132 has opening 132a, and opening 132a exposes the apical grafting pad 122 of part.End welding resisting layer 134 has opening 134a, and it exposes connection pad 124 at the bottom of the part.
Then,, on bottom surface 114, for example form conductive layer 140 with electroless plating method (electroless plating) please with reference to Figure 1B, welding resisting layer 134 and end connection pad 124 at the bottom of conductive layer 140 coverings, and electrically connect with end connection pad 124.It should be noted that in the present embodiment conductive layer 140 can electrically connect with connection pad of a plurality of ends 124 simultaneously.
Then, please once more with reference to Figure 1B, on conductive layer 140, form resistance coating 150, resistance coating 150 has opening 152, and opening 152 exposes the conductive layer 140 of part.In the present embodiment, the method that forms resistance coating 150 for example is on conductive layer 140, to form photosensitive material layer (not illustrating) earlier comprehensively, then, and again with the mode patterning photosensitive material layer of exposure imaging.
Afterwards, please with reference to Fig. 1 C, see through 152 pairs of conductive layers 140 of opening and apply electric current, to electroplate preparatory projection 160 on apical grafting pad 122.In the present embodiment, projection 160 has the protuberance 162 that protrudes in top welding resisting layer 132 in advance.With respect to the width W 2 of opening 132a, the Breadth Maximum W1 of protuberance 162 can promptly be not less than the width W 2 of opening 132a more than or equal to the width W 2 of opening 132a.In addition, with respect to the width W 3 of apical grafting pad 122, the Breadth Maximum W1 of protuberance 162 can be less than or equal to the width W 3 of apical grafting pad 122, promptly is not more than the width W 3 of apical grafting pad 122.
It should be noted that mode that the present embodiment utilization applies electric current to the conductive layer 140 on the bottom surface 114 that is positioned at substrate 110 is electroplated forms preparatory projection 160.Therefore; The wiring board manufacture method of present embodiment receives the restriction of contraposition precision on the technology in the time of can avoiding in the known technology on the end face of chip support plate, forming the opening of patterning photoresist layer, and can't dwindle the problem of size, size of lug and bump pitch of the opening of patterning photoresist layer.More detailed explanation is; Pass through present embodiment; Owing to do not need headspace (mentioned like known technology, as to strengthen the A/F of patterning photoresist layer) to accomplish contraposition, therefore the Breadth Maximum W1 of the protuberance 162 of formed preparatory projection 160 will can be greater than the width W 3 of apical grafting pad 122.Review, if when using the technique of counterpoint of known technology to form preparatory projection, be subject to the required parameter setting of contraposition precision, the Breadth Maximum of formed preparatory projection will be greater than apical grafting pad width.Thus, the wiring board manufacture method of present embodiment can effectively be dwindled the size and the bump pitch of preparatory projection 160, but and with the less chip of the prepared wiring board carries chips of wiring board manufacture method connection pad spacing of present embodiment.
Then,, remove resistance coating 150, then, remove conductive layer 140 please with reference to Fig. 1 D.At this moment, begun to take shape the wiring board 100 of present embodiment.
Afterwards, please once more with reference to Fig. 1 D, in the present embodiment, can form surface-treated layer 172 on the projection 160 in advance, and form surface-treated layer 174 on the part outside the opening 134a being exposed to of end connection pad 124.In the present embodiment, the method for formation surface-treated layer 172,174 for example is chemical nickel and gold technology, chemical nickel palladium technology, chemical porpezite technology or chemical nickel porpezite technology.
Below will at length introduce with regard to the structure division of the wiring board among Fig. 1 D 100.
In detail, in the present embodiment, substrate 110 comprises core layer 116, core conductive channel 118, upper dielectric layer D1, last conductive channel C1, following dielectric layer D2 and following conductive channel C2.
Core layer 116 has relative upper surface 116a and lower surface 116b.Core conductive channel 118 runs through core layer 116.Upper dielectric layer D1 is disposed on the upper surface 116a.Last conductive channel C1 runs through upper dielectric layer D1, and electrically connects core conductive channel 118 and apical grafting pad 122.Following dielectric layer D2 is disposed on the lower surface 116b.Following conductive channel C2 runs through dielectric layer D2 down, and electrically connects core conductive channel 118 and end connection pad 124.Know that by aforementioned in the present embodiment, apical grafting pad 122 can see through last conductive channel C1, core conductive channel 118 is electrically connected to end connection pad 124 with following conductive channel C2.
In the present embodiment, wiring board 100 comprises the top line layer 122a that is disposed on the end face 112, and the top line layer 122a of part constitutes apical grafting pad 122.In addition, top line layer 122a does not have the plating line relevant with forming preparatory projection 160, therefore when signal transmits in wiring board 100, can reduce because of the additional configuration plating line to influence that signal quality caused.Top welding resisting layer 132 is disposed on the end face 112 and top, cover part line layer 122a, and top welding resisting layer 132 has the opening 132a that exposes part apical grafting pad 122.
In the present embodiment, protuberance 162 has convex globoidal 162a, and convex globoidal 162a is towards the direction protrusion away from apical grafting pad 122, and the contact angle θ of protuberance 162 and top welding resisting layer 132 is in fact less than 90 degree.Detailed explanation is; Through the formed preparatory projection 160 of present embodiment; Owing to do not need to form preparatory projection like the mentioned patterning photoresist layer that utilizes of known technology; Therefore its protuberance 162 can have convex globoidal 162a, makes that the protuberance 162 and the contact angle θ of top welding resisting layer 132 in fact can be less than 90 degree.Projection 160 can directly contact the inwall of apical grafting pad 122 and opening 132a in advance, and projection 160 for example is a conductive projection in advance, and its material for example is a metal.In an embodiment, projection 160 for example is a copper bump in advance.The material of projection 160 for example is the electric conducting material of fusing point greater than the fusing point that is disposed at the scolder (not illustrating) on the preparatory projection 160 in advance, that is projection 160 has different fusing points with scolder in advance.In the present embodiment; For avoiding protuberance 162 oxidations or receiving external environmental; Can be on protuberance 162 configuration surface processing layer 172; The material of surface-treated layer 172 comprise nickel, gold, palladium with and the alloy of combination or organic solderability preservative (Organic Solderability Preservative, OSP).
In the present embodiment, wiring board 100 comprises the end line layer 124a that is disposed on the bottom surface 114, and the end line layer 124a of part constitutes end connection pad 124.In addition, end line layer 124a does not have the plating line relevant with forming preparatory projection 160, therefore when signal transmits in wiring board 100, can reduce because of the additional configuration plating line to influence that signal quality caused.End welding resisting layer 134 be disposed on the bottom surface 114 and the cover part at the bottom of line layer 124a, end welding resisting layer 134 has the opening 134a that exposes connection pad 124 at the bottom of the part.In the present embodiment; For avoiding 124 oxidations of end connection pad or receiving external environmental; Can form surface-treated layer 174 being exposed on the part outside the opening 134a of end connection pad 124, the material of surface-treated layer 174 comprise nickel, gold, palladium with and the alloy or the organic solderability preservative (OSP) of combination.
Fig. 2 illustrates the profile of the chip-packaging structure of the embodiment of the invention.
Please with reference to Fig. 2, chip-packaging structure comprises wiring board 100, chip 210 and a plurality of solder projection 220, it should be noted that in Fig. 2, is convenient explanation, only illustrates solder projection 220 and is example.The structure of wiring board 100 is identical with the structure of the wiring board 100 of Fig. 1 D, so repeat no more in this.Chip 210 is disposed on the wiring board 100, and disposes the corresponding chip connecting pad 212 of projection 160 in advance in a plurality of positions on the chip 210.
In sum, the present invention be utilize be positioned at substrate with respect to the conductive layer on the bottom surface of the end face that is provided with connection pad as plating seed layer, form preparatory projection on the connection pad of the end face of substrate, to electroplate.Therefore; The present invention receives the restriction of contraposition precision on the technology in the time of can avoiding in the known technology on the end face of chip support plate, forming the opening of patterning photoresist layer, and can't dwindle the problem of size, size of lug and bump pitch of the opening of patterning photoresist layer.Thus, the present invention can effectively dwindle the size and the bump pitch of preparatory projection.
Though the present invention discloses as above with embodiment; Right its is not in order to limit the present invention; Those of ordinary skill in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.
Claims (14)
1. the manufacture method of a wiring board comprises:
Substrate, at least one apical grafting pad, connection pad of at least one end, top welding resisting layer and end welding resisting layer are provided; Wherein this apical grafting pad and this end connection pad are disposed at respectively on the relative end face and bottom surface of this substrate; And this apical grafting pad and this end connection pad electrically connect; This top welding resisting layer and this end welding resisting layer are disposed at respectively on this end face and this bottom surface, and this top welding resisting layer has first opening that exposes this apical grafting pad of part, and this end welding resisting layer has and exposes second opening that part should end connection pad;
On this bottom surface, form conductive layer, this conductive layer covers should end welding resisting layer and this end connection pad, and with this end connection pad electric connection;
On this conductive layer, form resistance coating, this resistance coating has the 3rd opening, and the 3rd opening exposes this conductive layer of part;
Through the 3rd opening this conductive layer is applied electric current, to electroplate preparatory projection on this apical grafting pad;
Remove this resistance coating; And
Remove this conductive layer.
2. the manufacture method of wiring board as claimed in claim 1, wherein this preparatory projection has the protuberance that protrudes in this top welding resisting layer, and the Breadth Maximum of this protuberance is more than or equal to the width of this first opening.
3. the manufacture method of wiring board as claimed in claim 1, wherein this preparatory projection has the protuberance that protrudes in this top welding resisting layer, and the Breadth Maximum of this protuberance is less than or equal to the width of this apical grafting pad.
4. the manufacture method of wiring board as claimed in claim 1, the method that wherein forms this conductive layer comprises electroless plating method.
5. wiring board comprises:
Substrate has relative end face and bottom surface;
At least one apical grafting pad is disposed on this end face;
The top welding resisting layer is disposed on this end face and this apical grafting pad of cover part, and this top welding resisting layer has first opening that exposes this apical grafting pad of part;
Preparatory projection; Be disposed on this apical grafting pad and be arranged in this first opening; This preparatory projection is used for being connected with configuration solder projection above that, and this preparatory projection has the protuberance that protrudes in this top welding resisting layer, and the Breadth Maximum of this protuberance is less than or equal to the width of this apical grafting pad;
Connection pad of at least one end is disposed on this bottom surface, and is electrically connected to this apical grafting pad;
End welding resisting layer is disposed on this bottom surface and the cover part should end connection pad, and this end welding resisting layer has and exposes second opening that part should end connection pad, and
Conductive layer, covering should electrically connect with this end connection pad and with this end connection pad by end welding resisting layer, to form the plating seed layer of this preparatory projection as plating.
6. wiring board as claimed in claim 5, wherein this preparatory projection fills up this first opening, and the Breadth Maximum of this protuberance is more than or equal to the width of this first opening.
7. wiring board as claimed in claim 5, wherein this protuberance has convex globoidal.
8. wiring board as claimed in claim 7, wherein the contact angle of protuberance and this top welding resisting layer is less than 90 degree.
9. wiring board as claimed in claim 5, wherein this wiring board also comprises the top line layer that is disposed on this end face, and this top this apical grafting pad of line layer formation of part, this top line layer does not have and the relevant plating line of this preparatory projection of formation.
10. wiring board as claimed in claim 5, wherein this wiring board also comprises the end line layer that is disposed on this bottom surface, and part should the end line layer constitute should end connection pad, this end line layer does not have and the relevant plating line of this preparatory projection of formation.
11. wiring board as claimed in claim 5, wherein this preparatory projection is a copper bump.
12. a chip-packaging structure comprises:
Wiring board comprises:
Substrate has relative end face and bottom surface;
At least one apical grafting pad is disposed on this end face;
The top welding resisting layer is disposed on this end face and this apical grafting pad of cover part, and this top welding resisting layer has first opening that exposes this apical grafting pad of part;
Preparatory projection; Be disposed on this apical grafting pad and be arranged in this first opening; This preparatory projection is used for being connected with configuration solder projection above that, and this preparatory projection has the protuberance that protrudes in this top welding resisting layer, and the Breadth Maximum of this protuberance is less than or equal to the width of this apical grafting pad;
Connection pad of at least one end is disposed on this bottom surface, and is electrically connected to this apical grafting pad;
End welding resisting layer is disposed on this bottom surface and the cover part should end connection pad, and this end welding resisting layer has and exposes second opening that part should end connection pad; And
Conductive layer, covering should electrically connect with this end connection pad and with this end connection pad by end welding resisting layer, with plating seed layer as this preparatory projection of plating formation,
Chip is disposed on this wiring board, and disposes the position on this chip at least one chip connecting pad of projection in advance; And
At least one solder projection is disposed between this chip and this wiring board, and to connect this preparatory projection and this chip connecting pad, wherein said preparatory projection is used for being connected with configuration this at least one solder projection above that.
13. chip-packaging structure as claimed in claim 12, wherein this preparatory projection fills up this first opening, and the Breadth Maximum of this protuberance is more than or equal to the width of this first opening.
14. chip-packaging structure as claimed in claim 12, wherein the fusing point of this preparatory projection is different from the fusing point of this solder projection.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14084608P | 2008-12-24 | 2008-12-24 | |
| US61/140,846 | 2008-12-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101510515A CN101510515A (en) | 2009-08-19 |
| CN101510515B true CN101510515B (en) | 2012-09-05 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910128522 Active CN101510515B (en) | 2008-12-24 | 2009-03-16 | Circuit board, manufacturing method thereof and chip packaging structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101510515B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI416682B (en) | 2010-09-01 | 2013-11-21 | Unimicron Technology Corp | Package structure |
| KR102152865B1 (en) * | 2014-02-06 | 2020-09-07 | 엘지이노텍 주식회사 | Printed circuits board, package substrate and a manufacturing method thereof |
| TWI587463B (en) * | 2014-11-12 | 2017-06-11 | 矽品精密工業股份有限公司 | Semiconductor package structure and fabrication method thereof |
| TWI559469B (en) * | 2015-08-05 | 2016-11-21 | 力成科技股份有限公司 | Multi-chips package and manufacturing method thereof |
| US10290584B2 (en) | 2017-05-31 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive vias in semiconductor packages and methods of forming same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1407847A (en) * | 2001-06-27 | 2003-04-02 | 日本特殊陶业株式会社 | Wiring substrate manufacture |
| CN1620230A (en) * | 2003-11-18 | 2005-05-25 | 日本特殊陶业株式会社 | Process for manufacturing a wiring substrate |
| CN101252092A (en) * | 2008-03-12 | 2008-08-27 | 日月光半导体制造股份有限公司 | Multi-chip packaging structure and making method thereof |
-
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- 2009-03-16 CN CN 200910128522 patent/CN101510515B/en active Active
- 2009-04-03 TW TW98111229A patent/TWI375501B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1407847A (en) * | 2001-06-27 | 2003-04-02 | 日本特殊陶业株式会社 | Wiring substrate manufacture |
| CN1620230A (en) * | 2003-11-18 | 2005-05-25 | 日本特殊陶业株式会社 | Process for manufacturing a wiring substrate |
| CN101252092A (en) * | 2008-03-12 | 2008-08-27 | 日月光半导体制造股份有限公司 | Multi-chip packaging structure and making method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI375501B (en) | 2012-10-21 |
| CN101510515A (en) | 2009-08-19 |
| TW201026189A (en) | 2010-07-01 |
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