CN101208801B - 半导体器件及这种器件的制造方法 - Google Patents

半导体器件及这种器件的制造方法 Download PDF

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CN101208801B
CN101208801B CN2006800229673A CN200680022967A CN101208801B CN 101208801 B CN101208801 B CN 101208801B CN 2006800229673 A CN2006800229673 A CN 2006800229673A CN 200680022967 A CN200680022967 A CN 200680022967A CN 101208801 B CN101208801 B CN 101208801B
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韦伯·D·范诺尔特
简·雄斯基
菲利浦·默尼耶-贝拉德
埃尔温·海曾
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Koninklijke Philips NV
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Abstract

本发明涉及一种半导体器件(10)，具有衬底(11)和硅半导体本体(12)，包括具有晶体管(T)的有源区(A)和围绕有源区(A)的无源区(P)，并且配置有与从半导体本体(12)的表面下陷的金属材料导电区(2)相连的金属材料掩埋导电区(1)，据此所述掩埋导电区(1)至少是在半导体本体(12)的有源区的位置处是可电连接的。根据本发明，掩埋导电区(1)是在半导体本体(12)的有源区(A)的位置处的。按照这种方式，使用具有与周围的硅完全不同的结晶性质的金属材料，可以在半导体本体(12)的有源区(A)处局部地产生非常低的掩埋阻抗。通过使用根据本发明的方法是可行的。这种掩埋的低阻抗对于双极型晶体管和MOS晶体管两者提供实质上的优势。

Description

半导体器件及这种器件的制造方法
技术领域
本发明涉及一种具有衬底和硅半导体本体的半导体器件，所述半导体本体包括具有晶体管的有源区和围绕所述有源区的无源区，并且配置有与从半导体本体的表面下陷的金属材料的导电区相连的金属材料的掩埋导电区。如这里所使用的术语金属材料应该理解为意思是具有与技术电阻可比较的特定阻抗的金属，例如，诸如铜、铝、钨、钛、氮化钛等之类的金属、合金、或化合物。本发明还涉及一种制造这种器件的方法。
背景技术
这种器件和方法根据US专利US/2005/0023617是已知的。所述文献介绍了一种具有MOS晶体管的半导体器件，所述MOS晶体管形成了存储器的一部分并且形成于半导体本体的有源区中。有源区由在半导体本体中形成的腔体形式的无源区包围，所述腔体用电绝缘材料填充。在电绝缘材料中掩埋的是金属材料的导电区，所述导电区与基准电压以及存储器IC的至少一个相邻元件相连。通过在用绝缘体覆盖的凹槽底部中形成SiGe区、并且用另外的绝缘体对所述SiGe区进行掩埋来创建导电区。在已经将下陷的凹槽形成至SiGe区之后，通过刻蚀去除SiGe，其后用金属材料填充这样形成的腔体。
已知的晶体管的缺点是在MOS晶体管的情况下，晶体管表现出许多不利的现象，其中包括串扰。
发明内容
因此，本发明的目的是提出一种具有晶体管的半导体器件，所述晶体管不会表现出上述问题，并且在所述晶体管中不会出现串扰现象、或者串扰现象程度较轻。
为了实现该目的，在导言中所述类型的半导体器件的特征在于：在半导体本体的有源区的位置处形成掩埋导电区。本发明首先是基于这样的理解：通过在MOS晶体管的沟道区下面掩埋高导电区、实现了关于许多性质的改进，其中包括器件对于相邻晶体管之间的串扰的减小的敏感性。另外，防止了来自位于掩埋区下面的那部分半导体本体的电荷载流子的注入，结果所述器件在高温时表现出改进的性质，并且所述器件对辐射更不敏感。除此之外，本发明是基于这样的理解：可以在半导体本体的有源区内形成这种金属掩埋导电区，同时避免了针对晶体管的不利结果。通过在待形成掩埋导电区的位置处形成SiGe区，可以通过选择性刻蚀来去除该区域，适当地选择提供锗的含量，并且以及随后用金属材料填充。厚度和SiGe区域的锗含量的合适选择通过外延实现了在所述区域上形成硅半导体本体的单晶部分，而没有其中形成晶体管的该区域，表现出可能对于晶体管性质具有不利影响的缺陷。在形成晶体管之后，当刻蚀掉SiGe区并且随后用金属导电材料代替时，保持这种情况，同时这是本发明的本质方面：所述金属导电区不是单晶的、或者总之可以具有与硅不同的晶体结构和/或完全不同的晶格常数。
另一方面，待选择的锗含量依赖于对于硅是足够选择性的刻蚀剂的实用性。这样，可以将表现出足够大的选择性的湿法刻蚀剂(例如HNO3∶H2O∶HF或预氧化的HF混合物)和干法刻蚀技术(例如利用含氧和氟气体的等离子体)用于约30at％的锗含量。另一方面，锗含量的产物和SiGe区的厚度必须保持在特定值以下，因为否则如果通过外延在上面形成硅区域，位错将由在具有与硅的网格常数不同的网格常数的这种区域中建立的张力产生，所述位错对于所形成的硅区域的质量具有不利影响。对于约30at.％的锗含量，SiGe区的厚度必须小于或等于约20nm。如果选择性刻蚀剂是可用的，所述选择性刻蚀剂也可以用于更低的锗含量，SiGe区的厚度必须按比例地变大。
在优选实施例中，用与形成晶体管的连接导体的材料相同的材料填充掩埋导电区和下陷的导电区。这样的优势是可以在器件制造的后期阶段时形成所述掩埋导电区和下陷导电区。在这种后期阶段时，在该阶段存在的绝缘层，即所谓的预金属电介质给出足够的强度和附着力，以便可以毫无问题地形成下陷凹槽和掩埋区的腔体。同时通过在那种情况下填充掩埋区和下陷凹槽来形成晶体管的连接导体。
在有利的变体中，掩埋导电区与半导体区的表面间隔开比无源区的厚度小的距离。掩埋导电区的效应在这种情况下是最优的。优选地，在这种情况下，其中形成下陷导电区的那部分半导体本体位于无源区和有源区之间。
在另一个变体中，在位于无源区外部的那部分半导体本体中形成掩埋导电区。在这种情况下，SiGe区必须在无源区下面延伸进入半导体本体的上述部分中。为了在这种情况下减小从掩埋导电区至半导体本体的表面之间的距离，可以设置额外的SiGe区，所述区域在上述SiGe区域上方形成，通过硅区域与上述SiGe区分离。在去除(一部分)SiGe区之后，可以通过选择性刻蚀去除与所述额外的SiGe区重叠的那部分半导体本体的硅部分，所述额外的SiGe区与所述表面间隔开比无源区的厚度小的距离，所述额外的SiGe区向无源区本身那样作为刻蚀停止层。该变体的另一个优势是掩埋导电区可以具有比SiGe区大的厚度。另外，因为可用的腔体较大，所述区域将易于形成。
优选地，无源区包括所谓的沟槽隔离区。如果晶体管是MOS晶体管，掩埋导电区将位于如前所述的晶体管的沟道区中。
另外，有利地，根据本发明的器件可以包括双极型晶体管。有利地，在这种情况下掩埋导体区将形成晶体管的集电极的一部分。结果，所述晶体管将具有非常低的集电极串联电阻，并且可以毫无困难地大大减小晶体管的尺寸，同时获得了优秀的高频性质。最终，集电极层的尺寸减小至小于100nm的厚度将导致增加的基极集电极电容。由于金属区非常低的串联电阻，使得可以实现非常高的操作频率。
制造具有衬底和硅半导体本体的半导体器件的方法是根据本发明的，所述硅半导体本体包括具有晶体管的有源区和围绕所述有源区的无源区，并且配置有与从半导体本体的表面下陷的金属材料的导电区相连的金属材料的掩埋导电区，其中掩埋导电区是通过SiGe区形成的，所述方法的特征在于以下步骤：
在半导体本体的有源区内通过在其硅部分上形成单晶SiGe区来形成半导体本体；
通过半导体本体上的外延形成半导体本体的额外硅部分；
形成从表面至SiGe区的开口下陷区；
通过SiGe区的选择性刻蚀在SiGe区的位置处形成腔体；以及
用金属材料填充所述腔体，从而在所述位置处形成掩埋导电区。
使用这种方法，可以毫无困难地获得根据本发明的器件。
在优选实施例中，用金属材料填充开口下陷区，从而形成下陷的导电区。优选地，将相同的金属材料用于形成掩埋导电区。优选地，通过形成沟槽隔离区来形成无源区。在一个变体中，将下陷的导电区形成于无源区的外部。
在有利的实施例中，在已经形成晶体管之后并且在已经将绝缘层沉积到半导体本体上之后形成开口下陷区，在已经用掩模覆盖了触点开口之后，所述绝缘层配置有用于晶体管的触点开口以及在待形成的开口下陷区的位置处的额外开口。
在另一个变体中，将额外的SiGe区形成于半导体本体的所述额外的硅部分上，在所述额外区上形成了半导体本体的另一个硅部分，其中SiGe区和所述额外的SiGe区分别与半导体本体的表面间隔开比无源区的厚度更大或更小的距离。在该变体中，优选地，在形成所述腔体之后，通过刻蚀掉相邻硅之后将所述腔体扩大至所述额外的SiGe区。
附图说明
现在将参考实施例和附图更详细地解释本发明，其中：
图1至7是与根据本发明的器件的第一示例的厚度方向垂直的示意性截面图，示出了通过根据本发明的方法制造的连续阶段；
图8和9是与根据第一示例的器件的两个变体的厚度方向垂直的示意性截面图：
图10和I1是与根据本发明的器件的第二示例的厚度方向垂直的示意性截面图，示出了通过根据本发明的方法制造的相关阶段；
图12是与根据本发明第二示例的变体的厚度方向垂直的示意性截面图；
图13至15是与根据本发明的器件的第三示例的厚度方向垂直的示意性截面图，示出了通过根据本发明的方法制造的相关阶段；以及
图16是与根据本发明的器件的厚度方向垂直的示意性截面图。
具体实施方式
没有按比例绘制附图，并且为了清楚起见放大了一些尺寸。尽可能地将相似的区域或部分用相同的数字表示。
图1至7是与根据本发明的器件的第一示例的厚度方向垂直的示意性截面图，示出了通过根据本发明的方法制造的连续阶段。该示例的实质完整的器件10(参见图7)包括硅半导体本体12，包括具有在其上设置的半导体层结构的p型硅衬底11和双极型晶体管T。该该示例中是分立晶体管的晶体管T是微分型或外延型晶体管，即基极区31包括在半导体本体上生长的分层区域，所述半导体本体是无源区P上的多晶以及包括晶体管的集电极区33的有源区A内的单晶。在所述区域上存在的是射极区32，在该示例中是T型的。位于电绝缘层13内的连接导体7、8提供射极区32和基极区31的电连接。考虑到在该示例的晶体管的高频本性，基极区31包含具有20at％的锗含量的硅和锗的混合晶体。在晶体管上面和绝缘层13下面存在的是另外的电绝缘层14。
位于有源区A中的是掩埋导电区1，在该示例中包括金属导体并且形成晶体管T的集电极区33。掩埋导电区1经由从表面下陷的导电区2在表面处与用于集电极区33的连接导体9相连，所述表面填充有金属导电材料。在该示例中，区域1、2两者和连接导体7、8、9由相同的材料形成，在该示例中所述材料包括钨。如图7所示，所述器件10还包括已经用于形成掩埋导电区1的一部分SiGe区1A。已经在位于无源区P外部并且因此与另外的无源区P1相邻的半导体本体12的部分D中形成下陷的导电区2。
针对器件10的尺寸、形成其部分的(半导体)区域的掺杂浓度和尺寸已经选择了传统的值。例如，该实施例的器件10通过根据本发明的方法如下制造。
起点(参见图1)是p型硅衬底11，所述硅衬底11形成半导体本体12的一部分，并且在其上通过外延沉积了具有20nm厚和30at％的锗含量的SiGe层1A。在所述层上沉积了半导体本体12的额外硅部分12A。所述部分12A是n导电型的，所述部分12A形成至少在有源区A内的晶体管T的集电极区33的低掺杂部分。在表面上形成处于所谓的沟槽隔离区的无源区P、P1。在半导体本体12的有源区A中或内部形成双极型晶体管T，在这种情况下是所谓的微分或外延型的晶体管。用于该目的的接触步骤是传统的步骤，并且这里不会分立地进行描述。
随后，在如上所述的结构(参见图2)上形成电绝缘层13、14。在所述层13、14(参见图3)中，通过光刻和刻蚀形成触点开口C和额外的开口V，在这种情况下也是晶体管T的触点开口。
然后，(参见图4)用光致抗蚀剂掩模M覆盖触点开口C。额外的开口V保持可接近的，并且通过刻蚀，在这种情况下是通过干法刻蚀工艺刻蚀至SiGe层1A，经由所述开口V(参见图5)在无源区P和额外的无源区P1之间的半导体本体12中形成下陷的开口区2A。
然后，通过使用利用原子氟的选择性干法刻蚀的刻蚀在SiGe层1A中形成腔体1B，所述腔体1B延伸进入半导体本体12的有源区A中。
接下来(参见图7)，去除掩模M，并且用金属材料填充额外的开口V、掩埋开口区1B和下陷的开口区2A，通过CVD(化学气相沉积)技术来涂敷所述金属材料。同时，形成连接导体7、8、9和掩埋导电区1以及下陷的导电区2。如图中所示，可以完全地填充后一区域2，或者后一区域2仍然包括腔体。当然，惟一的实质的事实是下陷的导电区2形成了在该示例中形成双极型npn(该示例中)晶体管T的掩埋导电区1和所讨论的连接导体9之间的理想导电连接。
随后在形成一个或更多金属化层(互连)、接着在钝化之后通过诸如锯切之类的分离工艺获得了针对最终组件准备的单独的器件10。
图8和9是与第一示例的器件10的两个变体的厚度方向垂直的示意性截面图。
在第一变体中(参见图8)，掩埋导电区1位于掩埋高掺杂半导体区15中。在这种情况下是n+硅的这种区域在双极型晶体管中本质上是已知的并且是常用的，并且在这种情况下也是按照通常的方式形成的，例如在外延工艺之前或之后通过局部注入，通过所述外延工艺已经形成了SiGe层1A和半导体本体12的重叠部分12A。
在第二变体中(参见图9)，其与第一变体相同，另外无源区P3存在于无源区P下面，作为其结果形成了所谓的深沟绝缘。
图10和11是与根据本发明的器件的第二示例的厚度方向垂直的示意性截面图，示出了通过根据本发明的方法制造的相关阶段。器件10及其制造与第一示例的那些大部分相同，并且因此这里将只讨论差别。
第一差别(参见图10)涉及在形成无源区P、P1之前，在半导体本体12的硅部分12A的顶部上的额外的SiG。区的形成以及在半导体本体12的所述额外的SiGE区1C上的另一个硅区12B的形成。这只能在形成区域1A、12A之后马上、并且在相同的外延工艺中形成。现在，所述额外的SiGe区1C与表面间隔开比无源区P的厚度小的距离，然而同时，SiGe区/层1A如第一示例那样仍然在无源区P下面。
第二差别(参见图11)可以在SiGe层1A的一部分的位置处形成开口下陷区2A和腔体1B时来区分。当形成下陷的开口区2A时，去除了在那个位置存在的那部分额外的SiGe区1C，这可以通过选择性刻蚀工艺/刻蚀剂来实现。在两个步骤中形成掩埋导电区1的位置处的腔体1B。在第一步骤中，通过选择性刻蚀工艺去除(一部分)SiGe区1A。在第二步骤中，发生半导体本体12的硅的选择性刻蚀。结果，沿所有方向扩大了腔体1B，其中额外的SiGe区1C用作半导体本体12的有源区A中的刻蚀停止层。如果需要，然后可以通过选择性刻蚀步骤去除所述额外的SiGe区。该示例的重要优势在于掩埋导电区和下陷的导电区的尺寸相对较大，这促进了腔体的形成，并且导致减小的电阻。除此之外，有利的是有可以将无源区P内部的掩埋导电区1定位于与半导体本体12的表面相距非常小的距离。在双极型晶体管T的情况下，同样因为按照这种方式集电极区33的尺寸的非常强烈的向下缩放是可能的，这对于高操作频率有显著的贡献。
图12是与根据本发明第二示例的变体的厚度方向垂直的示意性截面图。在该示例中，半导体本体12的一部分D位于其有源区A和无源区P之间。因此，已经在由无源区P限制的那部分半导体本体12内部形成了下陷的导电区，并且在该变体中半导体12的表面也可以(显著地)比无源区P的厚度小。该变体还包括围绕下陷的导电区2的可选择的下陷高掺杂半导体区16。
图13至15是与根据本发明的器件的第三示例的厚度方向垂直的示意性截面图，示出了通过根据本发明的方法制造的相关阶段。与在前示例的第一重要的差别(参见图15)是：现在晶体管T包括MOS晶体管，所述MOS晶体管已经在p型衬底11中的n阱20中形成。如同上述的第二示例的变体那样，现在掩埋导电区1与表面间隔开较短的距离，并且将下陷的导电区2定位于有源区A和无源区P之间的半导体本体12的部分D中，下陷的导电区2以及因此掩埋导电区1经由高掺杂半导体区21与衬底1导电接触，所述高掺杂半导体区21与晶体管的漏极区41相连。现在，连接导体19形成了延伸进入MOST(在该示例中是NMOST)的沟道区42中的导体连接。连接导体17、18形成了NMOST的源极区43和漏极区41的电连接。在图15的截面图中未示出了MOS晶体管的栅极电极44的电连接。该示例的器件制造与根据前述示例的器件制造没什么本质区别。
当然，实质差别(参见图13)是这样的真实事实：现在晶体管T包括MOS晶体管，所述晶体管具有通常的结构并且按照通常的方式制造，但是其制造与第一示例的双极型晶体管的制造没什么不同(除了一些细节)。在该示例的器件10制造的第一步骤中的重要差别是在p型衬底11中形成所谓的n阱20，如同CMOS工艺中特别通常的。在形成晶体管之后，再次设置其中形成开口C、V的绝缘层13。
按照与第一示例相同的方式形成开口下陷区域2A和腔体1B(参见图14)，不同之处在于(前边已经注意到了)在有源区A和无源区P之间的半导体本体12的部分D中形成这些区域。
在形成掩模导电区1、下陷导电区2和连接导体17、18、19(参见图15)之后，可以在形成一个或更多金属化层(互连)之后、接着钝化之后的诸如锯切之类的分离工艺，再次获得针对最终组件所准备的单个器件10。
图16是与第三示例的器件变体的厚度方向垂直的示意性截面图。主要区别是在所述无源区P下面，形成通过无源区P的下陷导体区2。
这样的优点是使得可以减小侧向尺寸。
因为在不脱离本发明范围的情况下，对于本领域普通技术人员而言许多变化和修改是可能的，本发明不局限于这里所讨论的实施例。因此，除了适用于分立的半导体器件之外，本发明还非常适用于集成的半导体器件，例如(BI)CMOS((双极型)互补金属氧化物半导体)IC(集成电路)。在BICMOS IC的情况下，有利地，MOS晶体管和双极型晶体管可以是根据本发明的晶体管。另外应该注意的是代替使用沟槽隔离区，也可以使用通过LOCOS(硅的局部氧化)技术获得的隔离区。
另一个修改涉及掩埋导电区与半导体本体的重叠部分之间的触点的本质。依赖于后一部分的掺杂以及金属材料的选择，所述触点可以是欧姆接触、MIS(金属绝缘体半导体)接触或肖特基接触。在所述连接中，清楚的是连接导体不必是与下陷的导电区相同的材料。
对于根据本发明的方法，许多变化和修改也是可能的。因此，可以形成在示例中通过刻蚀来去除均匀的SiGe外延层的一部分来形成掩埋导电区。另一种可能是使用实际上局域化的并且限定的SiGe区。可以通过去除已经形成的SiGe层的一部分来形成所述区域，其后将半导体本体的硅部分形成于剩余部分上。另外，可以有利的使用选择性外延沉积，用于形成这种SiGe区。

Claims (6)

1.一种半导体器件(10)，具有衬底(11)和硅半导体本体(12)，该半导体器件(10)包括：
具有晶体管(T)的有源区(A)；
围绕有源区(A)的无源区(P)；
从所述半导体本体(12)的表面下陷的金属材料导电区(2)；以及
至少位于所述半导体本体(12)的有源区内的金属材料的掩埋导电区(1)，其特征在于所述掩埋导电区(1)包括：
与所述金属材料导电区(2)相连的部分；以及
所述有源区(A)中的包含金属材料的腔体(1B)，所述腔体(1B)延伸到与所述金属材料导电区(2)相连的部分并向着半导体本体(12)的表面延伸，从而所述掩埋导电区(1)的腔体(1B)距所述半导体本体(12)的表面比所述无源区(P)的厚度小的距离。
2.根据权利要求1所述的半导体器件(10)，其特征在于：用与形成晶体管的连接导体(7、8)的材料相同的材料填充掩埋导电区(1)和下陷的导电区(2)。
3.根据权利要求1或2所述的半导体器件(10)，其特征在于：半导体本体(12)的一部分(D)位于无源区(P)和有源区(A)之间，并且在所述部分(D)中形成下陷的导电区(2)。
4.根据权利要求1或2所述的半导体器件(10)，其特征在于：无源区(P)包括所谓的沟槽隔离区。
5.根据权利要求1或2所述的半导体器件(10)，其特征在于：晶体管包括双极型晶体管，并且所述双极型晶体管被设置有掩埋导电区(1)所在的集电极区(33)。
6.根据权利要求3所述的半导体器件(10)，其特征在于：晶体管包括MOS晶体管，所述MOS晶体管被设置有掩埋导电区(1)所在的沟道区。
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