CN101207137A - Material with metal silicide nanostructure and method for making the same - Google Patents
Material with metal silicide nanostructure and method for making the same Download PDFInfo
- Publication number
- CN101207137A CN101207137A CNA200610169554XA CN200610169554A CN101207137A CN 101207137 A CN101207137 A CN 101207137A CN A200610169554X A CNA200610169554X A CN A200610169554XA CN 200610169554 A CN200610169554 A CN 200610169554A CN 101207137 A CN101207137 A CN 101207137A
- Authority
- CN
- China
- Prior art keywords
- metal silicide
- nanostructure
- silicon
- metal
- soi substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a material with metal silicide nanometer structure and the preparation method thereof. The material comprises a metal silicide nanometer structure which is produced on an SOI substrate; the thickness of an insulation medium layer of the SOI substrate is 100 to 1000 nanometers, and the thickness of silicon thin film is 50 to 500 nanometers. The preparation method comprises the following steps: a required mask feature structure of nanometer structure is produced on the silicon thin film surface of the SOI substrate after cleaning, drying, spin coating positive photoresist, exposing, developing, and fixing; the silicon thin film of the SOI substrate is etched to the required nanometer structure by adopting a reactive ion etching, the etching depth is equal to the thickness of the silicon thin film, a metal thin film which is required by the metal silicide is deposited on the isolation layer which contains the silicon nanometer structure, then high temperatures anneal is performed to ensure that soild phase reaction is reacted between the metal and the silicon, thus to generate the metal silicide, the unreacted metal is removed through chemical etch, and then the metal silicide nanometer structure is formed. The method is simple, and the position and the dimension of the nanometer structure can be controlled.
Description
Technical field
The present invention relates to metal silicide nanostructure and preparation method thereof, particularly relate to and the integrated circuit fabrication process compatibility, have controlled shape and growth position, all have in fields such as integrated circuit, microelectronic component and nanometer electronic devices good application prospect, be produced on metal silicide nanostructure on SOI (silicon on insulator, thin-layer silicon on the insulating barrier) substrate and preparation method thereof.
Background technology
Metal silicide has characteristics such as lower resistivity, high thermal stability, good anti-electromigration performance and carrier mean free path be little, in nanometer electronic device and integrated circuit, has good application prospects, for example as interconnecting lead, source leakage and gate electrode etc.Along with reducing of device size, the metal silicide of making nanoscale becomes more and more important.With the nano wire is example, and the method for existing making metal silicide nano-wire roughly has following two kinds mainly based on the approach of " from bottom to top ": a kind of method is that the silicon nanowires that chemical vapour deposition (CVD) is synthetic is converted into metal silicide nano-wire; Another kind method is the direct growth metal silicide nano-wire.Now specifically describe as follows to these two kinds technology of making metal silicide nanostructure:
1. form metal silicide nano-wire by the synthetic silicon nanowires reaction of chemical vapour deposition (CVD): referring to documents 1, " single-crystal metal nano wire and metal/semiconductor nanowire heterojunction " (Single-crystal metallicnanowires and metal/semiconductor nanowire heterostructures), be stated from " Nature " 2004, on the Vol.430:61-65.It is to utilize chemical gaseous phase depositing process to synthesize silicon nanowires, and then plated metal nickel after 550 ℃ of annealing in process, is removed surperficial unreacted nickel with chemical corrosion method, thereby obtained nickel silicide nano-line on silicon nanowires.The manufacture method of this metal silicide nano-wire is owing to the influence of factors such as shape that is subjected to the initial silicon nano wire and growth position, and is wayward, be difficult to and present integrated circuit fabrication process compatibility, thereby its application is subjected to very big restriction.
2. direct growth metal silicide nano-wire: referring to documents 2, " oriented growth of nickel silicide nano-line " (Directed growth of nickel silicide nanowires), be stated from " Applied Physics Letters " 2004, Vol.84:1389-1391.It is a first plated metal nickel on dielectric substrate, both as catalyst, as the source metal of growth silicide, goes out nickel silicide nano-line by catalytic decomposition silane direct growth again; Assisting down of electric field, nickel silicide nano-line can be realized oriented growth between two nickel islands.Though this method can be controlled the direction of growth of metal silicide nano-wire to a certain extent, but still be difficult to realize the controllability of aspects such as its size, shape and growth position, can't with present integrated circuit fabrication process compatibility.
The method that is used to make metal silicide nanostructure at present is difficult to generally realize that its size, shape and growth position control comparatively accurately, can't be applied to present integrated circuit fabrication process.Though once the someone proposed to utilize mask plated metal nanostructure and then reaction on silicon substrate to form metal silicide nanostructure, this with integrated circuit fabrication process in make interconnecting lead and source leakage and gate electrode actual conditions still greatly differ from each other.On the other hand, the SOI substrate is an ideal material of making the high reliability integrated circuit, substituted for silicon is used widely aspect the large scale integrated circuit, therefore on the SOI substrate, make metal silicide nanostructure and just seem extremely important, and yet there are no relevant patent and reported in literature at present both at home and abroad.
Summary of the invention:
The objective of the invention is to: overcome the existing existing size of method, shape and the uppity shortcoming of growth position for preparing metal silicide nanostructure, a kind of material and preparation method who makes metal silicide nanostructure on the SOI substrate is provided, the metal silicide nanostructure of made and present integrated circuit fabrication process compatibility, both be applicable to the making of interconnecting lead and electrode in the integrated circuit, also can be used for studying the physics and the chemical characteristic of these nanostructures itself; This method has controlled size, shape and growth position.
The object of the present invention is achieved like this:
Material with metal silicide nanostructure provided by the invention comprises the metal silicide nanostructure of substrate and the making on substrate; It is characterized in that, described substrate is the dielectric interlayer 2 of growth on monocrystalline silicon piece 1 and the SOI substrate that silicon thin film 3 is formed, the dielectric thickness of interlayer of this SOI substrate is the 100-1000 nanometer, and the thickness of silicon thin film 3 is the 50-500 nanometer, and described silicon thin film 3 is monocrystalline silicon or polysilicon film; The I of the yardstick of described nanostructure reaches below 10 nanometers.
Described metal silicide comprises: transition metal silicides such as titanium silicide, cobalt silicide or nickle silicide.
Described dielectric interlayer comprises: silicon dioxide, silicon nitride, aluminium nitride, diamond, carbon nitrogen, boron nitride, HSQ (disilicon trioxide alkane), MSQ (methyl disilicon trioxide alkane) and other dielectric.
Manufacture method with material of metal silicide nanostructure provided by the invention may further comprise the steps:
1) select the SOI substrate, this SOI substrate is through cleaning, drying for standby;
2) the metal silicide nanostructure figure that designs deposits in the electron beam exposure apparatus, or the focused ion beam straight-writing system;
3) utilize the process technology of nanoscale, spin coating positive photoresist on the SOI substrate is through the hot plate baking of going forward, utilize the electron beam exposure system exposure, after development and photographic fixing, on silicon thin film 3 surfaces of SOI substrate, produce the mask graph structure 4 of required nanostructure;
4) adopt reactive ion etching method, the silicon thin film 3 of SOI substrate is etched into required nanostructure, promptly by reactive ion etching process with step 2) mask graph 4 made transfers on the silicon thin film 3, form silicon nanostructure 5, the degree of depth of etching is the thickness of silicon thin film 3, make that in the place that does not need to form metal silicide, silicon is etched away fully;
5) adopt coating process containing on the dielectric interlayer 2 of silicon nanostructure 5, deposition forms the required metallic film 6 of metal silicide;
6) sample that step 5) is made carries out high annealing in reative cell, makes plated film metal and silicon generation solid phase reaction generate metal silicide, and its annealing conditions is as follows: to reative cell
The interior argon gas that feeds, flow is 100-500sccm, and substrate heating temperature is in 300-900 ℃ of scope, and reaction pressure is 1-100kPa; For different metal silicides, also need correspondingly optimize technological parameter;
7) adopt chemical corrosion method, will adopt chemical corrosion method to remove to unreacted metal, promptly form metal silicide nanostructure 7 in position corresponding to silicon nanostructure 5 through the sample behind the step 6) high annealing.
In above-mentioned technical scheme, SOI substrate described in the step 1) can be to buy on the market, or utilize monocrystalline silicon piece to pass through the preparation of injection oxygen isolation technology or bonding technology, mode that also can be by spin coating or deposition after forming insulating barrier on the substrate again the sputtering sedimentation polysilicon membrane make.Choosing of described SOI substrate need be in conjunction with the actual conditions in the integrated circuit, the function that will realize according to the metal silicide nanostructure of making and deciding.For example, if metal silicide is that the thin-layer silicon on the then selected SOI substrate should be monocrystalline silicon as source-drain electrode; If metal silicide is that then the thin-layer silicon on the SOI substrate of Xuan Zeing should be polysilicon film, so just can directly apply to the making of device and circuit as interconnecting lead or gate electrode.The thickness of insulating barrier is generally the 100-1000 nanometer, and the thickness of silicon thin film is generally the 50-500 nanometer, with the thickness of the metal silicide nanostructure that will prepare and decide.
In above-mentioned technical scheme, step 2) the nanoscale process technology described in mainly is meant electron beam lithography, X-ray lithography, focused ion beam lithography and extreme ultraviolet photolithographic etc., they all are to utilize photoresist as interim medium, form the mask graph of required nanostructure on silicon thin film by operations such as exposure imagings.Usually can also utilize plasma suitably the mask graph that photoresist constitutes to be carried out ashing treatment, the yardstick of nanostructure is further dwindled.
In above-mentioned technical scheme, when removing unwanted silicon thin film by reactive ion etching process in the step 3), usually select for use sulphur hexafluoride as reacting gas, it is etch silicon more fast, and the selectivity of etching is also relatively good, and promptly the speed of the dielectrics such as speed ratio etching oxidation silicon of etch silicon is high a lot.
In above-mentioned technical scheme, during the step 4) depositing metal films, can adopt the metallic target sputtering method, comprise magnetron sputtering, DC glow sputter and ion beam sputtering etc., also can adopt the metal evaporation method, comprising: thermal evaporation, electron beam evaporation etc.; The kind of the metallic film of deposition is decided according to the kind of metal in the metal silicide that will prepare, it can be any metal that can form metal silicide, as titanium, cobalt, nickel etc., the thickness of metal film is generally the 30-500 nanometer, is as the criterion can make corresponding silicon nanostructure reaction form metal silicide at least.
In above-mentioned technical scheme, the high annealing described in the step 5) can carry out in the equipment of depositing metal films, also can take out from the equipment of original depositing metal films, carries out in other high temperature furnace again.
In above-mentioned technical scheme, the chemical corrosion method described in the step 6) is meant the employing chemical mordant, erode surperficial unreacted metal, and this corrosive agent does not corrode to established metal silicide.For example, make the titanium disilicide nanostructure, chemical mordant is 1: 1 the concentrated sulfuric acid and a hydrogen peroxide; Make the cobalt silicide nano wire, chemical mordant is 1: 1: 5 the concentrated sulfuric acid, hydrogen peroxide and a water; Make nickel silicide nano-line, chemical mordant is 4: 1 the concentrated sulfuric acid and a hydrogen peroxide.
The invention has the advantages that:
1. the present invention adopts the SOI material to make metal silicide nanostructure as substrate, because the existence of insulating interlayer in the SOI material, make device and the circuit made realize full dielectric isolation thereon, eliminate the latch-up of device and circuit, adopted the circuit and the device of SOI material to have the integration density height, speed is fast, low in energy consumption, high temperature resistant and advantage such as radioresistance.In addition, the metal silicide nanostructure interconnection line of realizing on the SOI substrate has been because the buffer action of insulating barrier has reduced between the interconnection line and the interaction between interconnection line and substrate effectively, for high-reliability electronic device and production of integrated circuits provide guarantee.
2. owing to adopt the micro-machined photoetching technique scheme of nanoscale, the metal silicide nanostructure that method of the present invention is made has the characteristics of size, shape and position-controllable, can make the nanostructure of arbitrary shape in the position that needs arbitrarily, the I of the yardstick in the plane reaches below 10 nanometers.
3. metal silicide nanostructure is made on the SOI substrate among the present invention, this with integrated circuit in the actual needs of filling by dielectric between interconnecting lead be consistent, so for ic manufacturing technology using value will be arranged more to the physics and the chemical characteristic research of the metal silicide nanostructure of such making.
4. method of the present invention is compared with existing method of making metal silicide nanostructure, it is simple to have manufacture craft, characteristics such as efficient is high and can produce in batches, the more important thing is because the introducing of nanoscale process technology, prepared metal silicide nanostructure has the precision height, good reproducibility is with present characteristics such as the complete compatibility of semiconductor technology.
Description of drawings:
The making schematic flow sheet of Fig. 1 metal silicide nanostructure of the present invention, wherein
Fig. 1 (a) is depicted as the SOI backing material;
Fig. 1 (b) produces the mask graph of required nanostructure on the thin-layer silicon of SOI substrate;
Fig. 1 (c) is etched into required nanostructure with thin-layer silicon;
Fig. 1 (d) comprises depositing metal films on the substrate of silicon nanostructure at Fig. 1 (c);
Fig. 1 (e) autoregistration on silicon nanostructure forms metal silicide nanostructure.
The drawing explanation:
1-monocrystalline silicon piece 2-dielectric interlayer
3-silicon thin film 4-mask graph structure
The silicon nanostructure 6-metallic film that stays after the 5-etching
The 7-metal silicide nano-wire
Fig. 2 is the stereoscan photograph of the nickel silicide nano-line of employing the present invention making
Concrete execution mode
Below by accompanying drawing and manufacture method the material with metal silicide nanostructure of the present invention is described in detail.
With reference to Fig. 1, make present embodiment nickle silicide nanostructure by flow process of the present invention:
1) select the SOI substrate with monocrystalline silicon thin layer for preparing by injection oxygen isolation technology for use, its crystal orientation is (100), and this SOI substrate is made up of dielectric interlayer 2 of growing on monocrystalline silicon piece 1 and top layer silicon film 3; Top layer silicon film 3 is a monocrystalline silicon, and its thickness is 100 nanometers, and the thickness of dielectric interlayer 2 is 350 nanometers;
2) with the described SOI substrate of step 1), pass through acetone respectively, after alcohol and washed with de-ionized water and the oven dry, positive photoresist PMMA in the spin coating, went forward to dry by the fire 1 minute at 180 ℃ of hot plates, photoresist thickness is about 100 nanometers, utilize Raith 150 electron beam exposure systems on photoresist layer, directly write two long 100 microns, wide 10 microns rectangular figure, their adjacent edge is spaced apart 50 nanometers, just having stayed a length like this between these two rectangles is 100 microns, width is the unexposed area of 50 nanometers, and through obtaining corresponding photoresist figure after development and the photographic fixing, promptly the mask graph structure 4;
3) sample that will have photoresist mask graph structure 4 is put into Oxford Plasmalab 80 Plus reactive ion etching systems, carry out etching with sulphur hexafluoride, with the photoresist figure transfer on top layer silicon, remove residual photoresist with the oxygen etching at last, just can obtain the silicon nanostructure 5 (silicon lines) that stays after the etching; Wherein the used parameter of etch silicon is: the flow of sulphur hexafluoride is 50sccm, and reaction pressure is 50mTorr, and power is 100W, etch period 1 minute.Removing the used parameter of residual photoresist with the oxygen etching is: the flow of oxygen is 100sccm, and reaction pressure is 100mTorr, and power is 100W, 30 seconds of etch period.
4) will put into magnetic control sputtering system through the sample after the step 3) etching, adopt conventional magnetron sputtering thin film technique depositing metal films 6 thereon, this metallic film 6 is a metal nickel film, the nickel film thickness is 50 nanometers, sputtering condition is: sputtering power 60W, air pressure 1Pa, underlayer temperature are room temperature, and argon flow amount is 200sccm;
5) carry out the substrate heating in magnetic control sputtering system, realize the annealing under the high temperature, make metallic nickel and silicon generation solid phase reaction, form the nickle silicide nanostructure in the position autoregistration with silicon nanostructure, promptly metal silicide nano-wire 7; Wherein annealing conditions is: the flow of argon gas is 400sccm, and reaction pressure is 5kPa, and underlayer temperature is in 450 ℃ of scopes, and annealing time is 5 minutes.
6) sample after handling through step 5) is carried out chemical corrosion, chemical corrosion liquid is sulfuric acid and hydrogen peroxide mixed liquor, and its volume ratio is 4: 1, erodes surperficial unreacted metal, has formed the nickle silicide nanostructure in the position of silicon nanostructure correspondence.
The nickle silicide nanostructure of present embodiment preparation referring to Fig. 2, the width of the silication nickel wire that shows among the figure is 280 nanometers.
With reference to figure 1, the preparation method of present embodiment carries out according to the technological process of Fig. 1, is described in detail as follows:
1) goes up by spin coating HSQ solution at monocrystalline silicon substrate (monocrystalline silicon supporting layer 1), through 250 ℃ of bakings after 2 minutes formula form the HSQ dielectric interlayer 2 that thickness is about 150 nanometers, utilize magnetron sputtering deposition polysilicon thin layer then, thickness is about 80 nanometers, forms the SOI substrate
2) will be in the SOI substrate spin coating of step 1) preparation negative photoresist (SAL 601), went forward to dry by the fire 2 minutes at 105 ℃ of hot plates, photoresist thickness is about 200 nanometers, utilizing Raith 150 electron beam exposure systems a series of length of exposing is 100 microns, width is the lines of 250 nanometers, the back baking is 2 minutes on 105 ℃ of hot plates, through just obtaining corresponding photoresist mask graph after development and the photographic fixing.
3) with step 2) sample of made puts into Oxford Plasmalab 80 Plus reactive ion etching systems, carry out etching with sulphur hexafluoride, the photoresist figure transfer on top layer silicon, is removed residual photoresist with the oxygen etching at last, just can obtain the silicon lines.Wherein the used parameter of etch silicon is: the flow of sulphur hexafluoride is 50sccm, and reaction pressure is 50mTorr, and power is 100W, 50 seconds of etch period.Removing the used parameter of residual photoresist with the oxygen etching is: the flow of oxygen is 100sccm, and reaction pressure is 100mTorr, and power is 100W, etch period 1 minute.
4) will put into magnetic control sputtering system through the sample that the rapid etching of previous step is crossed, and adopt conventional magnetron sputtering thin film technique plated metal nickel thereon, thickness is 40 nanometers, sputtering condition is: sputtering power 60W, air pressure 1Pa, underlayer temperature are room temperature, and argon flow amount is 100sccm.
5) behind the intact nickel of sputter, in magnetic control sputtering system, substrate is carried out the add in-place thermal annealing, make metallic nickel and pasc reaction, form the nickle silicide nanostructure in the position that silicon is arranged.Wherein annealing conditions is: the flow of argon gas is 200sccm, and reaction pressure is 2kPa, and underlayer temperature is 450 ℃, and annealing time is 5 minutes.
6) after the annealing in process, sample is taken out from magnetic control sputtering system, with volume ratio is that 4: 1 sulfuric acid and hydrogen peroxide mixed liquor carries out chemical corrosion, removes surperficial unreacted metal, stays nickle silicide nanostructure as shown in Figure 2 in the position of silicon nanostructure correspondence.
With reference to figure 1, present embodiment is made the technological process of titanium disilicide nanostructure and is undertaken by shown in Figure 1, and concrete steps are as follows:
1) select the SOI substrate with monocrystalline silicon thin layer that is prepared by injection oxygen isolation technology for use, its crystal orientation is (100), and the thickness of top layer silicon is thinned to 50 nanometers through after the reactive ion etching, and the thickness of buried silicon oxide layer is 350 nanometers.
2) will be through the SOI substrate behind the step 1) attenuate, positive photoresist PMMA in the spin coating, 180 ℃ were toasted 1 minute, and photoresist thickness is about 100 nanometers, puts into Raith 150 electron beam exposure systems and exposes.Graphic designs be quadrate array by 4.9 microns of length of side positions, the cycle is 5.0 microns, the exposure back just can stay the mutually orthogonal lines that width is about 100 nanometers like this.Through just obtaining the photoresist figure after development and the photographic fixing.
3) will expose and developing fixing after sample put into the reactive ion etching system, use the sulphur hexafluoride etch silicon, be etched away photoresist with oxygen then, just can obtain silicon lines grid.Wherein the used parameter of etch silicon is: the flow of sulphur hexafluoride is 50sccm, and reaction pressure is 50mTorr, and power is 100W, 30 seconds of etch period.Being etched away the used parameter of photoresist with oxygen is: the flow of oxygen is 100sccm, and reaction pressure is 100mTorr, and power is 100W, 30 seconds of etch period.
4) will put into the evaporation coating system through the sample after the step 3) etching, and adopt the mode plated metal titanium of thermal evaporation, thickness is 20 nanometers, and substrate does not heat in the plated metal process.
5) thermal evaporation has been deposited the sample transfer of Titanium in high-temperature annealing furnace; under the argon gas atmosphere protection, carry out annealing in process; the flow of argon gas is 300sccm; reaction pressure is 4kPa; after rising to 850 ℃, underlayer temperature promptly stops heating; treat that Titanium and silicon react, thereby form titanium disilicide nano wire network.
6) utilize the mixed liquor of chemical corrosion liquid sulfuric acid and hydrogen peroxide at last, its volume ratio is 1: 1, and surperficial unreacted metal titanium is removed, and produces the titanium disilicide nano wire network of present embodiment.
Claims (8)
1. material with metal silicide nanostructure comprises the metal silicide nanostructure of substrate and the making on substrate; It is characterized in that, described substrate is to go up the dielectric interlayer (2) of growth and the SOI substrate that top layer silicon film (3) is formed at monocrystalline silicon piece (1), the monocrystalline silicon piece of this SOI substrate (1) thickness is the 100-800 micron, the thickness of dielectric interlayer (2) is the 100-1000 nanometer, the thickness of described silicon thin film (3) is the 50-500 nanometer, and this silicon thin film (3) is monocrystalline silicon or polysilicon film.
2. by the described material with metal silicide nanostructure of claim 1, it is characterized in that described metal silicide is a transition metal silicide, this transition metal silicide comprises: titanium silicide, cobalt silicide or nickle silicide.
3. by the described material of claim 1 with metal silicide nanostructure, it is characterized in that described insulating medium layer comprises: silicon dioxide, silicon nitride, aluminium nitride, diamond, carbon nitrogen, boron nitride, disilicon trioxide alkane or methyl disilicon trioxide alkane.
4. manufacture method with material of metal silicide nanostructure may further comprise the steps:
1) select the SOI substrate, this SOI substrate is through cleaning, drying for standby;
2) the metal silicide nanostructure figure that designs deposits in the electron beam exposure apparatus, or the focused ion beam straight-writing system;
3) utilize the process technology of nanoscale, spin coating positive photoresist on the SOI substrate is through the hot plate baking of going forward, utilize the electron beam exposure system exposure, after development and photographic fixing, on silicon thin film (3) surface of SOI substrate, produce the mask graph structure (4) of required nanostructure;
4) adopt reactive ion etching method, by reactive ion etching process with step 2) mask graph (4) made transfers on the silicon thin film (3), the silicon thin film of SOI substrate is etched into required nanostructure (4), the degree of depth of etching is the thickness of silicon thin film (3), make that in the place that does not need to form metal silicide, silicon is etched away fully;
5) adopt coating process containing on the dielectric interlayer (2) of silicon nanostructure (5), deposition forms the required metallic film (6) of metal silicide, and the thickness of this metallic film (6) is the 30-500 nanometer;
6) adopt the high annealing method to make metal and silicon generation solid phase reaction, generate metal silicide, its annealing conditions is as follows: feed argon gas, flow is 100-500sccm, and substrate heating temperature is in 300-900 ℃ of scope, and reaction pressure is 1-100kPa;
7) adopt chemical corrosion method, the unreacted metal on sample is removed, form metal silicide nanostructure (7) in position corresponding to silicon nanostructure (5).
5. by the described manufacture method of claim 4 with material of metal silicide nanostructure, it is characterized in that, described SOI substrate is to buy on the market, or utilize monocrystalline silicon piece to pass through the preparation of injection oxygen isolation technology or bonding technology, or the mode by spin coating or deposition after forming insulating medium layer on the substrate again the sputtering sedimentation polysilicon membrane make.
6. by the described manufacture method of claim 1 with material of metal silicide nanostructure, it is characterized in that step 2) described in the nanoscale processing method comprise: electron beam lithography, X-ray lithography, focused ion beam lithography or extreme ultraviolet carving method.
7. by the described manufacture method of claim 1, it is characterized in that the step 4) depositing metal films adopts the metallic target sputtering method, comprises magnetron sputtering, DC glow sputter and ion beam sputtering with material of metal silicide nanostructure; Or adopt the metal evaporation method, comprising: thermal evaporation or electron beam evaporation method.
8. by the described manufacture method of claim 1, it is characterized in that the chemical corrosion method described in the step 6) comprises and make the titanium disilicide nanostructure that the employing chemical mordant is 1: 1 the concentrated sulfuric acid and a hydrogen peroxide with material of metal silicide nanostructure; Make the cobalt silicide nano wire, the employing chemical mordant is 1: 1: 5 the concentrated sulfuric acid, hydrogen peroxide and a water; Make nickel silicide nano-line, the employing chemical mordant is 4: 1 the concentrated sulfuric acid and a hydrogen peroxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610169554XA CN100524782C (en) | 2006-12-22 | 2006-12-22 | Material with metal silicide nanostructure and method for making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610169554XA CN100524782C (en) | 2006-12-22 | 2006-12-22 | Material with metal silicide nanostructure and method for making the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101207137A true CN101207137A (en) | 2008-06-25 |
| CN100524782C CN100524782C (en) | 2009-08-05 |
Family
ID=39567161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200610169554XA Expired - Fee Related CN100524782C (en) | 2006-12-22 | 2006-12-22 | Material with metal silicide nanostructure and method for making the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100524782C (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102092675A (en) * | 2011-01-14 | 2011-06-15 | 中国科学院物理研究所 | Method for preparing self-masking uni-junction multiport three-dimensional nano structure |
| CN102229421A (en) * | 2011-04-26 | 2011-11-02 | 复旦大学 | Preparation method of nanowire structure |
| CN101587902B (en) * | 2009-06-23 | 2011-12-07 | 吉林大学 | Silicon-on-nanometer-insulator material and preparing method thereof |
| CN102107847B (en) * | 2009-12-23 | 2013-01-16 | 中国科学院物理研究所 | Method for preparing three-dimensional micro-nano device |
| CN104878355A (en) * | 2015-04-30 | 2015-09-02 | 北京空间飞行器总体设计部 | Preparation method of nano-medium layer based on magnetron sputtering process |
| CN105424236A (en) * | 2015-11-19 | 2016-03-23 | 南京信息工程大学 | Multi-range array pressure sensing chip and detection method thereof |
| CN107046228A (en) * | 2017-04-07 | 2017-08-15 | 华南师范大学 | A kind of Electroabsorption Modulated Laser and preparation method thereof |
| CN107799387A (en) * | 2016-09-06 | 2018-03-13 | 中国科学院上海微系统与信息技术研究所 | A kind of method and structure that silicon nanowires is prepared on the polysilicon layer of doping |
| CN111244031A (en) * | 2020-01-21 | 2020-06-05 | 复旦大学 | Preparation method of small-size silicide nanowire and small-size silicide nanowire |
| CN113265635A (en) * | 2021-04-29 | 2021-08-17 | 杭州电子科技大学 | Preparation method and product of transition metal sulfide material patterning |
| CN113540284A (en) * | 2020-04-17 | 2021-10-22 | 中国科学院苏州纳米技术与纳米仿生研究所 | Aluminum nitride nanosheet array and manufacturing method thereof |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6750124B1 (en) * | 2001-02-06 | 2004-06-15 | Arizona Board Of Regents | Direct patterning of nanometer-scale silicide structures on silicon by ion-beam implantation through a thin barrier layer |
| US6773616B1 (en) * | 2001-11-13 | 2004-08-10 | Hewlett-Packard Development Company, L.P. | Formation of nanoscale wires |
| US6699779B2 (en) * | 2002-03-22 | 2004-03-02 | Hewlett-Packard Development Company, L.P. | Method for making nanoscale wires and gaps for switches and transistors |
| US6713393B2 (en) * | 2002-06-20 | 2004-03-30 | Intelligent Sources Development Corp. | Method of forming a nanometer-gate MOSFET device |
| KR100612853B1 (en) * | 2004-07-21 | 2006-08-14 | 삼성전자주식회사 | Si based material layer having wire type silicide and method of forming the same |
| US7253105B2 (en) * | 2005-02-22 | 2007-08-07 | International Business Machines Corporation | Reliable BEOL integration process with direct CMP of porous SiCOH dielectric |
| US20060255405A1 (en) * | 2005-05-12 | 2006-11-16 | National Chiao Tung University | Fully-depleted SOI MOSFET device and process for fabricating the same |
| CN100582043C (en) * | 2006-04-24 | 2010-01-20 | 浙江大学 | Titanium silicide nano-nail prepared by chemical vapor deposition under normal pressure and preparation method thereof |
-
2006
- 2006-12-22 CN CNB200610169554XA patent/CN100524782C/en not_active Expired - Fee Related
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101587902B (en) * | 2009-06-23 | 2011-12-07 | 吉林大学 | Silicon-on-nanometer-insulator material and preparing method thereof |
| CN102107847B (en) * | 2009-12-23 | 2013-01-16 | 中国科学院物理研究所 | Method for preparing three-dimensional micro-nano device |
| CN102092675A (en) * | 2011-01-14 | 2011-06-15 | 中国科学院物理研究所 | Method for preparing self-masking uni-junction multiport three-dimensional nano structure |
| CN102229421A (en) * | 2011-04-26 | 2011-11-02 | 复旦大学 | Preparation method of nanowire structure |
| CN102229421B (en) * | 2011-04-26 | 2016-01-20 | 复旦大学 | The preparation method of nano thread structure |
| CN104878355B (en) * | 2015-04-30 | 2017-04-05 | 北京空间飞行器总体设计部 | A kind of nanometer dielectric layer preparation method based on magnetron sputtering technique |
| CN104878355A (en) * | 2015-04-30 | 2015-09-02 | 北京空间飞行器总体设计部 | Preparation method of nano-medium layer based on magnetron sputtering process |
| CN105424236A (en) * | 2015-11-19 | 2016-03-23 | 南京信息工程大学 | Multi-range array pressure sensing chip and detection method thereof |
| CN107799387A (en) * | 2016-09-06 | 2018-03-13 | 中国科学院上海微系统与信息技术研究所 | A kind of method and structure that silicon nanowires is prepared on the polysilicon layer of doping |
| CN107046228A (en) * | 2017-04-07 | 2017-08-15 | 华南师范大学 | A kind of Electroabsorption Modulated Laser and preparation method thereof |
| CN107046228B (en) * | 2017-04-07 | 2019-08-06 | 华南师范大学 | A kind of Electroabsorption Modulated Laser and preparation method thereof |
| CN111244031A (en) * | 2020-01-21 | 2020-06-05 | 复旦大学 | Preparation method of small-size silicide nanowire and small-size silicide nanowire |
| CN113540284A (en) * | 2020-04-17 | 2021-10-22 | 中国科学院苏州纳米技术与纳米仿生研究所 | Aluminum nitride nanosheet array and manufacturing method thereof |
| CN113265635A (en) * | 2021-04-29 | 2021-08-17 | 杭州电子科技大学 | Preparation method and product of transition metal sulfide material patterning |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100524782C (en) | 2009-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100524782C (en) | Material with metal silicide nanostructure and method for making the same | |
| CN101499406B (en) | Method for producing silicide nano-structure on insulated underlay | |
| CN100423245C (en) | Metal silicide nano-wire and its making method | |
| CN107460542A (en) | A kind of preparation method of the stretchable crystalline semiconductor nano wire based on plane nano line Alignment Design and guiding | |
| CN102629559B (en) | Manufacture method of stacked gate SiC-metal insulator semiconductor (MIS) capacitor | |
| CN113039486A (en) | Hard mask manufacturing method capable of being used in next generation photoetching | |
| JP2012505816A (en) | Control method of graphene film growth | |
| CN101312213A (en) | Nanocrystalline floating gate structure non-volatility memory cell and its manufacture method | |
| CN101941696B (en) | Nanolithographic method applied to manufacture of graphene-based field effect tube | |
| CN109728096B (en) | Ferroelectric field effect transistor based on aluminum oxide material embedded nanocrystalline and preparation method thereof | |
| CN101794072B (en) | Method for preparing substrate with nano structure with line width below 20 nanometers | |
| CN105006482A (en) | Preparation method of graphene field effect transistor | |
| CN105097452B (en) | A kind of preparation method of the carborundum films with micron, sub-micron and nanometer hierarchical structure | |
| CN115458673B (en) | Superconducting quantum chip first layer structure and preparation method thereof | |
| WO2014124308A2 (en) | Multi-level graphene devices and methods for forming same | |
| CN108054086B (en) | Ultrashort channel based on polystyrene spheres and preparation method | |
| CN113421826B (en) | Atomic-level precision lossless layer-by-layer etching method for two-dimensional layered material | |
| CN1160797C (en) | Point-contact planar grid type single-electron transistor and its preparing process | |
| CN113540284B (en) | Aluminum nitride nanosheet array and manufacturing method thereof | |
| CN108502840A (en) | A kind of method that high efficiency prepares cyclic annular nano gap oldered array | |
| CN117438376B (en) | Complementary field effect transistor based on two-dimensional material and preparation method thereof | |
| CN110620043B (en) | Preparation method of semiconductor thin film field effect transistor made of unstable two-dimensional material | |
| CN115835768B (en) | Protective layer for preparing superconducting quantum chip and superconducting quantum chip | |
| CN114566424A (en) | Process method for directly growing graphical graphene on integrated circuit chip | |
| CN105938813A (en) | Manufacturing method for wafer level uniaxial strain SOI based on silicon nitride stress thin film and scale effect |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090805 Termination date: 20111222 |