WO2014124308A2

WO2014124308A2 - Multi-level graphene devices and methods for forming same

Info

Publication number: WO2014124308A2
Application number: PCT/US2014/015384
Authority: WO
Inventors: Mark Alan Davis
Original assignee: Solan, LLC
Priority date: 2013-02-08
Filing date: 2014-02-07
Publication date: 2014-08-14
Also published as: WO2014124308A3

Abstract

Multi-level graphene devices and methods for forming such devices are provided. A first foundation material is deposited onto a substrate thereby forming a first foundation layer. Graphene is grown on the first foundation layer thereby forming a first graphene level having one or more graphene stacks at least one of which comprises a first graphene based nanostructure. An interlayer is formed on the first graphene level. A second foundation material is deposited onto the interlayer thereby forming a second foundation layer. Graphene is grown on the second foundation layer thereby forming a second graphene level. Like the first graphene level, the second graphene level includes one or more graphene stacks at least one of which comprises a second graphene based nanostructure.

Description

MULTI-LEVEL GRAPHENE DEVICES AND METHODS FOR FORMING SAME

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to United States Patent Application No.

61/762,776, filed February 8, 2014, entitled "Multi-Level Graphene Devices and Methods for Forming Same" which is hereby incorporated by reference herein in its entirety.

FIELD OF THE DISCLOSURE

[0002] The disclosed embodiments are generally related to multi-level graphene devices and the methods by which such devices are made.

BACKGROUND

[0003] A thin layer of a material, typically nanometers thick, can exhibit enhanced properties for various promising applications. A graphene sheet and a thin graphitic layer comprising a plurality of graphene sheets are good examples. Compared to its bulk three- dimensional counterparts, a graphene sheet and a thin graphitic layer have demonstrated many exceptional chemical, mechanical, electronic and optical properties, including high carrier mobility, high Young's elastic modulus, and excellent thermoconductivity. Such materials are well suited for applications in electronic devices, super-strong composite materials, and energy generation and storage. A drawback with such devices is their difficulty to pattern. Thus, manufacturing methods for making graphene based devices without any requirement for patterning the graphene are desired.

SUMMARY

[0004] The present disclosure advantageously provides systems methods for making graphene based thin films from layered materials and band gap devices formed without any requirement for patterning graphene. For instance, one aspect of the present disclosure provides a method for fabricating multilevel stacked graphene structures. The method includes optionally depositing a first foundation material onto a substrate thereby forming a first foundation layer. Graphene is formed using the first foundation layer or by other means thereby forming a first graphene level. The first graphene level comprises one or more graphene stacks. A graphene stacks in the first graphene level forms a first graphene based nanostructure. In one example, the first graphene based nanostructure has a dimension (e.g., height, length, width, perimeter, etc.) that is 100 microns or less, 10 microns or less, 1 micron or less, 500 nanometers or less, 100 nanometers or less, 50 nanometers or less, 25 nanometers or less, or between 2 and 25 nanometers.

[0005] The method further includes forming a first interlayer on the first graphene level. After forming the first interlayer, an optional second foundation material, which may be the same as or different than the optional first foundation material, is optionally deposited onto the first interlayer thereby forming a second foundation layer. Graphene is grown onto the second foundation layer using the optional second foundation material or by other means thereby forming a second graphene level. Like the first graphene level, the second graphene level includes one or more graphene stacks, with a respective graphene stack in the second graphene level including a second graphene based nanostructure. In one example, the second graphene based nanostructure has a dimension (e.g., height, length, width, perimeter, etc.) that is 100 microns or less, 10 microns or less, 1 micron or less, 500 nanometers or less, 100 nanometers or less, 50 nanometers or less, 25 nanometers or less, or between 2 and 25 nanometers.

[0006] Another aspect of the present disclosure provides a method for fabricating stacked graphene layers. The method includes optionally depositing a first foundation material onto a substrate thereby forming an optional first foundation layer. Next, graphene is formed using the first foundation layer, or by other means, thereby forming a first graphene layer. The first graphene layer includes a first graphene based nanostructure. A second foundation material is optionally is deposited onto the first graphene layer thereby forming an optional second foundation layer. Graphene is grown using the second optional foundation layer or by other means thereby forming a second graphene layer on the first graphene layer. The second graphene layer comprises a second graphene based nanostructure.

[0007] Yet another aspect of the present disclosure provides a method for fabricating stacked graphene layers. The method includes depositing a first foundation material onto a substrate, thereby forming a first foundation layer. Next, the first foundation layer is etched such that a reduced thickness first foundation layer is exposed in recesses in the substrate. Graphene is then grown onto the reduced thickness first foundation layer thereby forming a first graphene layer in the recesses in the substrate. As with previously described aspects of the present disclosure, the first graphene layer includes a first graphene based nanostructure. A second foundation material is deposited onto the first graphene layer, thereby forming a second foundation layer. As with the first foundation layer, the second foundation layer is then etched such that a reduced thickness second foundation layer is exposed in the recesses in the substrate. The method further includes growing graphene onto the reduced thickness second foundation layer thereby forming a second graphene layer in the recesses in the substrate. The second graphene layer includes a second graphene based nanostructure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present application and, together with the detailed description, serve to explain the principles and implementations of the application.

[0009] FIG. 1 A provides a flow chart of an exemplary method for fabricating multilevel stacked graphene structures, in accordance with an embodiment of the present disclosure.

[0010] FIG. IB provides a flow chart of an exemplary method for fabricating stacked graphene layers, in accordance with some embodiments of the present disclosure.

[0011] FIG. 1C provides a flow chart of another exemplary method for fabricating stacked graphene layers, in accordance with some embodiments of the present disclosure.

[0012] FIG. 2A is a detailed graphical representation of an exemplary method for forming graphene on a substrate using foundation material, in accordance with some embodiments of the present disclosure.

[0013] FIG. 2B is a detailed graphical representation of an exemplary method for forming multilevel stacked graphene structures, in accordance with some embodiments of the present disclosure.

[0014] FIG. 2C is a detailed graphical representation of an exemplary method for forming multilevel stacked graphene structures having backfilled interlayers, in accordance with some embodiments of the present disclosure. [0015] FIG. 2D is a detailed graphical representation of an exemplary method for forming stacked graphene layers without interlayers, in accordance with some embodiments of the present disclosure.

[0016] FIG. 2E is a detailed graphical representation of another exemplary method for forming stacked graphene layers without interlayers, in accordance with some embodiments of the present disclosure.

[0017] FIGS. 2F-2G depict a detailed graphical representation of an exemplary method for forming stacked graphene layers in recesses of a substrate, in accordance with some embodiments of the present disclosure.

[0018] FIGS. 2H-2J depict detailed graphical representations of exemplary multilevel stacked graphene structures with variable dimensions and layouts, in accordance with some embodiments of the present disclosure.

[0019] FIG. 3 depicts a two-dimensional view of one layer of a graphene nanoribbon, in accordance with the prior art.

[0020] FIG. 4 illustrates an exemplary multiple band gap device that is made using the methods of the present disclosure.

[0021] FIG. 5 illustrates an additional exemplary multiple band gap device that is made in accordance with an aspect of the present disclosure.

[0022] FIG. 6 depicts a schematic electrical diagram of a multiple band gap photovoltaic device, in accordance with some embodiments of the present disclosure.

[0023] FIG. 7 depicts a schematic electrical diagram of a multiple band gap photodetector, in accordance with some embodiments of the present disclosure.

[0024] FIG. 8 depicts a schematic electrical diagram of a multiple band gap light emitting diode, in accordance with some embodiments of the present disclosure.

[0025] FIGS. 9A-B depicts a schematic top view of semiconducting nanohole superlattices, in accordance with some embodiments of the present disclosure.

[0026] FIG. 10 depicts a schematic top view of a multiple band gap device comprising a nanohole superlattice, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] In some embodiments, graphite-based structures, e.g. graphene quantum dots, graphene nanoribbons (GNRs), graphene nanonetworks, graphene plasmonics and graphene super-lattices, exhibit many exceptional chemical, mechanical, electronic and optical properties, and are very desirable for use in electronic devices, composite materials, and energy generation and storage. Such graphite-based structures in general comprise a graphene layer, typically nanometers thick and having a characteristic dimension also in the nanometers range. For example, in order to obtain adequate band gaps for operation at room temperature, GNRs are required to have a width within a few nanometers due to the inverse relationship between the band gap and the width of the GNRs.

[0028] In some embodiments, various methods are provided for fabricating graphite- based structures while achieving desired size, specified geometries, and characterized electronic properties of the graphite-based structures. These methods include, but are not limited to, (1) the combination of e-beam lithography and oxygen plasma etching; (2) stripping of graphite that is sonochemically processed; and (3) bottom-up chemical synthesis, e.g., by cyclodehydrogenation of l,4-diiodo-2,3,5,6-tetraphenylbenzene6, or ΙΟ,ΙΟ'-dibromo- 9,9'-bianthryl, polyanthrylene oligomers self-assembled on Au(l 11), Ag(l 11) or silica substrates, to name a few examples.

[0029] In some embodiments, different pitch and duty cycle combinations in graphene devices are utilized to improve efficiency. In particular, in some embodiments, graphene sheets are stacked, with different pitch and critical dimensions, such that devices have multiple pass functionality. Similarly, in some embodiments, structures comprising multiple levels of graphene layers allow for more versatile and efficient band gap devices.

[0030] Embodiments of the present disclosure are described in the context of methods for fabricating thin films from layered materials and in the context of thin films made therefrom. In this specification and claims, layered materials refer to a material comprising a plurality of sheets, with each sheet having a substantially planar structure.

[0031] As used herein, the term "thin films" refers to a thin layer comprising one sheet (e.g, a sheet of graphene); it also refers to several, several tens, hundreds or thousands of such sheets. The thickness of the thin films can range from a nanometer to several micrometers, or to several tens of micrometers. Final thin films produced by some processes disclosed in this application have a thickness in nanometers, and preferably less than fifty nanometers. Similarly, as used herein, a "graphene layer" refers to several, several tens, several hundreds or several thousands of such sheets. As user herein a sheet is a sheet of graphene, which is a single sheet composed of sp²-hybridized carbon.

[0032] As used herein, the term "stacks" refers to one or more layers of a material

(e.g., one or more layers of graphene). Like "thin films," "stacks" can also refer to several, several tens, several hundreds or several thousands of layers of material. For example, a stack of graphene refers to one or more layers of graphene or graphene structures. As used herein, the term "graphene structures" is used interchangeably with "graphene." As used herein, the term "stacks" is interchangeable with the terms "graphene stacks" and "stacks of graphene."

[0033] As used herein, the terms "graphene based nanostructure" and "graphene nanostructure" are interchangeable and refer to any carbon based structure incorporating graphene. Examples of graphene based nanostructures include, but are not limited to, graphene nanoribbons, graphene nanonetworks, graphene poles/pillars, and graphene based nanohole superlattices.

[0034] As used herein, the term "level" refers to one or more graphene stacks for a given foundation layer or substrate. Thus, in some embodiments, a level of graphene contains multiple graphene stacks formed from a respective foundation layer or substrate. As sometimes used herein, "level" is shorthand for "graphene level" or "level of graphene."

[0035] As used herein, the term "substrate" refers to one layer or multiple layers. In some embodiments, a substrate is glass, Si, Si0₂, SiC, or another material. When referring to multiple layers, the term "substrate" is equivalent to and interchangeable with the term "substrate stack."

[0036] As used herein, the term "foundation material" refers to any material that is suitable for growing graphene. In some embodiments, foundation materials are catalytic metals, e.g., Pt, Au, Fe, Rh, Ti, Ir, Ru, Ni, or Cu. In some other embodiments, foundation materials are non-metal materials, such as Si, SiC, non-stoichiometric SiC (e.g., boron doped or otherwise), and other carbon enhanced materials. As used herein, the phrase "carbon enhanced" materials refers to any materials into which carbon has been added. [0037] As used herein, the term "backfilled" refers to forming or depositing a layer of material without leaving any air gaps in between stacks of a level. In some embodiments, "backfilling" means to fully backfill all gaps in between portions of a given layer.

[0038] Those of ordinary skill in the art will realize that the following detailed description of the present application is illustrative only and is not intended to be in any way limiting. Other embodiments of the present application will readily suggest themselves to such skilled persons having benefit of this disclosure. Reference will now be made in detail to implementations of the present application as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.

[0039] In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

[0040] FIG. 1A provides a flow chart of an exemplary method 100 for fabricating multilevel stacked graphene structures, in accordance with some embodiments of the present disclosure. In the disclosed flow chart, a first graphene level is formed on a substrate. A first interlayer is formed on the first graphene level. Then a second graphene level is formed on the first interlayer. In some embodiments, the methods or materials used to form the first and second graphene levels are different and, consequently, the characteristics (e.g., band gap, number of graphene sheets, etc.) of the first and second graphene levels differ. This is a highly advantageous architecture which gives rise to the ability to form any number of composite type graphene devices, including multi-functionality (each graphene level has a different function) and composite functionality (the combined properties of the graphene levels work to produce a common composite function). Generally speaking, each of the graphene levels can be formed by any of three general mechanisms (i) catalytic or precipitation from a metal, (ii) reverse epitaxial sublimation of silicon leaving carbon, and (iii) nucleation growth, typically on a non-metallic material. Now that an overview of FIG. 1 A, the details of each step will be described in more detail. Throughout this description it will be appreciated that in some embodiments a foundation layer is deposited and then used to form graphene. However, the disclosure is not so limited. As referenced above, the disclosure provides for any method of graphene formation. Methods that consume a portion of the substrate, such as reverse epitaxial sublimation of silicon leaving carbon often do not make use of a foundation layer. Thus, the use of such foundation layers herein should be considered optional, nonlimiting embodiments.

[0041] In method 100, a first foundation material is optionally deposited (102) onto a substrate, such as silicon or glass, thereby optionally forming a first foundation layer on the substrate. As discussed above, in some embodiments, the foundation material is a catalytic metal or any other material, as long as the material is conducive to growing or depositing graphene on the surface of the material. In some embodiments, the foundation material used is not a metal at all. For instance, in some embodiments, the foundation material comprises a carbon compound, such as silicon carbide. The foundation layer can be deposited onto the substrate via any standard microfabrication technology, e.g. sputtering, spin coating, or chemical vapor deposition.

[0042] In some embodiments, no foundation material is deposited. For instance, in some embodiments, the substrate itself serves as the source material for graphene growth {e.g., in some embodiments the substrate itself is the foundation material). As an example, in some embodiments the substrate is silicon carbide and graphene is formed by epitaxial growth on the silicon carbide. That is, the graphene is actually grown by heating the silicon and leaving graphene. See Sutter, 2009, Nature Materials 8, 171-172, which is hereby incorporated by reference in its entirety. In such embodiments, the graphene is grown on either the silicon-face or the carbon-face of the silicon-carbon substrate after an optional hydrogen etching. See Van Mil et al., Materials Science Forum 615, Trans Tech Publ 2009, pp. 211-214, which is hereby incorporated by reference in its entirety. In some embodiments, the graphene is grown epitaxially using a silicon carbide substrate and using near- atmoshopheric pressure with argon gas suppression. See Sutter, 2009, Nature Materials 8, 171-172, which is hereby incorporated by reference in its entirety. [0043] In some embodiments, the substrate is a transition metal substrate. Examples of transition metal substrates include, but are not limited to iridium (Ir), ruthenium (Ru), platinum (Pt), cobalt (Co), nickel (Ni), and palladium (Pd). In some embodiments the transition metal substrate is crystalline. For instance, in some embodiments the substrate is Ir(l 11), Ru(OOOl), Pt(l 11), Co(0001), Ni(l 11), or Pd(l 11). See for example, Coraux et al, 2008, Nano Lett 8, 565-570, which is hereby incorporated by reference in its entirety. In some embodiments where the substrate is a transition metal, graphene is grown by heating the transition metal substrate in the presence of carbon. Thus, in such embodiments, the carbon is considered the foundation material. In some embodiments, the transition metal substrate is overlayed on another substrate material, such as silicon, quartz, sapphire, or silica. In some embodiments, the transition metal substrate is overlayed on porous material, such as porous silicon, which is in turn overlayed on another layer, such as crystalline silicon. In such embodiments, the porous material acts as a barrier to prevent diffusion of the transition metal into the crystalline substrate.

[0044] In some embodiments, a first foundation material is not used, but rather molecular beam epitaxy is used to grow graphene directly onto a substrate. For instance, in some embodiments, the substrate is 6H-SiC, Si(l 11), or a transition metal (e.g., nickel) and a solid carbon block or glassy carbon filament is used to perform molecular beam epitaxy onto the substrate. See Moreau et al, 2010, physical status solidi (a) 207, 300-303; and hacley et al., 2009, Applied Physics Letters 94, 133114, Garcia, 2010, Solid State Communications 150, 809-811, each of which is hereby incorporated by reference herein.

[0045] In some embodiment chemical vapor deposition (CVD) is used to form graphene on a substrate. In some embodiments one or more gases, at least one of which is organic, are used to provide the carbon to the CVD process. Examples of gases, or combinations thereof, that can be used for such purposes include, but are not limited to, (i) a mixture of hydrogen and methane gas, (ii) diluted hydrocarbon gas, (iii) a combination of methane, hydrogen and argon, (iv) methane in an argon vault, (v) ethanol-saturated hydrogen gas, and (vi) ethene gas. Examples of substrates that can be used to form graphene using

CVD include, but are not limited to copper, nickel, cobalt, stainless steel, cobalt/magnesium oxide, and iridium. In some embodiments, this metal substrate is overlayed on another substrate material as discussed above in the context of the transition metals that are used to form graphene in the presence of carbon. In some embodiments an organic liquid, such as hexane, is used to provide the carbon to the CVD process. In some embodiments, plasma enhance CVD is used to form graphene on a substrate.

[0046] In embodiments that make use of a first foundation layer, after the first foundation layer has been formed, the graphene is then grown (104) onto or using the first foundation layer, thereby forming a first graphene level. In other embodiments, the first graphene level is formed using any of the graphene formation processes discussed above.

[0047] As mentioned above, in some embodiments, the first graphene level comprises

(106) one or more graphene stacks. In some implementations, a respective stack of graphene structures in the first graphene level includes (108) a first graphene based nanostructure. As mentioned above, in some embodiments, the first graphene based nanostructure is any carbon based structure incorporating graphene. In some embodiments, a graphene stack in the first graphene level comprises thin films for use in band gap devices. In some embodiments, the graphene layer can be formed using any standard deposition technique, e.g., chemical vapor deposition.

[0048] After the first graphene level has been formed, an interlay er is formed (110) on the first graphene level. In some embodiments, the interlayer is any layer of material deposited or formed on a graphene level to separate the graphene level from another graphene level. In some implementations, the interlayer is deposited or formed such that at least one air gap exists between two different graphene stacks. In some implementations, the interlayer is deposited or formed such that at least one air gap exists between two different portions of a given substrate or foundation layer, each portion corresponding to different graphene stack. Optionally, in some embodiments, the interlayer is deposited or formed such that the gaps in between different graphene stacks, or different portions of the substrate or foundation layer corresponding to different graphene stacks, are completely backfilled. Such air gap can be horizontally juxtaposed or vertically juxtaposed under a separation sheet as used in MEM devices. A benefit of such air gaps is for manipulation of the index of refraction in optical devices. By definition air has an index of refraction of 1. Therefore apparent indices of graphene devices can be changed by addition of an air gap into such devices. A difference in n (index of refraction) is also a boundary or interface for wavelength manipulation. Thin graphene is also a transparent material such that transmission as well as absorptive diffraction properties can be exploited. [0049] In some embodiments, the interlayer comprises glass, Si, SiC, Si0₂, S1₃N₄,

HfO, TiO, or any other semiconductor dielectrics. In other embodiments, the interlayer is a functional film, e.g. a transparent conductive oxide, such as ITO (indium tin oxide) or any other derivatives of such. Still in other embodiments, the interlayer is a conductive material, e.g., aluminum, tungsten, or platinum. As used herein, the term "functional" describes materials with qualities that serve one or more functions, e.g., conductivity. For example, an interlayer comprising indium tin oxide (ITO) can be used as a top lead in a solar device because it is transparent and conductive. Thus, sunlight would pass through the ITO interlayer, strike the graphene nanostructures in the graphene level directly underneath the interlayer, and cause electrons to be pulled out by the ITO interlayer, resulting in a current. Advantageous uses of the interlayer in the disclosed graphene devices include, but are not limited to implementation of wavelength band filters, concentrators, interconnects, device functionality such as line buses, drains for photo voltaic, isolation material (dielectrics), lead to batteries, work functions between the metals for band gap enhancement, leads to other elements in the electronics package such as transistor or resistors, ability to integrate Schottky barrier or diode, to name a few. Moreover, in devices in which the first and second graphene levels have different sheet thickness (i.e., different numbers of graphene sheets), the interlayer can be used to leverage the first and second graphene levels to produce a desired composite effect. For instance, with each of the first and second graphene levels having different critical dimensions as required by final functionality, the interlayer can be used to accomplish wavelength tuning and broadband coverage (including increased efficiency by cascading photon capture).

[0050] After the interlayer has been formed, a second foundation material is optionally deposited (112) onto the interlayer, thereby optionally forming a second foundation layer. In some embodiments, like the optional first foundation layer, the optional second foundation layer comprises any material suitable for growing or depositing graphene. In some embodiments, the second foundation material is the same material as the first foundation material; hence, in some embodiments, the second foundation layer is the same material as the first foundation layer. Optionally, in some embodiments, the second foundation material is different from the first foundation material. In some implementations, having different materials for different foundation layers allows for different functions or different methods of forming/depositing graphene. This is because the different foundation layer materials necessarily produce graphene levels having different physical properties. In some instances such differing graphene characteristics produces a desired composite characteristic for the device as a whole.

[0051] Once the optional second foundation layer has been formed, graphene is grown (114) onto or using the second foundation layer, thereby forming a second graphene level. As mentioned above, in some implementations, the method for growing or

forming/depositing graphene on the second foundation layer to form the second graphene level is a different method from that for forming the first graphene level. Alternatively, in some embodiments, the method for forming the second graphene level is the same as the method for forming the first graphene level.

[0052] As with the first graphene level, the second graphene level comprises (116) one or more graphene stacks. A respective graphene stack in the second graphene level includes (118) a second graphene based nanostructure. As described above, in some embodiments, the second graphene based nanostructure is any of a variety of graphene based nanostructures, such as nanoribbons or nanonetworks. As used herein, the term

nanonetworks include isolated arrays of pillars and/or cavities. Such pillars and cavities are used in antenna arrays, biomed applications sensing, evanescence, etc. The ability to stack these structures using the methods disclosed herein provides for a diverse and highly versatile array of structures. In some embodiments, the second graphene based nanostructure is different from the first graphene based nanostructure. In other embodiments, the second graphene based nanostructure is the same as the first graphene based nanostructure.

[0053] As set forth above, Fig. 1 A describes a method for fabricating multiple levels of graphene. Having multiple levels of graphene in a structure provides several advantages. One advantage is that each level of graphene can be specifically designed for a specific function. For example, one level can be designed to be responsive to a first wavelength range {e.g., one portion of the visible, infrared and/or ultraviolet spectrum), while another level is designed to be responsive to a second wavelength range {e.g. another portion of the visible, infrared and/or ultraviolet spectrum). By "responsive" it is that in varying respective embodiments, the level emits or absorbs light in the designated wavelength range. For example, in some embodiments a first level absorbs or emits blue light whereas a second level absorbs or emits red light. The ability to provide multiple functions in the same device allows for more versatile and efficient devices (such as solar devices), integration of broadband devices (EUV through IR), increased efficiency by the design of elements to capture maximum peak wavelength energy, generation of 'neighboring effects of different 'functionality of graphene (single and multiple layers), reduced resistivity by use of more sheets, band gap tune ability, work function definition, denser packing of device, shorter mean free paths, better capture of photons, cascade devices (sometimes called stair case devices) where photons or wavelengths are stripped from top to bottom, advantageous optical properties and electrical interactions (e.g., sensing and response to specific wavelength at each level). An important consideration for the above is integration of functionalities.

[0054] As described above, in some embodiments that make use of a foundation material for formation of both the first and second graphene level, the respective foundation layers can each be a catalytic metal material. More generally, the first and second graphene levels can generally be formed by the same or different processes selected from the group consisting of (i) catalytic or precipitation from a metal, (ii) reverse epitaxial sublimation of silicon leaving carbon, and (iii) nucleation growth (usually on a nonmetallic metal). In some embodiments, the foundation material layer is nanopatterned, thereby forming a nanotemplate before growing graphene. As discussed later and in more detail with regard to Fig. 2A, nanopatterning of the foundation material layer can be achieved using standard lithography techniques, including depositing a layer of photoresist, nanopatterning by shining light onto the photoresist layer over a mask, and chemical etching exposed areas. It should be noted that any technique that results in the catalytic nanotemplate, e.g. e-beam lithography, can be used for nanopatterning a foundation material.

[0055] Fig. IB provides a flow chart of an exemplary method 120 for fabricating stacked graphene layers, in accordance with some embodiments of the present disclosure. The difference between the method of Fig. IB and that of Fig. 1A is that the method of Fig. IB does not make use of an interlay er between respective graphene layers. Rather, the second graphene layer is formed directly on the first graphene layer.

[0056] As described above with respect to Figure 1 A, a stack refers to several, several tens, several hundreds or several thousands of layers of material. Thus, "stacked graphene layers" refers to several, several tens, several hundreds or several thousands of layers of graphene. As mentioned above, in some embodiments, each "graphene layer" comprises multiple sheets of graphene. As with method 100, method 120 begins with optionally depositing (122) a first foundation material onto a substrate thereby forming a first foundation layer. In some embodiments, operation 122 is analogous to operation 102 in Fig. 1 A. Next, graphene is grown (124) using the first foundation layer thereby forming a first graphene layer. Alternatively, the first foundation layer is not deposited and graphene is formed on the substrate by other means as discussed above in relation to Fig. 1 A. In some embodiments, operation 124 is analogous to operation 104 in Fig. 1A. The first graphene layer comprises (126) a first graphene based nanostructure. After the first graphene layer has been formed, a second foundation material is deposited (128) onto the first graphene layer thereby forming a foundation layer on the first graphene layer. Graphene is then grown (130) onto or using the second foundation layer thereby forming a second graphene layer. The second graphene layer comprises (132) a second graphene based nanostructure. In some embodiments, operations 128 and 130 are analogous to operations 112 and 114, respectively, in Fig. 1 A.

[0057] In some implementations, a respective "graphene layer," as used herein, comprises several, several tens, several hundreds or several thousands of layers of graphene. Thus, in some embodiments, a respective graphene layer is a graphene stack. Therefore, in some embodiments, a stack of graphene layers, with each graphene layer being a graphene stack, is a stack of graphene stacks. This allows for the possibility of generating multilayer graphene stacks comprising 50, 100, 300 or more layers. Similarly, in some embodiments, a respective graphene level, which comprises one or more graphene stacks, comprises stacked graphene layers as described with reference to Fig. IB. In such embodiments, a respective graphene level contains multiple foundation and graphene layers stacked on top of one another.

[0058] Fig. 1C provides a flow chart of another exemplary method 140 for fabricating stacked graphene layers, in accordance with some embodiments of the present disclosure. As with methods 100 and 120, method 140 begins with depositing (142) a first foundation material onto a substrate, thereby forming a first foundation layer. Unlike methods 100 and

120, method 140 uses a substrate that has been etched such that the substrate contains one or more recesses. Like nanopatterning, discussed above, etching the substrate can be achieved using standard lithography techniques, similar to the techniques discussed later with regard to

Fig. 2A. In some embodiments, depositing operation 142 includes depositing (144) the first foundation material onto the substrate such that recesses in the substrate are backfilled. As described above, in some embodiments, backfilling the substrate refers to depositing a material such that there is not an air gap in the recesses of the substrate. In other words, in some embodiments, backfilling the substrate refers to depositing a material such that the recesses of the substrate are filled. As with utilizing different interlayer materials described above, backfilling provides certain functions and advantages. For example, in some embodiments, fully backfilling the recesses of the substrate with a material facilitates subsequent etching of the material. In some embodiments, the backfill material changes or modifies the composite index of refraction of the resultant graphene device. In some embodiments, backfilling of recesses in a substrate is used to achieve electrical isolation. In some embodiments, backfilling of recesses in a substrate is used to protect against contamination and subsequent processing. In some embodiments, backfilling of recesses in a substrate is used for planarization and surface preparation while protecting the graphene. In some embodiments, backfilling of recesses in a substrate is used to tailor device functionality or provide contact isolation.

[0059] After forming the first foundation layer, the first foundation layer is etched

(146) such that only a thin first foundation layer is exposed in recesses in the substrate. As used herein, the term "thin" refers to any amount sufficient to produce desired amounts of graphene. In some embodiments, "thin" refers to the necessary amount needed to produce "thin films," as described above. As with etching the substrate, described earlier, etching the foundation layer can be achieved using standard lithography techniques, similar to the technique discussed later with regard to Fig. 2A.

[0060] Once the first foundation layer has been etched, graphene is grown (148) onto the thin first foundation layer thereby forming a first graphene layer in the recesses in the substrate. The first graphene layer comprises (150) a first graphene based nanostructure. Operation 148 is similar to operations 104 and 124, described above, except that the graphene is grown on or using the thin layer of graphene in the recesses of the substrate.

[0061] Next, a second foundation material is deposited (152) onto the first graphene layer, thereby forming a second foundation layer. As with operation 142, in some embodiments, operation 152 includes depositing into the recesses in the substrate the second foundation material (154). Similar to operation 146, the second foundation layer is then etched (156) such that only a thin second foundation layer is exposed in the recesses in the substrate. Graphene is then grown (158) onto the thin second foundation layer thereby forming a second graphene layer in the recesses in the substrate. As with the first graphene layer, the second graphene layer comprises (160) a second graphene based nanostructure. As with the first and second graphene based nanostructures described in Figs. 1 A and IB, in some embodiments, the first and second graphene based nanostructures are different nanostructures. In other embodiments, the first and second graphene based nanostructures are the same.

[0062] In some implementations, the substrate used in the present disclosure is glass, silicon, SiC, Si0₂, or SiC/Si. In some embodiments, the substrate is a solid substance in a form of a thin slice. In some embodiments, the substrate is planar. In some embodiments the substrate is flexible. In some embodiments the substrate is rigid. In various embodiments, the substrate is made of a dielectric material, a semiconducting material, a metallic material, or a combination of such materials. Exemplary dielectric materials include glass, silicon dioxide, neoceram, and sapphire. Exemplary semiconducting materials include silicon (Si), silicon carbide (SiC), germanium (Ge), boron nitride (BN), and molybdenum sulfide (MoS). Exemplary metallic materials comprise copper (Cu), nickel (Ni), platinum (Pt), gold (Au), cobalt (Co), ruthenium (Ru), palladium (Pd), titanium (Ti), silver (Ag), aluminum (Al), cadmium (Cd), iridium (Ir), combinations thereof, and alloys thereof. In some embodiments the substrate comprises Si, Si0₂, SiC, Cu, Ni, or other materials. In some embodiments, the substrate substantially comprises neoceram, borosilicate glass, germanium arsenide, a IV-V semiconductor material, a substantially metallic material, a high temperature glass, or a combination thereof. In some embodiments the substrate comprises a metal foil or a metal slug.

[0063] In some embodiments, the substrate substantially comprises Si0₂ glass, soda lime glass, lead glass, doped Si0₂, aluminosilicate glass, borosilicate glass, dichroic glass, germanium/semiconductor glass, glass ceramic, silicate/fused silica, soda lime glass, quartz or chalcogenide/sulphide glass, fluoride glass, a glass-based phenolic, flint glass, or cereated glass.

[0064] In some embodiments, the substrate is made of poly methyl methacrylate

(PMMA), polyethylene terephthalate (PET), polyvinyl alcohol (PVA), or cellulose acetate (CA). In some embodiments, the substrate is made of a urethane polymer, an acrylic polymer, a fluoropolymer, polybenzamidazole, polymide, polytetrafluoroethylene, polyetheretherketone, polyamide-imide, glass-based phenolic, polystyrene, cross-linked polystyrene, polyester, polycarbonate, polyethylene, polyethylene, acrylonitrile-butadiene- styrene, polytetrafluoro-ethylene, polymethacrylate, nylon 6,6, cellulose acetate butyrate, cellulose acetate, rigid vinyl, plasticized vinyl, or polypropylene.

[0065] In some embodiments, the substrate includes one layer. In alternative embodiments, the substrate includes a plurality of layers. In some embodiments, a substrate comprises a plurality of layers, each with a different material. In some embodiments, a layer of another substance is applied onto the substrate. In some embodiments, the substrate has crystallographic symmetry.

[0066] FIG. 2 A is a detailed graphical representation of an exemplary method for depositing graphene on a substrate and foundation material, in accordance with some embodiments of the present disclosure. Initial operation 200 demonstrates a clean substrate 220. In some embodiments, substrate 220 is a material that facilitates formation or deposition of one or more layers of a foundation material.

[0067] In operation 202, foundation material layer 230 is optionally deposited onto substrate 220 using, for example, any of the deposition methods described in Section 7 below, in order to form foundation material layer 230. Foundation material layer 230 is any material that facilitates graphene growth through deposition. In one embodiment, foundation material layer 230 is a catalytic metal, e.g., Cu. Operation 202 corresponds to operation 102 in Fig. 1 A.

[0068] In some embodiments, foundation material layer 230 is etched such that the graphene layer grown, via operation 104, comprises a plurality of graphene stacks 261, separated by the etching process. Operations 204-210 represent a detailed implementation, e.g. photolithography, of an example etching process used to etch foundation material layer 230. As discussed above, other lithography methods, such as e-beam lithography, direct write, block copolymer, to name a few, can also be used in other embodiments of the present disclosure. [0069] Operation 204 shows a layer of a photoresist 240 deposited onto the foundation material layer 230. Exemplary properties of photoresist 240 are described in Section 8.4 below.

[0070] After the resist layer has been applied, the density of the resist layer 240 is often insufficient to support later processing. Accordingly, in some embodiments of the present disclosure, a bake is used to densify the resist layer and drive off residual solvent. This bake is referred to as a softbake, prebake, or post-apply bake. Examples of such bake processes are described in Section 8.5.

[0071] After the foundation material layer 230 has been coated with resist layer 240, the next operation is alignment and exposure of the resist layer. Alignment and exposure is, as the name implies, a two-purpose photomasking operation. The first part of the alignment and exposure operation is the positioning or alignment of the required image on the material surface. The image is found on a mask. The second part is the encoding of the image in the resist layer from an exposing light or radiation source. In operation 206, a light (not shown) is shined onto photoresist layer 240 through the mask (not shown), exposing portions of the foundation material 230 in accordance with the features of the mask. That is, the mask is made such that the mask itself obstructs light, but the apertures in the mask allows light to shine through. In some embodiments, apertures in the mask are arranged in such a way as to form a nanopattern from which a nanotemplate will be formed. In some embodiments, the nanotemplate defines the structure of the graphene nanostructure grown during the graphene growing operations of the methods described above. More details on alignment and exposure of a mask are provided in Section 8.6, below.

[0072] After exposure through a mask, the pattern is coded as a latent image in resist as regions of exposed and unexposed resist. In some embodiments, the pattern is optionally developed in the resist by chemical dissolution of the unpolymerized resist regions. There are several methods in which a developer is applied to resist in order to develop the latent image. Such methods include, but are not limited to, immersion, spray development, and puddle development. Details on developing a resist layer are disclosed in Section 8.8, below. In some embodiments of the present disclosure, resist is optionally hard baked after it has been developed. The purpose of the hard bake is to achieve good adhesion of the resist layer to the underlying layer to be patterned. Details on hard baking a resist layer after chemical development are disclosed in Section 8.9, below.

[0073] In operation 208, the exposed portions of foundation material layer 230 are etched away using a plasma etcher. A plasma etcher uses energized ions to chemically dissolve away either exposed or unexposed portions of the resist layer. The etching process can be any etching process that etches away only the exposed foundation material layer. It is important to note that the etching process should not affect the patterned photoresist layer 240, the portions of foundation material layer 230 that are directly under and covered by photoresist layer 240, or the substrate 220. Section 8.10, below, provides exemplary etching techniques, including wet etching, plasma etching, ion beam etching, and reactive ion etching.

[0074] In operation 210, the remaining portions of the photoresist layer 240 are removed by any of a number of residual layer removal techniques. For example, in one embodiment of the present disclosure light (not shown) is once again shined onto photoresist layer 240, but this time without the mask, in order to remove the remaining portions of photoresist layer 240, thereby exposing a patterned foundation material layer 230. In some embodiments, the resist layer 240 is stripped off with a strong acid such as H₂SO₄ or an acidoxidant combination, such as H₂S0₄-Cr₂O3, attacking the resist but not the groove to yield the fully patterned structure. Additional residual layer removal techniques that can be applied in operation 210 are described in Section 8.11, below.

[0075] In operation 212, the foundation layer 230 is used to form one or more layers of graphene 250 (also referred to herein as "graphene layers 250"). Operation 212 corresponds to operation 104 of Fig. 1A. In some embodiments, the one or more layers of graphene 250 grown on foundation layer 230 form first graphene level 260, as depicted in Fig. 2A. As mentioned above, in some implementations, foundation layer 230 is nonexistent, and thus first graphene level 260 simply comprises one or more layers of graphene 250. As described above with reference to Fig. 1 A, in some embodiments, first graphene level 260 comprises one or more stacks 261 of graphene structures, also called graphene stacks 261, where a respective stack 261 includes a first graphene based nanostructure, e.g., nanoribbon 300 depicted in Fig. 3. The one or more layers of graphene 250 can be deposited in a variety of methods, e.g. chemical vapor deposition, some of which are described in Section 7 below. For instance, in some embodiments of operation 212, chemical vapor deposition as described for example in Section 7.1 below, is used to deposit carbon onto the foundation layer 230 to form one or more graphene layers 250. In some embodiments of operation 212, reduced pressure chemical vapor deposition as described for example in Section 7.2 below, is used to deposit carbon onto the foundation layer 230 to form graphene layers 250. In some embodiments of operation 212, any of the techniques described for example in any of Sections 7.3 through 7.21 below, is used to deposit carbon onto the foundation layer 230 to form graphene layers 250.

[0076] FIG. 2B is a detailed graphical representation of an exemplary method for forming multilevel stacked graphene structures, in accordance with some embodiments of the present disclosure. The method depicted in Fig. 2B is a continuation of the method depicted in Fig. 2A. Thus, the method begins with operation 212, as described with reference to Fig. 2A. In operation 214, first interlayer 270 is formed from a first interlayer material.

Operation 214 corresponds to operation 110 in Fig. 1A. As previously mentioned, in some embodiments, interlayer 270 is formed with one or more air gaps 231. As shown in Figure 2B, such air gaps 231 can be used to electrically isolate graphene stacks 261, alter the composite electrical properties of the device as a whole, or for other desired effects.

[0077] Operations 216 and 218 correspond to operations 112 and 114, respectively, of

Fig. 1 A. As depicted in Fig. 2B, second foundation layer 232 is already etched. In some embodiments, second foundation layer 232 is etched (although not shown) with the same processes depicted in operations 204-210 of Fig. 2A. In other embodiments, second foundation layer 232 is etched using different processes, e.g., e-beam lithography. Similarly, one or more graphene layers 252 of second graphene level 262 can be grown in the same manner as or in a different manner from graphene layers 250 of first graphene level 260. In operation 222, operations 214, 216 and 218 are repeated to form second interlayer 272, third foundation layer 234, and third graphene level 264 comprising one or more graphene layers 254. As mentioned above, graphene layers 250, 252, and 254 can comprise the same amount of graphene layers and the same graphene structures, all different numbers of layers and types of graphene structures, or a combination of the number of graphene layers and the types of graphene structures. [0078] In Fig. 2B, each graphene level, 260, 262, and 264 comprises one or more graphene stacks 261, 263, and 265, respectively. The example illustrated in Fig. 2B shows graphene stacks 261, 263, and 265 as having the same or similar dimensions. The example also shows the stacks in each level being aligned. However, in some embodiments, the number of stacks for each level varies, or the dimensions of a stack for a given level differs from the dimensions of a stack for another level, as illustrated in Figs. 2H-2J. Varying the dimensions of the stacks and the number of stacks per level allows for production of various devices having advantageous properties. That is the graphene stacks are tailored by any combination of number of layers, width, length, thickness, domain, impurities, edge conditions (chair/zigzag), contiguous nature, band gap, defects, etc., to achieve desired functionality. That is, such parameters are modified and tuned for the wavelength physical condition. In some embodiments, each graphene level {e.g., 260, 262, 264) has a different electromagnetic spectral response. The shorter the width of a graphene stack 261, 263, 265, the higher the band gap. The narrower the pitch of a graphene stack 261, 263, 265, the tighter the packing. The duty cycle of the pitch accounts for 'empty' or non productive space.

Theoretically, there are different ways to capture a 450nm wavelength (blue channel) it can be by a narrow ribbon, or multiple layers, or 'stripping' other wavelengths (Wave guide theory). There is also the case of redundancy, if one element (20 nm wide with 30 layers of graphene) can capture 20%, then five stacked layers of the same composition would have a theoretical capture of 100%. Efficiency calculations which also include transmission, opacity and diminishing power per layer can also be considered in order to design and optimize the physical characteristics of each graphene stack in each graphene level of the resultant device.

[0079] Fig. 2C is a detailed graphical representation of an exemplary method for forming multilevel stacked graphene structures having backfilled interlayers, in accordance with some embodiments of the present disclosure. Operations 215-221 are analogous to operations 214-222 of Fig. 2B, except that interlayers 271 and 273 fully backfill the recesses in between graphene stacks in graphene levels 260 and 262, respectively.

[0080] Figs. 2D and 2E illustrate an exemplary graphical representation of method

120 in Fig. IB, and thus further details of the operations of the method have already been discussed above with reference to Fig. IB. Fig. 2D is a detailed graphical representation of an exemplary method for forming stacked graphene layers without interlayers, in accordance with some embodiments of the present disclosure. As with the methods in Figs. 2B and 2C, the method in Fig. 2D starts with operation 212. Operation 212 corresponds with operations 122 and 124 of Fig. IB. In operation 224, a second foundation layer 232 is deposited on top of first graphene layer 250. Operation 224 already shows second foundation layer 232 in etched form. As with operations 216 an 217 in Figs. 2B and 2C, in some embodiments, second foundation layer 232 is etched (although not shown) with the same processes depicted in operations 204-210 of Fig. 2A. In operation 226, second graphene layer 252 is grown. In operation 228, third foundation layer 234 and third graphene layer 254 is added. In some embodiments, the foundation layer is entirely consumed during fabrication of the devices depicted in Figures 2D and 2E and thus, in such embodiments the respective graphene layers from each iteration of the graphene generation process are stacked directly on top of each other.

[0081] The method in Fig. 2D is similar to the methods in Figs. 2B and 2C, with slight differences. As with Figs. 2B and 2C, in some embodiments, at least one of graphene layers 250, 252, and 254 contain graphene nanostructures different from the graphene nanostructures contained in another graphene layer. In other embodiments, the graphene nanostructures contained in each layer is of the same type. One difference between the method in Fig. 2D and the methods in Figs. 2B and 2C is that interlayers are not utilized. Another difference is that although graphene layers 250, 252, and 254 are stacked upon one another, the combination of the three graphene layers can still be viewed as one stack. Thus, as depicted in Fig. 2D, stack 261 comprises all three graphene layers 250, 252, and 254. Similarly, although three separate graphene layers are stacked, the combination of all three can be referred to as a single graphene level 260. The significance of this being that in some embodiments, one or more stacks 261 of first graphene level 260 (or stacks 263 of second graphene level 262 or stacks 265 of third graphene level 264) each comprise a stack of multiple graphene layers, as illustrated in Fig. 2D.

[0082] Fig. 2E is a detailed graphical representation of another exemplary method for forming stacked graphene layers without interlayers, in accordance with some embodiments of the present disclosure. Fig. 2E is analogous to Fig. 2D, except that substrate 220 has been etched to form recesses 223. Thus, operations 280-288 will not be discussed in detail.

[0083] Figs. 2F-2G depict a detailed graphical representation of an exemplary method for forming stacked graphene layers in recesses of a substrate, in accordance with some embodiments of the present disclosure. Figs. 2F-2G illustrate an exemplary graphical representation of method 140 in Fig. 1C, and thus further details of the operations of the method have already been discussed above with reference to Fig. 1C. Like Fig. 2E, the method begins with substrate 220 etched to form recesses 223 within the substrate, as shown in operation 280. Next, foundation material is deposited (281) on substrate 220, fully backfilling recesses 223, forming first foundation layer 230. Next, foundation material 230 is etched (283), using any of the standard lithography processes described herein, to form a thin foundation layer 230 exposed only in recesses 223 of substrate 220. Graphene is grown (285) to form first graphene layer 250. Operations 287-291 are analogous to operations 281-285.

[0084] In some embodiments, the stacks of graphene layers depicted in Figs. 2D-2G correspond to graphene stacks 261 described above with reference to Figs. 2A-2C (except that the dimensions of the stack are limited to the dimensions of recesses 223, for Figs. 2F- 2G, or the dimensions in between recesses 223, for Fig. 2E). Thus, in some implementations, the products 294, 295, and 296 in Figs. 2D-2G can be used as substitutes for any graphene level 260, 262, or 264 described above with reference to Figs. 2A-2C. In embodiments where products 294, 295, and 296 substitute for second and third graphene levels 262, and

264, substrate 220 is substituted with interlayers 270 or 272.

[0085] Figs. 2H-2J depict detailed graphical representations of exemplary multilevel stacked graphene structures 297, 298, and 299, with variable dimensions and layouts, in accordance with some embodiments of the present disclosure. As mentioned above, one advantage of having multiple levels of graphene is the ability to design each level differently. Structure 297 of Fig. 2H, a variation of structure 292 in Fig. 2B, is an example where stacks

265, 263, and 261, of graphene levels 264, 262, and 260, vary in width across the different graphene levels. Structure 298 of Fig. 21 is a variation of structure 297, with the stacks of each level being arranged such that the stacks of each level are not vertically aligned with stacks from another level. Structure 299 of Fig. 2 J illustrates yet another variation of structure 297, with each level containing a different number of stacks.

[0086] Figure 2H represents an embodiment in which a center of each respective graphene stack in one graphene level aligns with a center of a corresponding graphene stack in another graphene level. Moreover, although not drawn, embodiments of the present disclosure encompass structures in which a leading edge 502 of each respective graphene stack in one graphene level aligns with a leading edge 502 of a corresponding graphene stack in another graphene level. Furthermore, although not drawn, embodiments of the present disclosure encompass structures in which a trailing edge of each respective graphene stack in one graphene level aligns with a trailing edge of a corresponding graphene stack in another graphene level.

[0087] Methods for producing multilayer and multilevel graphene structures have been described above. Examples of graphene nanostructures included in the multilayer and multilevel graphene structures, as well as examples of band gap devices that may incorporate the multilayer and multilevel graphene structures, will now be described.

[0088] Fig. 3 depicts a two-dimensional view of one layer of a graphene nanoribbon

(GNR) 300 in accordance with the prior art. GNR 300 comprises a thin strip of graphene, or an unrolled carbon nanotube. As is evident from Fig. 3, graphene comprises carbon atoms sp2-bonded to form a honeycomb like lattice. In Fig. 3, each of the plurality of vertices 302 represents a carbon atom. GNRs, such as GNR 300, can have two edge structures that characterize their electronic properties: armchair and zigzag. Edge 310 depicts the armchair edge structure, while edge 320 depicts the zigzag edge structure. More details about GNRs and their electronic properties can be found in Motohiko Ezawa's Peculiar Band Gap Structure of Graphene Nanoribbons, Physica Status Solidi (c) 4, No. 2, 489 (2007), which is hereby incorporated by reference herein in its entirety.

[0089] Fig. 4 illustrates an exemplary embodiment 400 of a multiple band gap device arranged on a substrate 102 in accordance with the present disclosure. Instead of arranging nanoribbons or stacks in one row, exemplary embodiment 400 comprises a plurality of rows, with each row having a first common lead 406 and a second common lead 408. Graphene structures 404-i and 404-j represent either a single ribbon or a stack of GNR 300. Graphene structures 404-i and 404-j are either identical or have different characteristics. Each row can be electrically connected in series or parallel for a desired output. As illustrated in Fig. 4, the layout of the ribbons can be assumed to be in parallel lines. However, for optical considerations the ribbons can also be laid down in an orthogonal arrangement for additive effects and non-additive areas. In one specific embodiment, solar cells for static tracking the complementary layers can be offset by a number of degrees with respect to each other (e.g., 30, 45, or 60 degrees). Some designs are also related to a radius of curvature for exposures (e.g., Fresnel lens configurations).

[0090] Fig. 5 illustrates an additional exemplary multiple band gap device 500 in accordance with an aspect of the present disclosure, where 504 represents either a single ribbon or a stack of GNR 300, and GNN 506 represents a nanohole superlattice or a vertical stack of multiple nanohole superlattices. Nanoribbons, nanohole superlattices or stacks (formed with either nanoribbons or nanohole superlattices) in exemplary embodiment 500 are nanopatterned and arranged into a plurality of clusters (000-1 , 000-2, . .. , 000-N) on substrate 102. Each cluster is spatially separated from each other, and has its own first lead 510 and second lead 512. With respect to structure and function, 000-1 , 000-2, 000-N can represent embodiments for either nanoribbons or nanoholes superlattices. Exemplary embodiment 500 is a conglomerate that comprises a plurality of multiple band gap devices. Although not illustrated, similar arrangements of pillars or cavities are encompassed in the present disclosure.

[0091] In some embodiments, cluster 000-i has the same structure as cluster 000-j. In other embodiments, cluster 000-i has the same structure as cluster 000-j, but both of them are different from cluster 000-k. In yet other embodiments, cluster 000-i has the same structure as cluster 000-j, but nanoribbons or stacks of cluster 000-i have different characteristics than nanoribbons or stacks of cluster 000-j. In some embodiments, cluster 000-i is a device comprising a plurality of lateral spaced nanoribbons, whereas in other embodiments, cluster 000-i is a device comprising a plurality of vertically stacked nanoribbons. In some embodiments, cluster 000-i is a device comprising a plurality of lateral spaced nanohole superlattices, whereas in other embodiments, cluster 000-i is a device comprising a plurality of vertically stacked nanohole superlattices. In some embodiments, cluster 000-i is a device comprising one single nanohole superlattice, whereas in other embodiments, cluster 000-i is a device comprising one single stack formed by a plurality of vertically stacked nanohole superlattices.

[0092] In some embodiments, the plurality of multiple band gap devices, or clusters

000-1 , 000-2, . .. , 000-N, is geometrically arranged in a planar array, preferably with each cluster parallel or near parallel to adjacent clusters. In some embodiments, however, some clusters are displaced or tilted as shown in Fig. 5. In other embodiments, one cluster is placed on top of another cluster in the plurality of clusters. Depending on the desired application, the plurality of multiple band gap devices, or clusters 000-1, 000-2, ..., 000-N, are electrically connected in parallel, in series, or in combination of parallel and series.

[0093] In general, each device in plurality of multiple band gap devices or each cluster in the plurality of clusters has a width that is between 1 μιη to 10 mm and a length that is between 1 μιη to 10 mm. In some embodiments, each cluster in the plurality of clusters has a width that is between 10 μιη to 1 mm and a length that is between 10 μιη to 1 mm. In some embodiments, each cluster in the plurality of clusters has a width that is between 50 μιη to 500 μιη and a length that is between 50 μιη to 500 μιη.

[0094] In some instances, exemplary embodiments 400 and 500 respectively depicted in Figs. 4 and 5 comprise an optical splitter and can be used, for example, as photovoltaic devices or photodetectors.

[0095] Figs. 6-8 provide exemplary schematic electric diagrams for a multiple band gap device in accordance with the present disclosure. In Figs. 6-8, element 602 represents all the embodiments previously described, such as embodiments 400 and 500, and equivalents within the scope of the present disclosure. Through the first lead 604 and the second lead 606, embodiment 602 can be electrically connected to a selective external circuit, creating a multiple band gap photovoltaic device 600 (Fig. 6), a multiple band gap photodetector 700 (Fig. 7), or a multiple band gap LED 900 (Fig. 8).

[0096] A multiple band gap photovoltaic device 600 is created by connecting embodiment 602 to an external load, a schematic electrical diagram of which is illustrated in Fig. 7. Represented by the resistor 608, the load is an electricity generator, a water heater, a battery, or other appliances. In some embodiments, the load is an electrical grid when embodiment 602 is connected to a main electrical grid. In some embodiments, upon receiving incident sunlight, photovoltaic device 700 produces power at 50 W/m² or higher without a solar concentrator. In some embodiments, photovoltaic device 700 includes a solar concentrator and the power output is higher. For example, using a lOOx solar concentrator, a power of 5000 W/m2 is achieved in some embodiments.

[0097] Connecting embodiment 602 to an electrometer produces a multiple band gap photodetector 700, a schematic electrical diagram of which is illustrated in Fig. 7. The electrometer is any type of electrometer, including vibrating reed electrometers, valve electrometers, and solid-state electrometers, and measures either electric charge or electrical potential difference. By tuning and controlling the band gaps of embodiment 602, photodetector 700 is designed to measure infrared radiation, visible light, and/or ultraviolet radiation, in wavelength ranges anywhere between 10 nm and 100 μιη.

[0098] When embodiment 602 is connected to an external current, such as a battery, a multiple band gap LED 800 is generated. Fig. 8 provides a schematic electrical diagram of a multiple band LED 900 in accordance with the present disclosure. By tuning and controlling the band gaps of embodiment 602, the multiple band gap LED 800 can emit light in a wide wavelength spectrum in the range of between 10 nm to 100 μιη. In some embodiments, the multiple band LED 900 emits a hybrid light, such as a white light.

[0099] In addition, present photovoltaic device 600, photodetector 700, and LED 800 can be integrated into more complex electronic devices to facilitate desired applications. For instance, in some embodiments the photovoltaic device 600 is combined with the LED 800 for a variety of self-sustained solar lighting applications examples of which include outdoor lighting at night. During the daytime, the photovoltaic device 600 absorbs solar energy, converts solar energy into electricity and stores electricity, for example, in a battery. At night, stored electricity powers the LED 800 causing it to light.

[00100] In some embodiments the graphene based nanostructures in one more graphene levels is a semiconducting nanohole superlattice. Figs. 9A and 9B depict a semiconducting nanohole superlattice 930 with triangular nanoholes 932 and with rectangular nanoholes 934 respectively. Other shapes of nanoholes or combination of different shapes of nanoholes can be patterned. As used herein the term "semiconducting nanohole superlattice" refers to graphene having an array of nanoholes defined therein. In some embodiments, the nanohole superlattice comprises one sheet of graphene or multiple vertically stacked sheets of graphene. The array of nanoholes can be produced using any suitable fabrication known in the art. For example, in some embodiments, a nanohole superlattice structure is patterned with one or more nanohole arrays using conventional photolithography techniques.

Effectively, a nanohole superlattice is a two-dimensional network of crossing nanoribbons, in which the size, shape, and density of the nanoholes define the shape and dimensions of the nanoribbons. Thus, nanohole superlattices have similar characteristics to nanoribbons. For example, while not intending to be bound by any particular theory, the tight-binding model indicates that band gaps of graphene nanohole superlattices increase linearly with the product of nanohole size and density. This is because the width of a nanoribbon in the two- dimensional network of crossing nanoribbons can be decreased by either increasing the sizes of nanoholes or increasing the number of nanoholes in one fixed unit. Other similar characteristics include larger mean free paths for charge carriers in nanohole superlattices and dependence or weak dependence of the work functions of nanohole superlattices on the size, shape, density of the nanoholes. These characteristics make it possible to design a device with nanohole superlattices in a similar way as nanoribbons. In addition to having similar characteristics, a nanohole superlattice in general has several advantages compared to an individual nanoribbon. For instance, a nanohole superlattice usually provides more surface area for absorbing or omitting light, and hence potentially higher efficiency for any device comprising such a nanohole superlattice. Furthermore, a nanohole superlattice tolerates defects better than an individual nanoribbon.

Multiple Band Gap Devices

[00101] Fig. 10 depicts a schematic top view of a multiple band gap device comprising a nanohole superlattice 930 in accordance with an aspect of the present disclosure. As in embodiments comprising nanoribbons, the nanohole superlattice is disposed on a substrate 102. There are also two leads, the first lead 1006 and the second lead 1008, electrically contact two opposite edges of the nanohole superlattice. Patterned within the nanohole superlattice is an array of rectangular nanoholes 1034. By way of illustration, rectangular nanoholes 1034 depicted in FIG. 10 have different sizes and spacing, rendering the analogous nanoribbons within the nanohole superlattice 930 having different widths. Thus the nanohole superlattice 930 is expected to have multiple band gaps. Depending on the application and the desired band gap range, an array of nanoholes having different shapes, sizes, densities, or any combination thereof is used, or is distributed differently within the nanohole superlattice. In addition, in some embodiments, the nanohole superlattice is doped, in bulk or on edges, with different dopants or concentrations, to further tune the band gap range. Other parameters, such as the thickness of the nanohole superlattice, are varied as well to modify the band gap in some embodiments of the present disclosure.

[00102] In some embodiments, the one or more nanohole superlattices are arranged vertically by stacking one on top of another or arranged laterally by placing one next to another side by side. In some embodiments, the architecture of devices having nanohole superlattices is essentially the same as those described above when using nanoribbons, whether it is vertically stacked or lateral spaced.

Advantages

[00103] The present disclosure provides for the fabrication of any number of graphene levels on a substrate. In some instances, the graphene levels are interspersed with interlayers. Within each graphene level there exist graphene stacks that form graphene based

nanostructures. In some embodiments, the graphene stacks in any given graphene level generally have the same number of sheets of graphene, although this is not an absolute requirement. In some embodiments, the graphene stacks in one graphene level differ in some physical property from the graphene stacks in another graphene level. This advantageously provides for the ability to generation a wide array of devices, include devices in which the graphene stacks in one graphene level perform one function (because of some physical property common to these graphene stacks) while the graphene stacks in another graphene level perform another function (because of some physical property common to these other graphene stacks). Numerous examples of the wide variety of physical properties that may be shared or may be varied amongst the graphene stacks and among the graphene levels have been disclosed herein. This diversity gives rise to the ability to design a wide variety of composite devices as disclosed herein. Moreover, this is all accomplished without any requirement to post process graphene once the graphene has been formed, which is a notoriously difficult process particularly in the nanoscale dimensions some of the disclosed dimension have.

Deposition Methods

[00104] The following subsections describe individual fabrication techniques that can be used to deposit layers of material, e.g. foundation material layer 230, interlayer 270, photoresist 240, or graphene 250, hereinafter referred to collectively as "deposit materials," in accordance with embodiments of the present disclosure.

7.1 Chemical vapor deposition [00105] In some embodiments, one or more layers of the deposit materials are deposited by chemical vapor deposition. In chemical vapor deposition (CVD), the constituents of a vapor phase, often diluted with an inert carrier gas, react at a hot surface (typically higher than 190°C) to deposit a solid film. Generally, chemical vapor deposition reactions require the addition of energy to the system, such as heating the chamber or the wafer. For more information on chemical vapor deposition, exemplary devices used to perform chemical vapor deposition, and process conditions are used to perform chemical vapor deposition of silicon nitride, see Van Zant, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, pp. 363-393; and Madou, Fundamentals of Micro fabrication, Second Edition, 2002, pp. 144-154, CRC Press, each of which are hereby incorporated by reference herein in their entireties.

7.2 Reduced pressure chemical vapor deposition

[00106] In some embodiments, one or more layers of the deposit materials are deposited by reduced pressure chemical vapor deposition (RPCVD). RPCVD is typically performed at below 10 Pa and at temperatures in the range of (550°C - 600°C). The low pressure used in RPCVD results in a large diffusion coefficient, which leads to growth of a layer that is limited by the rate of surface reactions rather than the rate of mass transfer to the substrate. In RPCVD, reactants can typically be used without dilution. RPCVD is performed, for example, in some embodiments, in a horizontal tube hot wall reactor.

7.3 Low pressure chemical vapor deposition

[00107] In some embodiments, one or more layers of the deposit materials are deposited by low pressure chemical vapor deposition (LPCVD) or very low pressure CVD. LPCVD is typically performed at below 1 Pa.

7.4 Atmospheric chemical vapor deposition

[00108] In some embodiments, one or more layers of the deposit materials are deposited by atmospheric to slightly reduced pressure chemical vapor deposition.

Atmospheric pressure to slightly reduced pressure CVD (APCVD) is used, for example, to grow APCVD is a relatively simplistic process that has the advantage of producing layers at high deposition rates and low temperatures (350°C - 400°C).

7.5 Plasma enhanced chemical vapor deposition [00109] In some embodiments, one or more layers of the deposit materials are deposited by plasma enhanced (plasma assisted) chemical vapor deposition (PECVD).

PECVD systems feature a parallel plate chamber operated at a low pressure (e.g., 2-5 Torr) and low temperature (300°C - 400°C). A radio-frequency-induced glow discharge, or other plasma source is used to induce a plasma field in the deposition gas. PECVD systems that are used include, but are not limited to, horizontal vertical flow PECVD, barrel radiant-heated PECVD, and horizontal-tube PECVD. In some embodiments, remote plasma CVD

(RPCVD) is used. Remote plasma CVD is described, for example, in United States Patent No. 6,458,715 to Sano et al, which is hereby incorporated by reference in its entirety.

7.6 Anodization

[00110] In some embodiments, one or more layers of the deposit materials are deposited by anodization. Anodization is an oxidation process performed in an electrolytic cell. The material to be anodized becomes the anode (+) while a noble metal is the cathode (-). Depending on the solubility of the anodic reaction products, an insoluble layer (e.g., an oxide) results. If the primary oxidizing agent is water, the resulting oxides generally are porous, whereas organic electrolytes lead to very dense oxides providing excellent passivation. See, e.g., Madou et al, 1982, J. Electrochem. Soc. 129, pp. 2749-2752, which is hereby incorporated by reference in its entirety.

7.7 Sol-gel deposition techniques

[00111] In some embodiments, one or more layers of the deposit materials are deposited by a sol-gel process. In a sol-gel process solid particles, chemical precursors, in a colloidal suspension in a liquid (a sol) forms a gelatinous network (a gel). Upon removal of the solvent by heating a glass or ceramic layer. Both sol and gel formation are

low-temperature processes. For sol formation, an appropriate chemical precursor is dissolved in a liquid, for example, tetraethylsiloxane (TEOS) in water. The sol is then brought to its gel-point, that is, the point in the phase diagram where the sol abruptly changes from a viscous liquid to a gelatinous, polymerized network. In the gel state the material is shaped (e.g., a fiber or a lens) or applied onto a substrate by spinning, dipping, or spraying. In the case of TEOS, a silica gel is formed by hydrolysis and condensation using hydrochloric acid as the catalyst. Drying and sintering at temperatures between 200°C to 600°C transforms the gel into a glass and ultimately into silicon dioxide. [00112] In the semiconductor industry the sol-gel method described is often used to deposit silicon dioxide. The method is known as the Spin-On Glass method (SOG). Spin-On Glass materials have been widely used as a diffusion source or a planarizing dielectric or multilevel metalization schemes in the fabrication of nowadays integrated circuits. SOGs are in general Si-0 network polymers in organic solvents, and prepared through the hydrolysis- condensation reaction that implied the sol-gel technology. SOG materials can be divided into three groups: 1) silicate based compounds, 2) organosilicon compounds and 3) dopant- organic compounds. More information on SOG can be found, for example, in Nguyen Nhu Toan, Spin-On Glass Materials and Applications in Advanced IC Technologies, 1999, which is hereby incorporated herein by reference in its entirety.

7.8 Plasma spraying techniques

[00113] In some embodiments, one or more layers of the deposit materials are deposited by a plasma spraying process. With plasma spraying, almost any material can be coated on many types of substrates. Plasma spraying is a particle deposition method.

Particles, a few microns to 100 microns in diameter, are transported from source to substrate. In plasma spraying, a high-intensity plasma arc is operated between a sticktype cathode and a nozzle-shaped water-cooled anode. Plasma gas, pneumatically fed along the cathode, is heated by the arc to plasma temperatures, leaving the anode nozzle as a plasma jet or plasma flame. Argon and mixtures of argon with other noble (He) or molecular gases (H₂, N₂, 0₂, etc.) are frequently used for plasma spraying. Fine powder suspended in a carrier gas is injected into the plasma jet where the particles are accelerated and heated. The plasma jet reaches temperatures of 20,000 K and velocities up to 1000 ms^"1 in some embodiments. The temperature of the particle surface is lower than the plasma temperature, and the dwelling time in the plasma gas is very short. The lower surface temperature and short duration prevent the spray particles from being vaporized in the gas plasma. The particles in the plasma assume a negative charge, owing to the different thermal velocities of electrons and ions. As the molten particles splatter with high velocities onto a substrate, they spread, freeze, and form a more or less dense coating, typically forming a good bond with the substrate. Plasma spraying equipment is available from Sulzer Metco (Winterthur

Switzerland). For more information on plasma spraying, see, for example, Madou,

Fundamentals of Micro fabrication, Second Edition, 2002, pp. 157-159, CRC Press, which is hereby incorporated by reference in its entirety. 7.9 Ink jet printing

[00114] In some embodiments, one or more layers of the deposit materials are deposited by ink-jet printing. Ink-jet printing is based on the same principles of commercial ink-jet printing. The ink-jet nozzle is connected to a reservoir filled with the chemical solution and placed above a computer-controlled x-y stage. The target object is placed on the x-y stage and, under computer control, liquid drops (e.g., 50 microns in diameter) are expelled through the nozzle onto a well-defined place on the object. Different nozzles print different spots in parallel. In one embodiment of the present disclosure, a bubble jet, with drops as small as a few picoliters, is used to form a layer of a deposit material. In another embodiment, a thermal ink jet (Hewlett Packard, Palo Alto, California) is used to form a layer of a deposit material. In a thermal ink jet, resistors are used to rapidly heat a thin layer of liquid ink. A superheated vapor explosion vaporizes a tiny fraction of the ink to form an expanding bubble that ejects a drop of ink from the ink cartridge onto the substrate. In still another embodiment of the present disclosure, a piezoelectric ink-jet head is used for ink-jet printing. A piezoelectric ink-jet head includes a reservoir with an inlet port and a nozzle at the other end. One wall of the reservoir consists of a thin diaphragm with an attached piezoelectric crystal. When voltage is applied to the crystal, it contracts laterally, thus deflecting the diaphragm and ejecting a small drop of fluid from the nozzle. The reservoir then refills via capillary action through the inlet. One, and only one, drop is ejected for each voltage pulse applied to the crystal, thus allowing complete control over the when a drop is ejected. In yet another embodiment of the present disclosure, an epoxy delivery system is used to deposit a layer of a device. An example of an epoxy delivery system is the Ivek Digispense 2000 (Ivek Corporation, North Springfield, Vermont). For more information on jet spraying, see, for example, Madou, Fundamentals of Microfabrication, Second Edition, 2002, pp. 164-167, CRC Press, which is hereby incorporated by reference herein in its entirety.

7.10 Vacuum evaporation

[00115] In one embodiment of the present disclosure, one or more layers of the deposit materials are deposited by vacuum evaporation. Vacuum evaporation takes place inside an evacuated chamber. The chamber can be, for example, a quartz bell jar or a stainless steel enclosure. Inside the chamber is a mechanism that evaporates the metal source, a wafer holder, a shutter, thickness and rate monitors, and heaters. The chamber is connected to a vacuum pump. There are any number of different ways in which the metal is evaporated within the chamber, including filament evaporation, E-beam gun evaporation, and hot plate evaporation. See, for example, Van Zant, Microchip Fabrication, Fourth Edition, McGraw- Hill, New York, 2000, pp. 407-411, which is hereby incorporated by reference herein in its entirety.

7.11 Sputter deposition / physical vapor deposition

[00116] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by sputtering. Sputtering, like evaporation, takes place in a vacuum. However, it is a physical not a chemical process (evaporation is a chemical process), and is referred to as physical vapor deposition. Inside the vacuum chamber is a slab, called a target, of the desired film material. The target is electrically grounded. An inert gas such as argon is introduced into the chamber and is ionized to a positive charge. The positively charged argon atoms are attracted to the grounded target and accelerate toward it.

[00117] During the acceleration they gain momentum, and strike the target, causing target atoms to scatter. That is, the argon atoms "knock off atoms and molecules from the target into the chamber. The sputtered atoms or molecules scatter in the chamber with some coming to rest on the wafer. A principal feature of a sputtering process is that the target material is deposited on the wafer with chemical or compositional change. In some embodiments of the present disclosure, direct current (DC) diode sputtering, radio frequency (RF) diode sputtering, triode sputtering, DC magnetron sputtering or RF magnetron sputtering is used. See, for example, Van Zant, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, pp. 411-415; United States Patent 5,203,977; United States Patent 5,486,277; and United States Patent 5,742,471, each of which is hereby incorporated by reference herein in its entirety.

[00118] RF diode sputtering is a vacuum coating process where an electrically isolated cathode is mounted in a chamber that can be evacuated and partially filled with an inert gas. If the cathode material is an electrical conductor, a direct-current high-voltage power supply is used to apply the high voltage potential. If the cathode is an electrical insulator, the polarity of the electrodes is reversed at very high frequencies to prevent the formation of a positive charge on the cathode that would stop the ion bombardment process. Since the electrode polarity is reversed at a radio frequency, this process is referred to as 133 sputtering. Magnetron sputtering is different form of sputtering. Magnetron sputtering uses a magnetic field to trap electrons in a region near the target surface thus creating a higher probability of ionizing a gas atom. The high density of ions created near the target surface causes material to be removed many times faster than in diode sputtering. The magnetron effect is created by an array of permanent magnets included within the cathode assembly that produce a magnetic field normal to the electric field.

7.12 Collimated sputtering

[00119] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by collimated sputtering. Collimated sputtering is a sputtering process where the arrival of metal occurs at an angel normal to the wafer surface. The metal is collimated by a thick honeycomb grid that effectively blocks off angle metal atoms in some embodiments. Alternatively, ionizing the metal atoms and attracting them towards the wafer collimates the metal. Collimated sputtering improves filling of high aspect ratio contacts.

7.13 Laser ablated deposition

[00120] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by laser ablated deposition. In one form of laser ablated deposition, a rotating cylindrical target surface is provided for the laser ablation process. The target is mounted in a vacuum chamber so that it is rotated about the longitudinal axis of the cylindrical surface target and simultaneously translated along the longitudinal axis. A laser beam is focused by a cylindrical lens onto the target surface along a line that is at an angle with respect to the longitudinal axis to spread a plume of ablated material over a radial arc. The plume is spread in the longitudinal direction by providing a concave or convex lateral target surface. The angle of incidence of the focused laser beam is other than normal to the target surface to provide a glancing geometry in some embodiments. Simultaneous rotation about and translation along the longitudinal axis produce a smooth and even ablation of the entire cylindrical target surface and a steady evaporation plume. Maintaining a smooth target surface is useful in reducing undesirable splashing of particulates during the laser ablation process and thereby depositing high quality thin films. See, for example, United States Patent Number 5,049,405, which is hereby incorporated by reference herein in its entirety.

7.14 Molecular beam deposition [00121] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by molecular beam deposition. Molecular beam deposition is a method of growing films, under vacuum conditions, by directing one or more molecular beams at a substrate. In some instances, molecular beam deposition involves epitaxial film growth on single crystal substrates by a process that typically involves either the reaction of one or more molecular beams with the substrate or the deposition on the substrate of the beam particles. The term "molecular beam" refers to beams of monoatomic species as well as polyatomic species. The term molecular beam deposition includes both epitaxial growth and nonepitaxial growth processes. Molecular beam deposition is a variation of simple vacuum evaporation. However, molecular beam deposition offers better control over the species incident on the substrate than does vacuum evaporation. Good control over the incident species, coupled with the slow growth rates that are possible, permits the growth of thin layers having compositions (including dopant concentrations) that are precisely defined. Compositional control is aided by the fact that growth is generally at relatively low substrate temperatures, as compared to other growth techniques such as liquid phase epitaxy or chemical vapor deposition, and diffusion processes are very slow.

[00122] Essentially arbitrary layer compositions and doping profiles are obtained with precisely controlled layer thickness. In fact, layers as thin as a monolayer are grown by MBE. Furthermore, the relatively low growth temperature permits growth of materials and use of substrate materials that could not be used with higher temperature growth techniques. See for example, United States Patent 4,681,773, which is hereby incorporated by reference herein in its entirety.

7.15 Ionized physical vapor deposition

[00123] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by ionized physical vapor deposition (I-PVD), also known as ionized metal plasma (IMP). In I-PVD, metal atoms are ionized in an intense plasma. Once ionized, the metal is directed by electric fields perpendicular to the wafer surface. Metal atoms are introduced into the plasma by sputtering from the target. A high density plasma is generated in the central volume of the reactor by an inductively coupled plasma (ICP) source.

This electron density is sufficient to ionize approximately 80% of the metal atoms incident at the wafer surface. The ions from the plasma are accelerated and collimated at the surface of the wafer by a plasma sheath. The sheath is a region of intense electric field that is directed toward the wafer surface. The field strength is controlled by applying a radio frequency bias.

7.16 Ion beam deposition

[00124] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by ion beam deposition (IBD). IBD uses an energetic, broad beam ion source carefully focused on a grounded metallic or dielectric sputtering target. Material sputtered from the target deposits on a nearby substrate to create a film. Most applications also use a second ion source, termed an ion assist source (IAD), which is directed at the substrate to deliver energetic noble or reactive ions at the surface of the growing film. The ion sources are "gridded" ion sources and are typically neutralized with an independent electron source. IBD processing yields excellent control and repeatability of film thickness and properties. Process pressures in IBD systems are approximately 10^~4 Torr. Hence, there is very little scattering of either ions delivered by the ion sources or material sputtered from the target of the surface. Compared to sputter deposition using magnetron or diode systems, sputter deposition by IBD is highly directional and more energetic. In combination with a substrate fixture that rotates and changes angle, IBD systems deliver a broad range of control over sidewall coatings, trench filling and liftoff profiles.

7.17 Atomic layer deposition

[00125] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by atomic layer deposition. Atomic layer deposition is also known as atomic layer epitaxy, sequential layer deposition, and pulsed-gas chemical vapor deposition. Atomic layer deposition involves use of a precursor based on self-limiting surface reactions. Generally, an object is exposed to a first species that deposits as a monolayer on the object. Then, the monolayer is exposed to a second species to form a fully reacted layer plus gaseous byproducts. The process is typically repeated until a desired thickness is achieved. Atomic layer deposition and various methods to carry out the same are described in United States Patent Number 4,058,430 to Suntola et al., entitled "Method for

Producing Compound Thin Films," United States Patent Number 4,413,022 to Suntola et al., entitled "Method for Performing Growth of Compound Thin Films," to Ylilammi, and

George et al., 1996, J. Phys. Chem. 100, pp. 13121-13131, each of which is hereby incorporated by reference herein in its entirety. Atomic layer deposition has also been described as a chemical vapor deposition operation performed under controlled conditions that cause the deposition to be self-limiting to yield deposition of, at most, a monolayer. The deposition of a monolayer provides precise control of film thickness and improved compound material layer uniformity. Atomic layer deposition is performed using equipment such as the Endura Integrated Cu Barrier/Seed system (Applied Materials, Santa Clara, California).

7.18 Hot filament chemical vapor deposition

[00126] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by hot filament chemical vapor deposition (HFCVD). In HFCVD, reactant gases are flowed over a heated filament to form precursor species that subsequently impinge on the substrate surface, resulting in the deposition of high quality films. HFCVD has been used to grow a wide variety of films, including diamond, boron nitride, aluminum nitride, titanium nitride, boron carbide, as well as amorphous silicon nitride. See, for example, Deshpande et al., 1995, J. Appl. Phys. 77, pp. 6534-6541, which is hereby incorporated by reference herein in its entirety.

7.19 Screen printing

[00127] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by a screen printing (also known as silk-screening) process. A paste or ink is pressed onto portions of an underlying structure through openings in the emulsion on a screen. See, for example, Lambrechts and Sansen, Biosensors:

Microelectrochemical Devices, The Institute of Physics Publishing, Philadelphia, 1992, which is hereby incorporated by reference in its entirety. The paste consists of a mixture of the material of interest, an organic binder, and a solvent. The organic binder determines the flow properties of the paste. The bonding agent provides adhesion of particles to one another and to the substrate. The active particles make the ink a conductor, a resistor, or an insulator. The lithographic pattern in the screen emulsion is transferred onto portions of the underlying structure by forcing the paste through the mask openings with a squeegee. In a first step, paste is put down on the screen. Then the squeegee lowers and pushes the screen onto the substrate, forcing the paste through openings in the screen during its horizontal motion.

During the last step, the screen snaps back, the thick film paste that adheres between the screening frame and the substrate shears, and the printed pattern is formed on the substrate. The resolution of the process depends on the openings in the screen and the nature of the paste. With a 325-mesh screen {i.e., 325 wires per inch or 40 μΜ holes) and a typical paste, a lateral resolution of ΙΟΟμΜ can be obtained. [00128] For difficult-to-print pastes, a shadow mask, such as a thin metal foil with openings, complements the process. However, the resolution of this method is inferior (>500 μΜ). After printing, the wet films are allowed to settle for a period of time (e.g., fifteen minutes) to flatten the surface while drying. This removes the solvents from the paste.

Subsequent firing burns off the organic binder, metallic particles are reduced or oxidized, and glass particles are sintered. Typical temperatures range from 500°C to 1000°C. After firing, the thickness of the resulting layer ranges from ΙΟμΜ to 50μΜ. One silk-screening setup is the DEK 4265 (Universal Instrument Corporation, Binghamton, New York). Commercially available inks (pastes) that can be used in the screen printing include conductive (e.g., Au, Pt, Ag/Pd, etc.), resistive (e.g., Ru0₂, Ir0₂), overglaze, and dielectric (e.g., A1₂0₃, Zr0₂). The conductive pastes are based on metal particles, such as Ag, Pd, Au, or Pt, or a mixture of these combined with glass. Resistive pastes are based on Ru0₂ or Bi₂Ru₂0₇ mixed with glass (e.g., 65% PBO, 25% Si0₂, 10% Bi₂0₃).

[00129] The resistivity is determined by the mixing ratio. Overglaze and dielectric pastes are based on glass mixtures. Different melting temperatures can be achieved by adjusting the paste composition. See, for example, Madou, Fundamentals of

Microfabrication, Second Edition, CRC Press, Boca Raton, Florida, 2002, pp. 154-156, which is hereby incorporated by reference herein in its entirety.

7.20 Electroless metal deposition

[00130] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by electroless metal deposition. In electroless plating a layer is built by chemical means without applying a voltage. Electroless plating baths can be used to form Au, Co-P, Cu, Ni-Co, Ni-P, Pd, or Pt layers. See, for example, Madou,

Fundamentals of Microfabrication, Second Edition, CRC Press, Boca Raton, Florida, 2002, pp. 344-345, which is hereby incorporated by reference herein in its entirety.

7.21 Electroplating

[00131] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by electroplating. Electroplating takes place in an electrolytic cell. The reactions that take place in electroplating involve current flow under an imposed bias. In some embodiments, a layer is deposited as part of a damascene process. See, for example, Madou, Fundamentals of Microfabrication, Second Edition, CRC Press, Boca Raton, Florida, 2002, pp. 346-357, which is hereby incorporated herein by reference in its entirety.

Lithographic Etching Methods

[00132] The following subsections describe lithographic etching techniques that can be used in the fabrication methods described above. One of skill in the art will appreciate that etching or patterning the substrate can be conducted using other methods including, but not limited to, direct write technologies, Block Copolymer techniques and frequency doubling techniques.

8.1 Cleaning and dehydration baking

[00133] In some embodiments in accordance with the present disclosure, the fabrication methods begin with a cleaning process. Substrate cleaning is an important step in a lithographic process if there is contamination in presence, as the contamination can severally compromise the adhesion of the resist to the substrate. Substrate surfaces have four general types of contamination: particulates, organic residues, inorganic residues, and unwanted oxide layers. Depending on the substrate and the type of contaminants, several cleaning techniques can be used. These methods include dry cleaning, wet cleanings, ultrasonic agitation, polishing with abrasive compounds, supercritical cleaning.

[00134] In some embodiments, a wet cleaning is used to remove organic materials from the substrate and prepare for the adhesion of the resist to the substrate. It is carried out by submerging a substrate in a bath or by rinsing the substrate with DI water and/or a solvent rinse. After the wet cleaning, the substrate is dried to remove moistures. Several drying techniques can be used. For example, in some embodiments, the substrate after wet cleaning can be dried using dehydration bake method. In this method, the substrate is baked at a temperature for a period of time such as baked at 80 C for several minutes. In some embodiments, the substrate may be dried by N₂ flow or spinning. More detailed information with regard to cleaning and drying of a substrate can be found, for example, in Van Zant, Microchip Fabrication, Forth Edition, McGraw-Hill, New York, 2000, pp. 87-131, which is hereby incorporated by reference herein in its entirety.

8.2 Adhesion promotion coating [00135] To further improve the adhesion of the resist to the substrate, an adhesion promoter can be applied to the substrate before the application of the resist. Depending on the substrate and the resist, various adhesion promoters can be used. In some embodiments, Bis(trimethylsilyl)amine (also known as hexamethyldisilazane, or HMDS) or other organic materials are chosen as the adhesion promoter for the fabrication processes described in the present application.

[00136] HMDS is an organosilicon compound with the molecular formula

[(CH₃)₃Si]₂NH. The molecule is a derivative of ammonia with trimethylsilyl groups in place of two hydrogen atoms. This colorless liquid is a reagent and a precursor to bases that are popular in organic synthesis and organometallic chemistry. In photolithography, HMDS is often used as an adhesion promoter for photoresist, and can be applied using any suitable conventional methods. For example, HMDS can be applied by vapor chemical deposition. In general, good adhesions are obtained by applying HMDS from the gas phase on heated substrates.

8.3 Bottom anti-reflective coating

[00137] Optionally, a bottom anti-reflective coating (BARC) may be applied to help reduce image distortions associated with light reflections during lithography. In some cases, BARCs are critical and highly desirable. For example, when the substrate or a layer on the substrate is highly reflective, as in metal and polysilicon layers, light reflections can destroy the pattern resolution by three mechanisms: a) off-normal incident light can be reflected back through the resist that is intended to be masked; b) incident light can be reflected off device features and expose "notches" in the resist; and c) thin- film interference effects can lead to linewidth variations when resist thickness changes are caused by substrate or wafer topology or nonflatness.

[00138] BARCs can be either organic or inorganic, and can be applied either before or after the photoresist. Conventional methods, such as spinning, sputtering or chemical vapor deposition, can be used to apply the BARCs. By reducing standing waves, thin-film interference, or specular reflections, a BARC helps shrink line widths and improves the pattern resolution. In some cases, a BARC can absorb the radiation and dissipates the energy as heat. Such a BARC is generally suitable to be applied to a substrate before the resist. This BARC lowers reflectance back into the photoresist that has passed through the photoresist. 8.4 Resist properties

[00139] One form of photolithographic processing in accordance with the present disclosure begins with the coating of a resist layer over the layer of material to be patterned. Another form of photolithographic processing in accordance with the present disclosure applys the resist coating after at least one of the steps described in the previous sections, i.e., cleaning and dehydration baking, adhesion promotion coating or BARC. Resists used to form this resist layer are typically comprised of organic polymers applied from a solution. In some embodiments, the thickness of the resist is determined using Bossung Curve analysis. Bossung Curve analysis is one of the most commonly used tools in lithography. It maps a control surface for critical dimensions as a function of the variables of focus and exposure (dose). A detailed discussion of the Bossung Curve analysis can be found in Zavecz, Metrology, Inspection and Process Control edited by C. Archie, Proceeding of SPIE (2006) Vol. 6152 -109.

[00140] In some embodiments, this resist layer has a thickness in the range of 0.1 μιη to 2.0 um. Furthermore, in some embodiments, the resist layer has a uniformity of plus or minus 0.01 μιη. In some embodiments, the resist layer is applied using a spin technique such as a static spin process or a dynamic dispense process. In some embodiments, the resist layer is applied using a manual spinner, a moving-arm resist dispenser, or an automatic spinner. See, for example, Van Zant, Microchip Fabrication, Forth Edition, McGraw-Hill, New York, 2000, pp. 217-222, which is hereby incorporated by reference herein in its entirety.

[00141] Negative resists. In some embodiments, the resist layer is an optical resist that is designed to react with ultraviolet or laser sources. In some embodiments, the resist layer is a negative resist in which polymers in the resist form a cross-linked material that is etch resistant upon exposure to light. Examples of negative resists that can be used to make the resist layer include, but are not limited to, azidelisoprene negative resists,

polymethylmethacrylate (PMMA), polymethylisopropyl ketone (PMIPK), poly-butene-1- sulfone (PBS), poly-(trifluoroethyl chloroacrylate) TFECA, copolymer-(V-cyano ethyl acrylate-V-amido ethyl acrylate) (COP), poly-(2 -methyl pentene-l-sulfone) (PMPS) and the like.

[00142] Positive resists. In other embodiments, the resist layer (e.g., positive resist layer of Fig. 2A) is a positive resist. The positive resist is relatively insoluble. After exposure to the proper light energy, the resist converts to a more soluble state. This reaction is called photosobulization. One positive photoresist in accordance with the present disclosure is the phenol-formaldehyde polymer, also called phenol-formaldehyde novolak resin. See, for example, DeForest, Photoresist: Materials and Processes, McGraw-Hill, New York, 1975, which is hereby incorporated by reference herein in its entirety. In some embodiments, the resist layer is LOR OSA, LOR 5 0.7A, LOR 1A, LOR 3A, or LOR 5A (MICROCHEM, Newton, Massachusetts). LOR lift-off resists use polydimethylglutarimide.

8.5 Soft baking

[00143] After the resist layer has been applied, the density is often insufficient to support later processing. And some solvent may inhibit the exposure curve. Accordingly, in some embodiments of the present disclosure, a bake is used to density the resist layer and drive off residual solvent or excess carrier solvent from the resist layer. After the bake, the resist becomes less tacky and the thickness of the resist layer is reduced slightly. This bake is referred to as a softbake, prebake, or post-apply bake. Several methods of baking the resist layer are contemplated by the present disclosure including, but not limited to, convection ovens, infrared ovens, microwave ovens, or hot plates. See, e.g, Levinson, Principles of Lithography, SPIE Press, Bellingham, Washington, 2001, pp. 68-70, which is hereby incorporated by reference herein in its entirety.

8.6 Alignment and exposure of the mask

[00144] After the spacer has been coated with a resist layer, the next step is alignment and exposure of the resist layer. Alignment and exposure is, as the name implies, a two- purpose photomasking step. The first part of the alignment and exposure step is the positioning or alignment of the required image on the material surface. The image is found on a mask. The second part is the encoding of the image in the resist layer from an exposing light or radiation source. In the present disclosure, any conventional alignment system can be used to align the mask with the resist layer, including but not limited to, contact aligners, proximity aligners, scanning projection aligners, steppers, step and scan aligners, x-ray aligners, and electron beam aligners. For a review of aligners that can be used in the present disclosure, see, e.g., Solid State Technology, April 1993, p. 26; and Van Zant, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, pp. 232-241, each of which in incorporated herein by reference in its entirety. Masks can be negative or positive. [00145] A positive mask (not shown) used to develop a positive resist would have the opposite pattern of a negative mask. Both negative masks and positive masks used in the methods of the present disclosure are fabricated with techniques similar to those used in wafer processing. A photomask blank, consisting of an opaque film (usually chromium) deposited on glass substrates, is covered with resist. The resist is exposed according to the desired pattern, is then developed, and the exposed opaque material etched. Mask patterning is accomplished primarily by means of beam writers, which are tools that expose mask blanks according to suitably formatted biosensor electrode patterns. In some embodiments, electron or optical beam writers are used to pattern negative masks or positive masks. See, e.g., Levison, Principles of Lithography, SPIE Press, Bellingham, Washington, 200 1, pp. 229- 256, which is hereby incorporated by reference herein in its entirety.

[00146] Exposing the resist to light breaks or forms chemical bonds in the resist layer.

The final image matches the desired pattern from the mask or interference pattern. In various embodiments, attention is focused on providing uniformity of the light intensity and/or controlling the exposure rate.

[00147] In one embodiment of the present disclosure, the tool used to project the pattern of a mask onto a device is a wafer stepper. Wafer steppers exist in two

configurations, step-and-repeat and step-and-scan. In a step-and-repeat system, the entire area of the mask to be exposed is illuminated when a shutter is opened. In a step-and scan system, only part of the mask, and therefore only part of the exposure field on the device unit, is exposed when a shutter is opened. The entire field is exposed by scanning mask and the device being patterned synchronously. See, e.g., Levison, Principles of Lithography, SPIE Press, Bellingham, Washington, 200 1, pp. 1 33- 174, which is hereby incorporated by reference herein in its entirety.

8.7 Post expose bake

[00148] Before developing the resist, a post exposure bake (PEB) is optionally performed after exposure. In some cases where high resolutions are not required, the PEB is not necessary. However, for certain resists or for high resolutions, a PEB is inevitable for the crosslinking induced by the exposure.

[00149] PEB can be applied above the softening point of the resist without destroying the structures to be developed. For example, a PEB can be performed at 110°C, for 1-2 min on a hotplate. A PEB performed near the softening point of the photo resist can reduce mechanical stress formed during softbake and exposure. A PEB can also promote the thermally activated diffusion of carboxylic acid formed during exposure from the photo active compound. This diffusion step smoothes the spatial periodic pattern of carboxylic acid, which in turn will help to improve the image or pattern resolution.

8.8 Development

[00150] After exposure through a mask, the pattern is coded as a latent image in resist as regions of exposed and unexposed resist. The pattern is developed in the resist by chemical dissolution of the unpolymerized resist regions. A number of development techniques can be used to develop the resist. Development techniques are designed to leave in the resist layer an exact copy of the pattern that was on the mask or reticle. The successful development of the image coded in resist is dependent on the nature of the resist's exposure mechanisms.

[00151] Negative resist, upon exposure to light, goes through a process of

polymerization which renders the resist resistant to dissolution in the developer chemical. The dissolving rate between the two regions is high enough so that little of the layer is lost from the polymerized regions. The chemical preferred for many negative -resist-developing situations is xylene or Stoddart solvent. The development step is done with a chemical developer followed by a rinse. For negative resists, the rinse chemical is n-butyl acetate in some embodiments.

[00152] Positive resists present a different developing condition. The two regions, polymerized and unpolymerized, have a different dissolving rate. This means that during the developing step some resist is always lost from the polymerized region. Use of developers that are too aggressive or that have overly long developing times result in an unacceptable thinning of the resist. Two types of chemical developers used with positive resists in accordance with the present disclosure are alkaline-water solutions and nonionic solutions. The alkaline -water solutions can be sodium hydroxide or potassium hydroxide. Typical nonionic solutions include, but are not limited to, tetramethylamrnonimurn hydroxide (TMAH). The rinse chemical for positive-resist developers is water. A rinse is used for both positive and negative resists. This rinse is used to rapidly dilute the developer chemical to stop the developing action. [00153] There are several methods in which a developer is applied to resist in order to develop the latent image. Such methods include, but are not limited to, immersion, spray development, and puddle development. In some embodiments of the present disclosure, wet development methods are not used. Rather, a dry (or plasma) development is used. In such dry processes, a plasma etcher uses energized ions to chemically dissolve away either exposed or unexposed portions of the resist layer without first developing the resist layer using wet chemical techniques.

[00154] In some embodiments, in particular when an organic compound is used as the photoresist, the chemical reaction in the resist layer needs to be controlled to ensure the image fidelity. This can be achieved by controlling the exposure time, the development time, or other processing parameters. Image fidelity herein refers to the ability of a lithographic process to render an image accurately, without any visible distortion or information loss.

8.9 Hard baking

[00155] In some embodiments of the present disclosure, resist is hard baked after it has been developed. The purpose of the hard bake is to achieve good adhesion of the resist layer to the underlying layer to be patterned. In some embodiments, a hard bake is accomplished using a convection oven, in-line or manual hot plates, infrared tunneling ovens, moving-belt convection ovens, vacuum ovens and the like. General baking temperature and baking times are provided by the resist manufacture. Therefore, specific baking temperatures and times is application dependent. Usually the hard baking temperature is the hottest or highest temperature among all of the processes. Nominal hard bake temperatures are from 130°C to 200°C for thirty minutes in a convection oven. The hard baking sets the resist and enhances mechanical stability of the resist for the subsequent etch or implant process. At this point, the image fidelity is usually measured and fed back to the preceding lithographic steps.

8.10 Etching

[00156] After development, an etching step is used for patterning. A number of etching methods are available. Etching can be divided into dry and wet etching. The following disclosure provides examples of such etching. It will be understood by one of skill in the art that the disclosed etching methods can be used independently of the preceding lithographic steps in accordance with some embodiments. It will be further understood by one of skill in the art that the disclosed etching methods can be used with the preceding lithographic steps in accordance with some embodiments. Wet etching is the use of acidic or basic solutions to solvate away a specific reacted species. Examples are silicon dioxide being etched in hydrofluoric acid, or S1₃N₄ in hot phosphoric acid, or mono-crystalline silicon in potassium hydroxide (KOH)). Photoresist materials are removed by acid or base materials (depending on polarity and resist chemistry).

[00157] The following list is a generic categorization of the classifications of etch methods. Each etch method has specialized equipment for optimization of the process.

Complexity has evolved to the point where some of the terms and techniques are

interchangeable. For example, there are terms depending on the vendor, for inductive coupled plasma (ICP) etch or transformer coupled plasma (TCP), each which improves an ion etcher.

[00158] Wet etching.

[00159] In wet etching, etchant is introduced either as a liquid bath with submersion or a surface spray/mist. Material is removed as a function of solvation of the etch intermediate or byproduct. A limitation of wet etching is the wetting function of the chemical. Some etchants are two step reactions such as oxidation of a material then solvation of the oxide.

[00160] Wet etches can also be used in combination with the dry etches as a preparatory step for surface cleaning or contaminate removal. An example is organic material removal prior to a reactive ion etch. Wet etches are typically isotropic or follow crystal lattices.

[00161] In one embodiment of the present disclosure, the structure to be patterned is immersed in a tank of an etchant for a specific time. Then the structure is transferred to a rinse station for acid removal, and transferred to a station for final rinse and a spin dry step.

[00162] Wet spray etching or vapor etching. In some embodiments of the present disclosure, wet spray etching or vapor etching is used for patterning. Wet spray etching offers several advantages over immersion etching including the added definition gained from the mechanical pressure of the spray. In vapor etching, the wafer is exposed to etchant vapors such as hydrofloric acid vapors.

[00163] Dry etching - Reactive-ion etching. [00164] Dry etching encompasses other methods outside the wet etch environment.

Basic mechanics includes excitation of a chemical to an ionic state and then reaction with the substrate and films. Material is removed either by physical/mechanical methods or chemical conversion and solvation into the gas stream.

[00165] Sputter (physical / mechanical). In sputter approaches, ions or elements are accelerated to a high energy and directed toward a surface. Surfaces are removed due to the collisions of these highly charged ions, much like a nanoscale sandblasting method. Sputter etching is facilitated by charging the ion and then establishing a high bias towards to the substrate. Removal is line of sight from the target in the direction of the bias. Sputter etching is a method to achieve anisotropic etch profiles. Sputtering can also be accomplished by directional ion bombardment by 'ion guns'. Examples include focused ion beam (FIB) or other direct write approaches.

[00166] Chemical (solvation - liquid or gas). Chemical enhanced etching exploits generation of intermediate species that can be solvated in the solution or vaporized in the low pressure chamber. Chemical etching is tuned to generate the solvated states due to the chemicals included in the reaction mixture. For example, chlorine is used for most metals. A fluorine based chemical such as carbontetrafluoride (CF₄) or sulfurfluoride (SF₆) is used for etching silicon or silicon oxide. Oxide etches with CF₄ or SF₆ follows the same reaction mechanism as the wet etch with HF acid.

[00167] Chemical etch is more isotropic in nature than the corresponding sputtering systems. A technique of alternating and combining the two methods can sculpt complex side wall profiles. The present disclose encompasses the use of such methods to generate the specific nodes for functionality. An example is the 'wine glass' structure disclosed Figure 7 of related application No. 61/802,006, filed March 15, 2013, which is hereby incorporated by reference herein for its disclosure of such structures.

[00168] Ion beam etching. Another type of etcher that is used to perform the etching of spacer 140 in accordance with various aspects of the present disclosure is ion beam etching. Unlike chemical plasma systems, ion beam etching is a physical process. The structure to be etched is placed on a holder in a vacuum chamber and a stream of argon is introduced into the chamber. Upon entering the chamber, the argon is subjected to a stream of high-energy electrons from a set of cathode (-)-anode (+) electrodes. The electrons ionize the argon atoms to a high-energy state with a positive charge. The wafers are held on a negatively grounded holder that attracts the ionized argon atoms. As the argon atoms travel to the wafer holder they accelerate, picking up energy. At the wafer surface, they crash into the exposed wafer layer and blast small amounts from the wafer surface. No chemical reaction takes place between the argon atoms and the wafer material. The material removal (etching) is highly directional (anisotropic), resulting in good definition in small openings.

[00169] Plasma etching. Plasma generation is a method for ionization in the dry etch process. Plasmas can be tuned and controlled for the different gases used. Plasma can be struck with one gas and maintained by another. Relative location of the plasma can increase etch rate or impact resultant damage. Some systems apply remote plasma generation sources while others control the confinement and immersion in the plasma. Generally there is a dilution or carrier gas that maintains the plasma and then a small volume of reactive gas is introduced. Vacuum levels define the type of plasma etching and complexity for control. Power of the generator is a control factor as well as the frequency.

[00170] In some embodiments , plasma etching is performed using a plasma etcher.

Physically, a plasma etcher comprises a chamber, vacuum system, gas supply, and a power supply. The structure to be etched is loaded into the chamber and the pressure inside is reduced by the vacuum system. After the vacuum is established, the chamber is filled with the reactive gas. For the etching of silicon dioxide, for example, the gas is usually CF4 that is mixed with oxygen. A power supply creates a radio frequency (RF) field through electrodes in the chamber. The field energizes the gas mixture to a plasma state. In the energized state, the fluorine attacks the silicon dioxide, converting it into volatile components that are removed from the system by the vacuum system.

[00171] Any of a wide variety of plasma etchers is used to perform etching, in accordance with various embodiments of the present disclosure. Such etchers include, but are not limited to, barrel etchers, plasma planar systems, electron cyclotron resonance sources, high density reflected electron sources, helicon wave sources, inductively coupled plasma sources, and transformer coupled plasma sources.

[00172] In some embodiments, a reactive ion etcher system combines plasma etching and ion beam etching principles. The systems are similar in construction to the plasma systems but have a capability of ion milling. The combination brings the benefits of chemical plasma etching along with the benefits of directional ion milling. See, e.g., Van Zant, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, pp. 256-270, which is hereby incorporated herein by reference for more information on etching techniques and etching equipment that can be used in accordance with the present disclosure.

8.10 Characteristics of an Etch Process.

[00173] The etch process generates an artifact or signature of the processing employed.

Knowledge of how to apply etching methods determines the final profile of the structure. Definitions for the following terms are provided in order to convey an understanding of the etch processing characteristics.

[00174] Isotropic etching. Isotropic implies equal etching in all directions. The two references are vertical and horizontal directions. An isotropic etch 'undercuts' the mask at a ratio to the vertical depth etched. Impact is that a circular opening of 1 micron when etched to a 0.5 micron depth would have a bowl like shape that is 2 microns at the top of the bowl, 1 micron at the bottom, with rounded side walls. An important consideration here is that if a conformal film were deposited over a topography/structure, an isotropic etch would remove the horizontal material as well as the side wall/vertical material. There is no shadowing or off line of sight protection from an isotropic etch (excluding rate limiting or aspect ratio physical diffusivity barriers). This characteristic is used in cleans and sacrificial film removals. One trick is to use isotopic etching to consume the side walls, thereby reducing the critical dimension.

[00175] Anisotropic etching. Anisotropic etching is preferential etching in one direction over the other. Hence the term anisotropic: not isotropic. Ability to produce anisotropic etch chemistries allows for denser packing of devices. Anisotropy is limited by the bias and directionality of the tool utilized. The mask image is transferred into the substrate with fidelity: a 1 micron circular opening etched to 0.5 micron depth is 1 micron by 0.5 micron feature in the substrate.

[00176] An application for the disclosed technology is considering the etching of a conformal coating. If the deposited film is .25 microns over a .8 micron step, an anisotropic etch removes the .25 microns on the surface (horizontal surface) but leaves the side wall (vertical surface) material. Thereby an anisotropic etch results in a new structure of the deposited material where an isotropic etch would remove all material. Limitations on anisotropic etches are physical limitations that inhibit reactive species reaching the bottom surface of the etch location. These topics are defined in 'aspect ratio', 'poisoning', 'etch stops' and other terms below.

[00177] Etching Definitions and Examples

[00178] Etch rate - A function of the process recipe which quantifies how fast a material is removed. Units are expressed in removed thickness per time, e.g. Angstroms per second. Etch rate includes lateral calculation as well as the vertical component. Etch rate can be reduced by addition of diluents or carrier gases that do no enhance the etch reaction. Etch rate is modified to compensate for reaction chamber design where the etch rate in the center may be higher than on the outer edge. Etch rate is sacrificed for uniformity and repeatability. High etch rates are desirable for manufacturability. However, etch rate is only one part of the grand compromise for a final etch process.

[00179] Selectivity - A comparative etch rate ratio of the desired material to be etched and the protective mask material (ratio of material etch rate over mask etch rate). A high selectivity is desired to maintain transfer of the lithography into the substrate. If the selectivity is low the differentiation between starting structure and final structure is compromised due to loss of mask. Etch chemistries are adjusted to achieve the highest selectivity possible without compromising process time for the material etch rate. High selectivity with an Angstrom per hour etch rate is not practical in typical embodiments.

[00180] Side wall slope - A desired etch profile could be a perfect transfer of the mask image into the substrate material with vertical sidewalls. The most common etch artifact is an oblique angle slope where the top is wider than the bottom. This can be caused from various etch conditions. A primary mechanism for this is that the etch reaction is hindered by diffusivity of the etchant, by-product interference, loss of ionization states, or competitive nonproductive reactions. In the instant disclosure, both vertical side wall, oblique and re-entry angled structures are contemplated through the disclosed etching techniques.

[00181] Re-entrant Side wall - The opposite of the oblique angle side wall is the reentrant side wall angle. Here the bottom is wider than the top masked surface. This profile can be obtained by segmented etching with increasingly isotropic etch recipes. The isotropic undercuts by the lateral etch nature. The resultant structure resembles the dove tail joint in wood working. Another method for reentrant side walls is the enhancement of the etch rate in the trench as a function of dopant materials.

[00182] Inhibitor Sidewall protection due to byproduct re-deposition. Another control method for side wall profile is due to the nature of the etchant reaction. The etch reaction may generate a by-product that is not highly volatile. These compounds redeposit on the side wall during the reaction. In an isotropic etch it stops the lateral etch at the top but does not hinder at the bottom area. Re-deposition is viewed as both a positive and negative aspect of the process. Such re-deposition is advantageously used in the present disclosure.

[00183] Erosion. A method to increase the oblique slope of a side wall during an etch process is to erode the masking material at the edges. This is usually a function of heating the mask material during the etch process. This has the impact that the edge acuity of the resist is lost, resulting in the feature size being gradually reduced with etch time. Resist erosion reduces the critical dimension at the top of the feature. Examples of extreme erosion would produce teepee or pyramid like structures

[00184] Etch Stop. An etch stop material is a material that has a very low etch rate that is built as a sandwich structure in a device. As the target material is etched the structure is defined. However when the etchant hits the etch stop material the maximum depth is reached. This is a method to control the depth of an etch material with high precision.

Deposition sandwich can be controlled uniformly across the substrate regardless of the etch reactor design or non uniformity. A second artifact is that the amount of over etch time can be extended and only the lateral etch will continue. Lateral etch results in re-entrant slopes or critical dimension reduction.

[00185] Self limiting or poisoning. An etch recipe can be designed in which there is a limitation of the etchant material. Then due to physical constraint such as aspect ratio, dilution, power or bias, the effective etch is restricted. Evidence of this artifact is in deep trench, 10 to 15 microns, where there is tapering and closure. Regardless of the additional time provided the etch depth does not progress. Poisoning of the reaction has the same results but can be observed by additions to the gas stream that inhibits conversion to the desired species, or a competitive reaction that consumes the reactive species in a

nonproductive reaction. [00186] Crystalline specific (lattice orientation). For mono crystalline or highly ordered lattice structures, etchants can be used to highlight and accentuate the lattice structure. For example, iodine based wet etches are used for defect analysis due to different etch rates on the crystal lattice. In some embodiments, crystalline specific etches for special substrate enhancements and for specific devices are used. In some embodiments, metallic etches can improve the surface area for the graphene growth. Moreover, nucleation approaches make use of faceting etch for graphene growth.

[00187] Secondary Etch Functions and Utilization

[00188] The following provides additional uses for the disclosed etching processes that are used in accordance with some embodiments of the present disclosure.

[00189] Cleaning. Etch removal of contaminates accumulated during previous processing steps can be performed. Examples of a standard etch clean process such as the RCA Clean is 1) application of distilled water, 2) application of buffered ammonium hydroxide, 3) application of dilute HF for ancient oxide, and 4) application of HC1 for metallic clean. Clean procedures can also be plasma based prior to a deposition process. A clean process is removing the unwanted films prior to the following step. Cleans can be before etch steps (remove inhibitors), deposition and lithography.

[00190] Polish. A light etch step to change the profile slightly or remove unwanted residuals. For segmented film deposition a slight polish removes undesired side wall material and fine tunes by reduction of material the final film thickness.

[00191] Structure definition. Previous discussion highlighted the side wall slope as nominal/vertical, oblique, or reentrant angled. Functional nodes can be sculpted in the profile by tuning the etch process. A simple example is the wine glass structure which was designed for metal flow into contact views. As the structures became more complex such as for plasmonics, nodes are defined by crevices or protrusion. Full structures such as a rib or ribbon can be generated by an anisotropic etch of a conformally deposited film. These concepts are captured in our portfolio as related to side walls, segmented film deposition, or fine structure lithography to name a few.

[00192] Deep trench and isolation of structures. State of the art technologies have advanced to do deep trench etches with aspect ratios of 20: 1 to greater. One of the benefits of trench formation is the ability to isolate structures on the same substrate. The isolation can be by air or a back fill material (dielectric or oxides. The etch process defines the isolation and the resultant critical dimension of the rib or pillar. Polarity is important because the device functionality can be buried in the bottom of the trench and the wall portions can act as thermal radiators, wave guides, or particulate traps.

[00193] Aspect ratios. Aspect ratio is defined by the height of the structure over the width. In the etch process this impacts the diffusivity of the etchant in a narrow trench (10: 1) which will slow the etchant reaction. A secondary concern is the physical stability of a tall feature on a narrow base. Such features are impacted by the micro fluidic forces of subsequent processing resulting in toppling or cleavage of the structure.

[00194] Side wall deposition. Depending on the application and process engineering this can be a benefit or a detriment. The majority of re-deposition material during an etch process is difficult to remove with later steps (especially metal halides) which is a detriment. The rate of re-deposition can impact the profile of the structure. A benefit of re-deposition is an organic re-deposition or interaction with the photo resist that maintains the resist mask and image fidelity. This re-deposition is a corrective action for undesired resist erosion. Another example of re-deposition being beneficial is when the byproduct material can be formed for a device functionality or structure.

[00195] Etch passivation. Slight differentiation, or subset of side wall re-deposition.

During an etch step and oxidizing ambient may be used as the etchant chemistry. If there are other layers exposed such as metals (aluminum) a thin oxide will be formed which passivates the secondary surface. Other etch byproducts passivates other materials.

[00196] Tool Types

[00197] The present disclosure encompasses the use of a wide variety of etch tool configurations. Manufactures of such tools include, but are not limited to, Applied materials, Lam Research, Tegal, Hitachi, Oxford, Plasma Therm, and Branson to name a few. Each company has improvements or enhancements over the competitors. The following list highlights some of the designs and types of reactors on the market: barrel etchers, parallel plate, downstream etchers, ICP, TCP, sinks, spray dispense, oxidation, EBEAM oxidation, and direct write systems. For wet etch (wet sinks) there are numbers of designs for recirculation, purity, automation of multiple baths and inclusion of spin rinse dryers. Note also in the literature some tools are refined to the substrate or material designed to be etched: metal etchers, oxide etchers, etc.

8.11 Residual layer removal

[00198] The result of the etching process described above is the formation of grooves. Next, the residual layer is removed in a process known as resist stripping in order to yield the patterned structure. In some embodiments, the resist is stripped off with a strong acid such as H₂SO₄ or an acid oxidant combination, such as Η₂8θ4-Ο·₂θ3, attacking the resist but not the groove to yield the fully patterned structure. Other liquid strippers include organic solvent strippers (e.g., phenolic organic strippers and solventlamine strippers) and alkaline strippers (with or without oxidants). In some embodiments of the present disclosure, a dry plasma process is applied to remove a resist. In such embodiments, the device is placed in a chamber and oxygen is introduced. The plasma field energizes the oxygen to a high energy state, which, in turn, oxidizes the resist components to gases that are removed from the chamber by the vacuum pump. In dry strippers, the plasma is generated by microwave, radio frequency, or ultraviolet-ozone sources. More information on photolithographic processes that can be used to pattern devices is found in Madou, Fundamentals of Microfabrication, Second Edition, CRC Press, Boca Raton, Florida, 2002, pp. 2-65; Van Zant, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, Wolf and Tauber, Silicon Processing for the VLSI Era, Second Edition, Lattice Press, Sunset Beach, California, 2002; and SZE and Ng, Physics of Semiconductor Devices, Third Edition, Wiley-Interscience, 2007, each of which are hereby incorporated by reference herein in their entireties. Such methods include the use of a positive photoresist rather than a negative photoresist as well as extreme ultraviolet lithography, x-ray lithography, charged-particle-beam lithography, scanning probe lithography, soft lithography, and three-dimensional lithographic methods.

REFERENCES CITED

[00199] All references cited herein are incorporated herein by reference in their entirety and for all purposes to the same extent as if each individual publication or patent or patent application was specifically and individually indicated to be incorporated by reference in its entirety for all purposes. [00200] Many modifications and variations of this disclosure can be made without departing from its spirit and scope, as will be apparent to those skilled in the art. The specific embodiments described herein are offered by way of example only, and the disclosure is to be limited only by the terms of the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

WHAT IS CLAIMED IS:

1. A method for fabricating a multilevel stacked graphene structure, the method comprising:

a) forming a first graphene level comprising one or more graphene stacks on a substrate, wherein a graphene stack in the first graphene level forms a first graphene based nanostructure;

b) depositing a first interlayer on the first graphene level; and

c) forming a second graphene level comprising one or more graphene stacks on the first interlayer, wherein a graphene stack in the second graphene level forms a second graphene based nanostructure.

2. The method of claim 1, wherein the substrate is patterned before the forming a).

3. The method of claim 1, wherein the forming a) comprises depositing a first foundation material onto the substrate and using the first foundation material to form the first graphene level.

4. The method of claim 3, wherein the first foundation layer is patterned before forming graphene using the first foundation layer.

5. The method of claim 1, wherein the forming c) comprises depositing a second foundation material onto the first interlayer and using the second foundation material to form the second graphene level.

6. The method of claim 5, wherein the first foundation layer is patterned before forming graphene using the second foundation layer.

7. The method of claim 1, further comprising sequentially repeating the depositing b) and forming c) one or more times thereby forming at least a second interlayer on the second graphene level, and a third graphene level on the second interlayer, the third graphene level including one or more graphene stacks, wherein a graphene stack in the third graphene level forms a third graphene based nanostructure.

8. The method of claim 1, wherein the substrate comprises an exposed portion and wherein the forming the first interlayer c) includes providing at least one air gap in the exposed portion of the substrate.

9. The method of claim 2, wherein the depositing the first foundation material includes creating at least one air gap between portions of the first foundation layer and wherein depositing the first interlayer b) includes leaving the least one air gap between portions of the first foundation layer and the first graphene level.

10. The method of claim 3, wherein one or more gaps exist between portions of the substrate and wherein the depositing b) comprises backfilling the one or more gaps with an interlayer material.

11. The method of claim 3, wherein the first foundation material comprises Ni, Cu, Pt, Au, Fe, Pvh, Ru, Ti, Ir, Si, SiC, boron doped SiC, or any combination thereof.

12. The method of claim 5, wherein the second foundation material comprises Ni, Cu, Pt, Au, Fe, Rh, Ru, Ti, Ir, Si, SiC, boron doped SiC, or any combination thereof.

13. The method of any one of claims 1-11, wherein the first or second graphene based nanostructure comprises a graphene nanoribbon, a graphene nano-network, a graphene pole, a graphene pillar, or a graphene based nanohole superlattice.

14. The method of any one of claims 1-13, wherein the substrate comprises glass, silicon, SiC, Si0₂ or SiC/Si.

15. The method of any one of claims 1-14, wherein the first interlayer comprises glass, Si, SiC, Si0₂, Si₃N₄, HfO, TiO, indium tin oxide, Al, W, or Pt.

16. The method of any one of claims 1-15, wherein the forming a) or forming c) occurs through chemical vapor deposition.

17. The method of any one of claims 1-15, wherein the forming a), depositing b) or forming c) occurs through a process selected from the group consisting of molecular beam deposition, laser ablated deposition, collimated sputtering, vacuum evaporation, ionized physical vapor deposition, and ion beam deposition.

18. The method of any one of claims 1-12 or 14-17, wherein the first graphene based nanostructure comprises a graphene based nanohole superlattice comprising a plurality of layers arranged on the substrate, the plurality of layers having an array of holes defined therein, and wherein the first graphene based nanostructure is characterized by a band gap or a band gap range.

19. The method of claim 1, wherein the forming a) or forming c) occurs segmentally.

20. The method of any one of claims 1-13 or 15-19, wherein the first interlayer is a transparent conductive oxide.

21. The method of any of claims 1-20, wherein the first graphene based nanostructure and the second graphene based nanostructure differ in a curvature, an edge shape, or a width.

22. The method of claim 1, wherein

i) the substrate comprises a plurality of recesses,

ii) the forming a) comprises depositing a first foundation material onto the substrate and using the first foundation material to form the first graphene level, and

iii) the forming c) comprises depositing a second foundation material onto the substrate and using the second foundation material to form the second graphene level, the method further comprising:

etching the first foundation layer such that a reduced thickness first foundation layer is selectively exposed in the plurality of recesses in the substrate, wherein the forming the first graphene level a) comprises growing graphene onto the reduced thickness first foundation layer thereby forming the first graphene level in the plurality of recesses in the substrate; and

etching the second foundation layer such that a reduced thickness second foundation layer is selectively exposed in the plurality of recesses in the substrate, wherein the forming the second graphene level c) comprises growing graphene onto the reduced thickness second foundation layer thereby forming the second graphene level.

23. The method of any of claims 1-22, wherein the first graphene based nanostructure and the second graphene based nanostructure differ in a pitch or in a critical dimension.

24. A multilevel graphene stacks structure fabricated by any one of the methods of claims 1-23.

25. A structure comprising:

a substrate;

a first graphene level overlayed on the substrate, the first graphene level comprising one or more graphene stacks, wherein a first graphene stack in the first graphene level forms a first graphene based nanostructure;

a first interlayer overlayed on the first graphene level; and

a second graphene level overlayed on the first interlayer, wherein the second graphene level comprises one or more graphene stacks, wherein a second graphene stack in the second graphene level forms a second graphene based nanostructure.

26. The structure of claim 25, wherein the first graphene stack and the second graphene stack differ in a characteristic dimension, pitch, band gap, or index of refraction.

27. The structure of claims 25 or 26, wherein the first graphene stack is not aligned with the second graphene stack.

28. The structure of any one of claims 25-27, wherein the first graphene level and the second graphene level each comprises a respective plurality of graphene stacks.

29. The structure of claim 28, wherein spacing between graphene stacks in the first graphene level is different from spacing between graphene stacks in the second graphene level.

30. The structure of any one of claims 25-29, further comprising:

a second interlayer overlayed on the second graphene level;

a third graphene level overlayed on the second interlayer, wherein the third graphene level comprises at least a third graphene stack, wherein the third graphene stack includes a third graphene based nanostructure.

31. A structure comprising:

a substrate; a first graphene level, the first graphene level comprising a first plurality of graphene stacks, wherein each respective graphene stack in the first plurality of graphene stacks is (i) overlayed on the substrate and (ii) spatially separated from all other graphene stacks in the first plurality of graphene stacks;

a first interlayer overlayed on the first graphene level; and

a second graphene level, the second graphene level comprising a second plurality of graphene stacks, wherein each respective graphene stack in the second plurality of graphene stacks is (i) overlayed on the first interlayer and (ii) spatially separated from all other graphene stacks in the second plurality of graphene stacks.

32. The structure of claim 31 , wherein

each graphene stack in the first plurality of graphene stacks has the same first thickness,

each graphene stack in the second plurality of graphene stacks has the same second thickness, and

the first thickness is other than the second thickness.

33. The structure of claim 31 , wherein spatial separations between the plurality of graphene stacks in the first plurality of graphene stacks forms a plurality of spaces and the first interlayer backfills into the plurality of spaces.

34. The structure of claim 31 , wherein spatial separations between the plurality of graphene stacks in the first plurality of graphene stacks forms a plurality of spaces and the first interlayer overlays these spaces thereby forming air gaps in the graphene structure

35. The structure of claim 31 , wherein

a first graphene stack in the first plurality of graphene stacks is characterized by a first value for a physical property,

a second graphene stack in the second plurality of graphene stacks is characterized by a second value for a physical property,

wherein the first value is other than the second value.

36. The structure of claim 35, wherein the physical property is a number of graphene layers, a width, a length, a thickness, an impurity concentration, an edge condition, a band gap, a defect, or an electromagnetic spectral response.

37. The structure of claim 31 , wherein

the first plurality of graphene stacks is collectively characterized by a first value for a physical property,

the second plurality of graphene stacks is collectively characterized by a second value for a physical property,

wherein the first value is other than the second value.

38. The structure of claim 37, wherein the physical property is a graphene stack packing density, a duty cycle, a pitch, an index of refraction, a band gap, or an electromagnetic spectral response.

39. The structure of claim 31 , wherein

the first plurality of graphene stacks are nanoribbons that are spaced apart from each other and are arranged in parallel on the substrate, and

the second plurality of graphene stacks are nanoribbons that are spaced apart from each other and are arranged in parallel on the first interlayer.

40. The structure of claim 39, wherein the spacing between graphene stacks in the first plurality of graphene stacks is different than the spacing between graphene stacks in the second plurality of graphene stacks.

41. The structure of claim 31 , wherein

the first plurality of graphene stacks are spaced apart from each other with a first spacing interval, and

the second plurality of graphene stacks are spaced apart from each other with a second spacing interval.

42. The structure of claim 41, wherein the first spacing interval is the same as the second spacing interval.

43. The structure of claim 41, wherein the first spacing interval is different than the second spacing interval.

44. The structure of claim 31 , wherein

the first plurality of graphene stacks are spaced apart from each other and are arranged at acute angles on the substrate with respect to each other, and

the second plurality of graphene stacks are spaced apart from each other and are arranged at acute angles on the first interlayer with respect to each other.

45. The structure of claim 31 , wherein

the first plurality of graphene stacks are nanoribbons that are spaced apart from each other and are arranged at acute angles on the substrate with respect to each other, and

the second plurality of graphene stacks are nanoribbons that are spaced apart from each other and are arranged at acute angles on the first interlayer with respect to each other.

46. The structure of claim 31 , wherein

the first plurality of graphene stacks are nanoribbons that are spaced apart from each other with a first spacing, and

the second plurality of graphene stacks are nanoribbons that are spaced apart from each other and are arranged so that each respective graphene stack in the second plurality of graphene stacks aligns with a corresponding graphene stack in the first plurality of graphene stacks.

47. The structure of claim 31 , wherein a center of each respective graphene stack in the second plurality of graphene stacks aligns with a center of a corresponding graphene stack in the first plurality of graphene stacks.

48. The structure of claim 31, wherein a leading edge of each respective graphene stack in the second plurality of graphene stacks aligns with a leading edge of a corresponding graphene stack in the first plurality of graphene stacks.

49. The structure of claim 31 , wherein a trailing edge of each respective graphene stack in the second plurality of graphene stacks aligns with a trailing edge of a corresponding graphene stack in the first plurality of graphene stacks.

50. A structure comprising:

a substrate;

a first graphene level, the first graphene level comprising a first plurality of graphene stacks, wherein each respective graphene stack in the first plurality of graphene stacks is (i) overlayed on the substrate and (ii) spatially separated from all other graphene stacks in the first plurality of graphene stacks; and

a second graphene level, the second graphene level comprising a second plurality of graphene stacks, wherein each respective graphene stack in the second plurality of graphene stacks is (i) overlayed on a corresponding graphene stack in the first plurality of graphene stacks and (ii) spatially separated from all other graphene stacks in the second plurality of graphene stacks.

51. The structure of claim 50, wherein

the first thickness is other than the second thickness.

52. The structure of claim 50, wherein

a second graphene stack in the second plurality of graphene stacks is characterized by a second value for a physical property, and

wherein the first value is other than the second value.

53. The structure of claim 52, wherein the physical property is a number of graphene layers, a width, a length, a thickness, an impurity concentration, an edge condition, a band gap, a defect, or an electromagnetic spectral response.

54. The structure of claim 50, wherein

the first plurality of graphene stacks is collectively characterized by a first value for a physical property, the second plurality of graphene stacks is collectively characterized by a second valueor a physical property,

wherein the first value is other than the second value.

55. The structure of claim 54, wherein the physical property is an index of refraction, a band gap, or an electromagnetic spectral response.

56. The structure of claim 50, wherein the first plurality of graphene stacks are nanoribbons that are spaced apart from each other and are arranged in parallel on the substrate.

57. The structure of claim 50, wherein the spacing between graphene stacks in the first plurality of graphene stacks is different than the spacing between graphene stacks in the second plurality of graphene stacks.

58. The structure of claim 50, wherein the first plurality of graphene stacks are nanoribbons that are spaced apart from each other and are arranged at acute angles on the substrate with respect to each other.

59. The structure of claim 50, wherein a center of each respective graphene stack in the second plurality of graphene stacks aligns with a center of a corresponding graphene stack in the first plurality of graphene stacks.

60. The structure of claim 50, wherein a leading edge of each respective graphene stack in the second plurality of graphene stacks aligns with a leading edge of a corresponding graphene stack in the first plurality of graphene stacks.

61. The structure of claim 50, wherein a trailing edge of each respective graphene stack in the second plurality of graphene stacks aligns with a trailing edge of a corresponding graphene stack in the first plurality of graphene stacks.