CN102229421B - The preparation method of nano thread structure - Google Patents
The preparation method of nano thread structure Download PDFInfo
- Publication number
- CN102229421B CN102229421B CN201110106336.2A CN201110106336A CN102229421B CN 102229421 B CN102229421 B CN 102229421B CN 201110106336 A CN201110106336 A CN 201110106336A CN 102229421 B CN102229421 B CN 102229421B
- Authority
- CN
- China
- Prior art keywords
- metal
- semiconductor layer
- preparation
- nano
- thread structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of preparation method of nano thread structure, the method is by the sidewall surfaces depositing metal films in polycrystal semiconductor layer both sides, metal in described metallic film spreads to the sidewall surfaces of described polycrystal semiconductor layer, after annealed, metal-semiconductor compounds nano wire is formed in the sidewall surfaces of described polycrystal semiconductor layer, preparation method due to nano thread structure provided by the invention does not need to utilize high-resolution photoetching technique to form nano wire, thus preparation cost has greatly been saved, and metal-semiconductor compounds nano wire prepared by the present invention can also as mask, by its nanostructured Graphic transitions to next Rotating fields, thus provide conveniently for the preparation of nano thread structure.
Description
Technical field
The present invention relates to semiconductor process technique field, particularly relate to a kind of preparation method of nano thread structure.
Background technology
The semiconductor integrated circuit technique of present stage advanced person enters nm regime, and the characteristic size of transistor is also by continued scale-down, at raising device performance while reducing single transistor cost, higher requirement be it is also proposed to semiconductor technological condition, and by the impact of quantum effect, the characteristic size of device can not ad infinitum continue to reduce, and traditional semi-conducting material, technique will meet with bottleneck, the directive significance that Moore's Law will lose semi-conductor industry.Research and develop new material, new technique carrys out materials and process in alternative existing integrated circuit and have exigence.The one-dimensional material such as nano wire, nanotube is as functional unit requisite in nano-device, and the status in research in nanotechnology field seems important all the more.
In addition, in recent ten years, in Condensed Matter Physics field, the research of people to low-dimensional, small dimensional material shows keen interest.Nanostructured is in current scientific technological advance forward position, has challenging research field.Especially in recent years, the silicon line of nanoscale is more and more subject to people's attention.On the one hand, because its potential application prospect, such as: device miniaturization, integrated level is improved, and for making some particular device etc.; On the other hand, due to the special physical property such as skin effect that silicon materials show under miniature scale, mechanics effect, the characteristics of luminescence and quantum size effects etc., be more and more subject to the attention of scientific circles.
At present, the preparation of silicon nanowires mainly adopts two kinds of preparation methods of the routine of nano material: " from top to bottom (Top-down) " and " from bottom to top (Bottom-up) ".Wherein, " from top to bottom " method adopts to obtain nano material from bulky crystal by the mode etching, corrode or grind; And " from bottom to top " method goes out to send control, assembling, the reaction various nano material of generation or nanostructured from atom or molecule, generally adopt chemical vapour deposition (CVD) (CVD, ChemicalVaporDeposition) method.
" from bottom to top " method is except the restriction (as high temperature, high pressure etc.) of itself, adopt the silicon nanowires prepared of the method to there is certain shortcoming in the preparation process of follow-up nano electron device, locate as being difficult to mobile, be difficult to the Ohmic contact that formed.On the contrary, " from top to bottom " method make use of current microelectronic processing technology, can realize batch production, makes preparation high density and high-quality nanometer integrated sensor in the future be called possibility.Therefore, " from top to bottom " method becomes the mainstream technology preparing silicon nanowires at present.
And, current " from top to bottom " method mainly utilizes chemistry etch techniques to form silicon nanowires, in this technical process, photoetching technique with high costs need be used, and several nano level photoetching technique can be realized at present and only have beamwriter lithography or nano impression, wherein, beamwriter lithography can realize the photoetching of 5 ~ 10nm, but its requirement is very high; And although nano impression can realize several nano level photoetching, its cost is too high.
Thus, how to obtain the nano thread structure of low cost, become the technical problem that current industry needs solution badly.
Summary of the invention
The object of the present invention is to provide a kind of preparation method of nano thread structure, to solve the problem that in prior art, the preparation cost of nano thread structure is too high.
For solving the problem, the present invention proposes a kind of preparation method of nano thread structure, and described nano thread structure is metal-semiconductor compounds nano wire, and the method comprises the steps:
Semiconductor substrate is provided, and forms dielectric layer, polycrystal semiconductor layer and insulating barrier successively on the semiconductor substrate;
Successively described insulating barrier and described polycrystal semiconductor layer are etched, remove insulating barrier and the polycrystal semiconductor layer of both sides;
At the deposited on sidewalls metallic film of described polycrystal semiconductor layer both sides, the metal in described metallic film spreads to described polycrystal semiconductor layer;
Remove the remaining metallic film of described polycrystal semiconductor layer sidewall surfaces;
Described polycrystal semiconductor layer is annealed, forms metal-semiconductor compounds nano wire in the sidewall surfaces of described polycrystal semiconductor layer.
Optionally, the method, after formation metal-semiconductor compounds nano wire, also comprises the step removing described insulating barrier and described polycrystal semiconductor layer.
Optionally, described metallic film is deposited on the sidewall of described polycrystal semiconductor layer both sides by PVD method.
Optionally, in the process of described PVD method depositing metal films, the ionization of target part is become ionic condition, makes it produce metal ion, and add the first bias voltage on described polycrystal semiconductor layer.
Optionally, described the ionization of target part is become ionic condition by add on described target second bias voltage realize.
Optionally, described first bias voltage is any one in Dc bias, AC bias or pulsed bias.
Optionally, described second bias voltage is any one in Dc bias, AC bias or pulsed bias.
Optionally, the width of described metal-semiconductor compounds nano wire is 2 ~ 11nm, and it is highly 10 ~ 20nm.
Optionally, described polycrystal semiconductor layer is polysilicon layer, and described metal-semiconductor compounds nano wire is metal silicide nano-wire.
Optionally, described polycrystal semiconductor layer is polycrystalline germanium layer, and described metal-semiconductor compounds nano wire is metal germanide nano wire.
Optionally, described metal-semiconductor compounds nano wire is reacted by metal and described polycrystal semiconductor layer and generates, and wherein, described metal is any one in nickel, cobalt, titanium, ytterbium, or nickel, cobalt, titanium, in ytterbium any one and mix platinum.
Optionally, tungsten and/or molybdenum is also mixed with in described metal.
Optionally, the underlayer temperature when the deposited on sidewalls metallic film of described polycrystal semiconductor layer both sides is 0 ~ 300 DEG C.
Optionally, the temperature of described annealing is 200 ~ 900 DEG C.
Optionally, described dielectric layer is any one in silica, silicon nitride or high-K dielectric layer.
Optionally, the method also comprises with described metal-semiconductor compounds nano wire for mask, by the step of described metal-semiconductor compounds nano wire Graphic transitions to next Rotating fields.
Compared with prior art, the preparation method of nano thread structure provided by the invention is by the sidewall surfaces depositing metal films in polycrystal semiconductor layer both sides, metal in described metallic film spreads to the sidewall surfaces of described polycrystal semiconductor layer, after annealed, metal-semiconductor compounds nano wire is formed in the sidewall surfaces of described polycrystal semiconductor layer, preparation method due to nano thread structure provided by the invention does not need to utilize high-resolution photoetching technique to form nano wire, has thus greatly saved preparation cost.
And described metal-semiconductor compounds nano wire can also as mask, by its nanostructured Graphic transitions to next Rotating fields, thus provide conveniently for the preparation of nano thread structure.
And the preparation method of nano thread structure provided by the invention, can also in the process of described PVD method depositing metal films, the ionization of target part is become ionic condition, it is made to produce metal ion, and the first bias voltage is added on described polycrystal semiconductor layer, by regulating the size of the ionization degree of described target and described first bias voltage, thus regulate the width of described metal-semiconductor compounds nano wire, the width-adjustable of nano thread structure prepared by the present invention.
Accompanying drawing explanation
The flow chart of the preparation method of the nano thread structure that Fig. 1 provides for the embodiment of the present invention;
The generalized section of the structure that each flow process of preparation method of the nano thread structure that Fig. 2 A to Fig. 2 G provides for the embodiment of the present invention is corresponding.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the preparation method to the nano thread structure that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only for object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of preparation method of nano thread structure is provided, the method is by the sidewall surfaces depositing metal films in polycrystal semiconductor layer both sides, metal in described metallic film spreads to the sidewall surfaces of described polycrystal semiconductor layer, after annealed, metal-semiconductor compounds nano wire is formed in the sidewall surfaces of described polycrystal semiconductor layer, preparation method due to nano thread structure provided by the invention does not need to utilize high-resolution photoetching technique to form nano wire, thus preparation cost has greatly been saved, and metal-semiconductor compounds nano wire prepared by the present invention can also as mask, by its nanostructured Graphic transitions to next Rotating fields, thus provide conveniently for the preparation of nano thread structure.
Please refer to Fig. 1, Fig. 2 A to Fig. 2 G, wherein, the flow chart of the preparation method of the nano thread structure that Fig. 1 provides for the embodiment of the present invention, the generalized section of the structure that each flow process of preparation method of the nano thread structure that Fig. 2 A to Fig. 2 G provides for the embodiment of the present invention is corresponding, composition graphs 1 and Fig. 2 A to Fig. 2 F, the preparation method of the nano thread structure that the embodiment of the present invention provides, wherein, described nano thread structure is metal-semiconductor compounds nano wire, and the method comprises the steps:
S101, provide Semiconductor substrate 100, and form dielectric layer 101, polycrystal semiconductor layer 102 and insulating barrier 103 successively in described Semiconductor substrate 100, as shown in Figure 2 A;
S102, successively described insulating barrier 103 and described polycrystal semiconductor layer 102 to be etched, remove insulating barrier and the polycrystal semiconductor layer of both sides, as shown in Figure 2 B;
S103, deposited on sidewalls metallic film 104 in described polycrystal semiconductor layer 102 both sides, as shown in Figure 2 C; Metal in described metallic film 104 spreads to described polycrystal semiconductor layer 102;
S104, remove the remaining metallic film 104 of described polycrystal semiconductor layer 102 sidewall surfaces; Particularly, wet method or dry etching is utilized to remove the remaining metallic film 104 of described polycrystal semiconductor layer 102 sidewall surfaces; Remove the section of structure after the remaining metallic film 104 of described polycrystal semiconductor layer 102 sidewall surfaces as shown in Figure 2 D, after described metal diffuses to described polycrystal semiconductor layer 102 sidewall surfaces, form the semiconductor lamella 105 containing metal in described polycrystal semiconductor layer 102 sidewall surfaces;
S105, described polycrystal semiconductor layer 102 to be annealed, form metal-semiconductor compounds nano wire 106 in the sidewall surfaces of described polycrystal semiconductor layer 102, as shown in Figure 2 E.
Further, the method, after formation metal-semiconductor compounds nano wire 106, also comprises the step removing described insulating barrier 103 and described polycrystal semiconductor layer 102; Remove the profile of the structure after described insulating barrier 103 and described polycrystal semiconductor layer 102 as shown in Figure 2 F.
Further, described metallic film 104 is deposited on the sidewall of described polycrystal semiconductor layer 102 both sides by PVD method.Further, in the process of described PVD method depositing metal films 104, the ionization of target part can also be selected to become ionic condition, make it produce metal ion, and add the first bias voltage on described polycrystal semiconductor layer 102; Wherein, described the ionization of target part is become ionic condition by add on described target second bias voltage realize; Further, described first bias voltage is any one in Dc bias, AC bias or pulsed bias, and described second bias voltage is any one in Dc bias, AC bias or pulsed bias.
By the ionization of target part is become ionic condition, it is made to produce metal ion, and the first bias voltage is added on described polycrystal semiconductor layer 102, described metal ion is made to accelerate to move to the sidewall of described polycrystal semiconductor layer 102, and enter the sidewall of described polycrystal semiconductor layer 102, thus making the metal ion of the sidewall diffusing to described polycrystal semiconductor layer 102 more, diffusion depth is darker, and thus the width of the final metal-semiconductor compounds nano wire 106 formed is widened; Therefore the width of metal-semiconductor compounds nano wire 106 that the embodiment of the present invention provides is adjustable.
It should be noted that; in one particular embodiment of the present invention; described the ionization of target part is become ionic condition by add on described target second bias voltage realize; but the present invention is not as limit, anyly a part of ionization of target is made to become the mode of ionic condition all within protection scope of the present invention.
Further, the width of described metal-semiconductor compounds nano wire 106 is 2 ~ 11nm, and it is highly 10 ~ 20nm; It should be noted that, if the ionization of target part is not become ionic condition, and on described polycrystal semiconductor layer 102, do not add the first bias voltage, the width of described metal-semiconductor compounds nano wire 106 is generally 2 ~ 8nm; And if the ionization of target part is become ionic condition, and on described polycrystal semiconductor layer 102, add the first bias voltage, then the width of described metal-semiconductor compounds nano wire 106 is generally 3 ~ 11nm; But the width of metal-semiconductor compounds nano wire 106 of the present invention is not as limit, according to the degree of target ionization and the size of the first bias voltage, described width is adjustable.In addition; why the height of described metal-semiconductor compounds nano wire 106 is decided to be 10 ~ 20nm; it is the restriction considering that described polycrystal semiconductor layer 102 both sides etch; under existing condition, the etching wanting described polycrystal semiconductor layer 102 both sides keeps vertical, and its height (thickness) is generally better at below 20nm; but the present invention is not as limit; as long as adopt nano thread structure prepared by the present invention, no matter it is highly how many, all within protection scope of the present invention.
Further, described polycrystal semiconductor layer 102 is polysilicon layer, and described metal-semiconductor compounds nano wire 106 is metal silicide nano-wire.
Further, described polycrystal semiconductor layer 102 is polycrystalline germanium layer, and described metal-semiconductor compounds nano wire 106 is metal germanide nano wire.
Further, described metal-semiconductor compounds nano wire 106 reacts generation by metal and described polycrystal semiconductor layer 102, and wherein, described metal is any one in nickel, cobalt, titanium, ytterbium, or nickel, cobalt, titanium, in ytterbium any one and mix platinum; Mixing platinum is because pure nickle silicide poor stability under the high temperature conditions, or occurs that film thickness becomes uneven and lumps, or generates the high nickel disilicide NiSi of resistivity
2, have a strong impact on the performance of device, therefore, in order to the nickle silicide that slows down the speed of growth and there is caking when preventing thin layer of nickel suicide from running into high temperature or form nickel disilicide, a certain proportion of platinum can be mixed in nickel; Mix platinum in other metal and do similar explanation.
Further, tungsten and/or molybdenum is also mixed with in described metal; To control nickle silicide further or to mix the growth of platinum nickle silicide and the diffusion of nickel/platinum, and increase nickle silicide or mix the stability of platinum nickle silicide; Tungsten is mixed and/or molybdenum does similar explanation in other metal.
Certainly, the metal in the present invention is not limited with the concrete metal of above-mentioned citing, and other can react with semi-conducting material, produces the metal of metal-semiconductor compounds all within protection scope of the present invention.
Further, the underlayer temperature when the deposited on sidewalls metallic film 104 of described polycrystal semiconductor layer 102 both sides is 0 ~ 300 DEG C; This is because concerning metallic nickel, depositing temperature to cause more than 300 DEG C while the nickel diffusion of excess nickel can and polycrystal semiconductor layer 102 (such as polysilicon) directly reaction formation nickle silicide, cause the failure of THICKNESS CONTROL; Under this specified temp, nickel can spread to polysilicon sidewall through polysilicon sidewall surface, this diffusion has self-saturation characteristic: nickel carries out spreading to polysilicon sidewall and only occurs in the skin layer of silicon, form the thin layer nickel of certain silicon/nickle atom ratio, the thickness of this thin layer nickel is relevant with underlayer temperature during deposit, and temperature is higher, and the thickness of this thin layer nickel is also larger, at room temperature, the equivalent nickel thickness of this thin layer nickel is 2 ran.
Further, the temperature of described annealing is 200 ~ 900 DEG C.
Further, described dielectric layer is any one in silica, silicon nitride or high-K dielectric layer.
Further, the method also comprises with described metal-semiconductor compounds nano wire 106 for mask, by the step of described metal-semiconductor compounds nano wire 106 Graphic transitions to next Rotating fields; Particularly, with described metal-semiconductor compounds nano wire 106 for mask, its next Rotating fields is etched, thus by the Graphic transitions of described metal-semiconductor compounds nano wire 106 to next Rotating fields; Complete the section of structure after this step as shown in Figure 2 G.
It should be noted that, although the present invention utilizes polycrystal semiconductor layer and metal reaction to form metal-semiconductor compounds nano wire, but the present invention is not as limit, in actual use, single-crystal semiconductor layer and metal reaction can also be utilized to form metal-semiconductor compounds nano wire, such as, if the Semiconductor substrate adopted is germanium (GOI) on silicon (SOI) or insulating barrier on insulating barrier, top layer due to SOI and GOI is single-crystal semiconductor layer, the single-crystal semiconductor layer in described SOI or GOI then can be utilized to replace the polycrystal semiconductor layer in the embodiment of the present invention and metal reaction to form metal-semiconductor compounds nano wire.In sum, the invention provides a kind of preparation method of nano thread structure, the method is by the sidewall surfaces depositing metal films in polycrystal semiconductor layer both sides, metal in described metallic film spreads to the sidewall surfaces of described polycrystal semiconductor layer, after annealed, metal-semiconductor compounds nano wire is formed in the sidewall surfaces of described polycrystal semiconductor layer, preparation method due to nano thread structure provided by the invention does not need to utilize high-resolution photoetching technique to form nano wire, thus preparation cost has greatly been saved, and metal-semiconductor compounds nano wire prepared by the present invention can also as mask, by its nanostructured Graphic transitions to next Rotating fields, thus provide conveniently for the preparation of nano thread structure.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (14)
1. a preparation method for nano thread structure, is characterized in that, described nano thread structure is metal-semiconductor compounds nano wire, and the method comprises the steps:
Semiconductor substrate is provided, and forms dielectric layer, polycrystal semiconductor layer and insulating barrier successively on the semiconductor substrate;
Successively described insulating barrier and described polycrystal semiconductor layer are etched, remove insulating barrier and the polycrystal semiconductor layer of both sides;
At the deposited on sidewalls metallic film of described polycrystal semiconductor layer both sides, the metal in described metallic film spreads to described polycrystal semiconductor layer; Wherein, described metallic film is deposited on the sidewall of described polycrystal semiconductor layer both sides by PVD method, in the process of described PVD method depositing metal films, the ionization of target part become ionic condition, make it produce metal ion, and add the first bias voltage on described polycrystal semiconductor layer;
Remove the remaining metallic film of described polycrystal semiconductor layer sidewall surfaces;
Described polycrystal semiconductor layer is annealed, forms metal-semiconductor compounds nano wire in the sidewall surfaces of described polycrystal semiconductor layer.
2. the preparation method of nano thread structure as claimed in claim 1, is characterized in that, the method, after formation metal-semiconductor compounds nano wire, also comprises the step removing described insulating barrier and described polycrystal semiconductor layer.
3. the preparation method of nano thread structure as claimed in claim 1, is characterized in that, describedly the ionization of target part is become ionic condition to realize by adding the second bias voltage on described target.
4. the preparation method of nano thread structure as claimed in claim 3, it is characterized in that, described first bias voltage is any one in Dc bias, AC bias or pulsed bias.
5. the preparation method of nano thread structure as claimed in claim 3, it is characterized in that, described second bias voltage is any one in Dc bias, AC bias or pulsed bias.
6. the preparation method of nano thread structure as claimed in claim 1, it is characterized in that, the width of described metal-semiconductor compounds nano wire is 2 ~ 11nm, and it is highly 10 ~ 20nm.
7. the preparation method of nano thread structure as claimed in claim 1, it is characterized in that, described polycrystal semiconductor layer is polysilicon layer, and described metal-semiconductor compounds nano wire is metal silicide nano-wire.
8. the preparation method of nano thread structure as claimed in claim 1, it is characterized in that, described polycrystal semiconductor layer is polycrystalline germanium layer, and described metal-semiconductor compounds nano wire is metal germanide nano wire.
9. the preparation method of nano thread structure as claimed in claim 7 or 8, it is characterized in that, described metal-semiconductor compounds nano wire is reacted by metal and described polycrystal semiconductor layer and generates, wherein, described metal is any one in nickel, cobalt, titanium, ytterbium, or nickel, cobalt, titanium, in ytterbium any one and mix platinum.
10. the preparation method of nano thread structure as claimed in claim 9, is characterized in that, be also mixed with tungsten and/or molybdenum in described metal.
The preparation method of 11. nano thread structures as claimed in claim 1, is characterized in that, the underlayer temperature when the deposited on sidewalls metallic film of described polycrystal semiconductor layer both sides is 0 ~ 300 DEG C.
The preparation method of 12. nano thread structures as claimed in claim 1, is characterized in that, the temperature of described annealing is 200 ~ 900 DEG C.
The preparation method of 13. nano thread structures as claimed in claim 1, it is characterized in that, described dielectric layer is any one in silica, silicon nitride or high-K dielectric layer.
The preparation method of 14. nano thread structures as claimed in claim 1, is characterized in that, the method also comprises with described metal-semiconductor compounds nano wire for mask, by the step of described metal-semiconductor compounds nano wire Graphic transitions to next Rotating fields.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110106336.2A CN102229421B (en) | 2011-04-26 | 2011-04-26 | The preparation method of nano thread structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110106336.2A CN102229421B (en) | 2011-04-26 | 2011-04-26 | The preparation method of nano thread structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102229421A CN102229421A (en) | 2011-11-02 |
| CN102229421B true CN102229421B (en) | 2016-01-20 |
Family
ID=44842044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110106336.2A Expired - Fee Related CN102229421B (en) | 2011-04-26 | 2011-04-26 | The preparation method of nano thread structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102229421B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102655176B (en) * | 2012-05-10 | 2015-09-09 | 复旦大学 | Capacitor with nano thread structure and preparation method thereof |
| CN104528634B (en) * | 2014-12-16 | 2017-01-18 | 南京工业大学 | Side wall forming manufacturing method of nano structure |
| CN113130648B (en) * | 2019-12-30 | 2022-05-27 | 有研工程技术研究院有限公司 | Tumor marker sensor based on fin field effect transistor manufacturing process |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194768B1 (en) * | 1998-10-23 | 2001-02-27 | Advanced Micro Devices, Inc. | High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure |
| CN101207137A (en) * | 2006-12-22 | 2008-06-25 | 中国科学院物理研究所 | Material with metal silicide nanostructure and method for making the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764058B (en) * | 2009-12-31 | 2013-07-31 | 复旦大学 | Method for forming ultrathin controllable metal silicide |
-
2011
- 2011-04-26 CN CN201110106336.2A patent/CN102229421B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194768B1 (en) * | 1998-10-23 | 2001-02-27 | Advanced Micro Devices, Inc. | High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure |
| CN101207137A (en) * | 2006-12-22 | 2008-06-25 | 中国科学院物理研究所 | Material with metal silicide nanostructure and method for making the same |
Non-Patent Citations (1)
| Title |
|---|
| Novel method of producing ultrasmall platinum silicide gate electrodes;P. H. Woerlee 等;《Applied Physics Letters》;19851001;第47卷(第7期);第700-702页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102229421A (en) | 2011-11-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI253175B (en) | FinFET transistor device on SOI and method of fabrication | |
| Yin et al. | Vertical sandwich gate-all-around field-effect transistors with self-aligned high-k metal gates and small effective-gate-length variation | |
| CN102074584B (en) | Air-gap grapheme transistor and manufacturing method thereof | |
| US7999251B2 (en) | Nanowire MOSFET with doped epitaxial contacts for source and drain | |
| TW202016985A (en) | Method of forming two-dimensional material layer, field effect transistor and fabricating method thereof | |
| TWI248651B (en) | Method for reducing the contact resistance of the connection regions of a semiconductor device | |
| US9059274B2 (en) | Replacement gate self-aligned carbon nanostructure transistor | |
| US20110001169A1 (en) | Forming uniform silicide on 3d structures | |
| CN103503147A (en) | Graphene nanoribbons and carbon nanotubes fabricated from SiC fins or nanowire templates | |
| WO2012146019A1 (en) | Preparation method of nano mos device and nano mos device | |
| US20110169105A1 (en) | Semiconductor device and method for manufacturing the same | |
| CN102229421B (en) | The preparation method of nano thread structure | |
| KR101647324B1 (en) | Non-planar transistor fin fabrication | |
| CN102945791B (en) | A kind of preparation method of silicon nanowire array | |
| US20150376778A1 (en) | Graphene growth on sidewalls of patterned substrate | |
| TW579548B (en) | Semiconductor device having gate with negative slope and method for manufacturing the same | |
| CN105742345A (en) | Tunneling field-effect transistor and preparation method therefor | |
| CN107039335A (en) | The forming method of semiconductor structure | |
| Hållstedt et al. | Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs | |
| US8101525B2 (en) | Method for fabricating a semiconductor device having a lanthanum-family-based oxide layer | |
| WO2012122787A1 (en) | Method for manufacturing metal-semiconductor compound thin-film | |
| JP2011512668A (en) | Single-electron transistor operating at room temperature and method for manufacturing the same | |
| WO2012146018A1 (en) | Preparation method of nano mos device and nano mos device | |
| Rossi et al. | Performance of vertical gate-all-around nanowire p-MOS transistors determined by boron depletion during oxidation | |
| Zhang et al. | A novel self-aligned process for platinum silicide nanowires |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160120 Termination date: 20210426 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |