CN101206363B - Electrooptic device and electronic device - Google Patents

Abstract

The present invention relates to an electrooptic device and electronic equipment. The electrooptic device comprises: data lines(6a) and scanning lines (11) formed over a substrate (10); pixel electrodes (9a) corresponding to the intersections of the data lines and the scanning lines; transistors disposed in the intersection areas corresponding to the intersections in a non-open area, the transistors each including (i) a semiconductor layer disposed in a layer different from the scanning lines, the semiconductor layer has a channel region extending in Y direction in which the data lines extend, and (ii) a gate electrode is disposed in a layer on the opposite side of the semiconductor layer than the scanning lines, the gate electrode overlaps with the channel region; and a first insulating layer is between the semiconductor layer and the scanning lines, the first insulating layer has a contact hole (810) for electrically connecting the gate electrode and the scanning line, the contact hole having a first portion (811) located beside the semiconductor layer of the corresponding transistor in plan view with respect to the substrate and that extends in the Y direction and a second portion that overlaps with part of a corresponding scanning line and that extends in a second direction in which the scanning lines extend.

Description

Electro-optical device and electronic equipment

Technical field

For example the present invention relates to, electro-optical device such as liquid-crystal apparatus and have this electro-optical device, for example, the technical field of the electronic equipment of liquid crystal projection apparatus etc.

Background technology

As the liquid-crystal apparatus of an example of this electro-optical device, direct viewing escope not only for example, and also is general as the optical modulator component (light valve) of projection type image display apparatus.Particularly under the situation of projection type image display apparatus, because the high light incident liquid crystal light valve that light source sends, photomask is set in liquid crystal light valve, as the light-blocking member that blocks incident light, avoid because the thin film transistor (TFT) (TFT:Thin Film Transistor) of this light in liquid crystal light valve causes leakage current increase and misoperation etc.Aspect such light-blocking member or photomask, for example, No. 3356429 communique of patent (hereinafter referred to as patent documentation 1) discloses a kind of technology, by in the grid wiring of the upper layer side configuration of the semiconductor layer that constitutes TFT, the bottom surface photomask of the lower layer side configuration of this grid wiring and semiconductor layer is connected the part that is provided with in the contact hole of usefulness, improves the shade function to TFT.

But in patent documentation 1 disclosed technology, grid wiring is connected the contact hole of usefulness with the bottom surface photomask, sees in the plane, forms the rectangular shape that has along data line.Therefore, such technical matters is arranged, promptly along with the high apertureization that this electro-optical device is required, wiring width narrows down, and probably is difficult to fully guarantee to form the area of contact hole, and contact resistance increases.

On the other hand, this electro-optical device possesses pixel electrode, selects the sweep trace, data line of the driving usefulness of this pixel electrode and switches the TFT of the element of usefulness as pixel on substrate, be configured and can carry out driven with active matrix.In addition, be purpose with high-contrastization etc., between TFT and pixel electrode, capacity cell is set sometimes.On the substrate with the textural element more than the high density fabrication, make every effort to improve the miniaturization of aperture ratio of pixels and device.

Wherein particularly, capacity cell wishes that electric capacity is big as far as possible, but in contrast, wishes to design to such an extent that do not sacrifice pixel aperture ratio.Therefore, for example, open in the 2005-115104 communique (hereinafter referred to as patent documentation 2) the spy and to disclose so a kind of technology, promptly form capacity cell by bottom surface and side in the substrate upper recess, when guaranteeing high aperture, increase the electric capacity of this capacity cell.

Above-mentioned capacity cell also can be given the TFT shading electrode double as photomask as the inscape of this capacity cell.For example, in above-mentioned patent documentation 2, the technology that reduces the incident of semiconductor layer light with capacity cell is disclosed.

But, if adopt patent documentation 2 disclosed technology, individual technical matters is arranged on manufacturing process, promptly forming the recess that capacity cell uses must cause manufacturing process complicated with the independent operation making that is independent of the operation that forms other inscapes on substrate.In addition, along with further raising aperture opening ratio and equipment miniaturization, the more difficult technical matters of guaranteeing to form the area of capacity cell is arranged.

Summary of the invention

The present invention for example forms in view of the above problems, purpose provides a kind of raising aperture opening ratio that is suitable for, when can reduce the generation of light leakage current among the TFT, can realize that each layer beyond the gate electrode of TFT and this gate electrode go up the electro-optical device that is electrically connected good between the sweep trace of configuration and have the electronic equipment of this electro-optical device.In addition, it is a kind of when keeping high aperture and can increasing the memory capacitance capacity that purpose is to provide, and can reduce the generation of light leakage current among the TFT, can show the electro-optical device of high-quality image and have the electronic equipment of this electro-optical device.

According to the 1st electro-optical device of the present invention,, on substrate, possess cross one another data line and sweep trace in order to address the above problem; Pixel electrode, corresponding setting with the point of crossing of this data line and sweep trace; And transistor, be arranged in the intersection region corresponding in the non-open area spaced apart from each other, the open area of pixel with above-mentioned point of crossing, comprise: (i) semiconductor layer, across the 1st dielectric film, be configured on the layer that differs from one another with above-mentioned sweep trace, form the long channel region of raceway groove that has along the 1st direction of above-mentioned data line extension, (ii) gate electrode, with respect to this semiconductor layer, be configured on the layer of an opposite side with above-mentioned sweep trace, overlapping with above-mentioned channel region; Wherein, on above-mentioned the 1st dielectric film, be formed for being electrically connected the contact hole of above-mentioned gate electrode and above-mentioned sweep trace, it sees to have on the aforesaid substrate plane: part 1 prolongs along above-mentioned the 1st direction in above-mentioned semiconductor layer side; And part 2, overlapping with the part of above-mentioned sweep trace, and prolong along the 2nd direction that above-mentioned sweep trace extends.

Employing is according to the 1st electro-optical device of the present invention, and when its work, sweep signal offers transistorized gate electrode successively through sweep trace, and picture signal offers transistorized source electrode through data line, makes picture signal offer pixel electrode.Like this, just can for example be arranged to display image in the rectangular pixel region (or be called " image display area ") corresponding to the point of crossing of data line and sweep trace at a plurality of pixel electrodes, that is, the image that just may carry out so-called active matrix mode shows.

Wherein, sweep trace, data line and transistor are seen on the plane of substrate, be arranged on a pixel (promptly, pixel corresponding to pixel electrode) in the non-open area spaced apart from each other, open area (that is, on each pixel, allowing) in fact to showing the zone of contributive transmittance or reflection.That is, these sweep traces, data line and transistor are not arranged on the open area of each pixel, and are arranged in the non-open area, make it not hinder demonstration.

Transistor is arranged in the intersection region corresponding with the point of crossing of data line and sweep trace in the non-open area (that is, being arranged on all or part of of intersection region), comprises semiconductor layer with channel region and the gate electrode that is overlapped in channel region.

On the lit-par-lit structure on the substrate, semiconductor layer is configured in the layer that differs from one another with sweep trace and goes up (that is, being configured in the lower floor or the upper strata of sweep trace across the 1st dielectric film) across the 1st dielectric film.Channel region, the raceway groove with the 1st direction of extending along data line (the multi-strip scanning line direction of arranging in other words, that is, Y direction) is long.That is, semiconductor layer typically forms along the 1st direction and extends.

Gate electrode with respect to semiconductor layer, is configured on the layer of an opposite side with sweep trace on the lit-par-lit structure on the substrate.In this case, should on electric, connect gate electrode and sweep trace at the square one-tenth contact hole of semiconductor layer side.That is, be configured at sweep trace under the situation of lower layer side of semiconductor layer, gate electrode for example is configured in the upper layer side of semiconductor layer across gate insulating film, and in other words transistor forms the top gate type transistor.On the other hand, be configured at sweep trace under the situation of upper layer side of semiconductor layer, gate electrode for example is configured in the lower layer side of semiconductor layer across gate insulating film, and in other words transistor forms the bottom gate type transistor.

On the lit-par-lit structure that is configured on the substrate, gate electrode and sweep trace connect by contact hole that form or perforate on the dielectric film between gate electrode and the sweep trace on electric.Promptly, for example, be configured at sweep trace under the situation of lower layer side of semiconductor layer (promptly, across the upper layer side of the 1st dielectric film at sweep trace, under the situation of transistor as the top gate type configuration), gate electrode extends setting with the overlapping part of channel region in this gate electrode in contact hole, thereby connects gate electrode and sweep trace on electric.Perhaps, for example, be configured at sweep trace under the situation of upper layer side of semiconductor layer (promptly, transistor is across the lower layer side of the 1st dielectric film at sweep trace, form under the situation of bottom gate type), sweep trace extends setting from the main line part that extends along the 2nd direction in contact hole, thereby connects gate electrode and sweep trace on electric.No matter under any situation, in contact hole, all form the part of gate electrode or sweep trace.In addition, also can be configured connector (plug), on electric, connect gate electrode and sweep trace by in contact hole, using the conductive material all different to form with gate electrode and sweep trace.

In the present invention, particularly, connect the contact hole that gate electrode and sweep trace are used on electric, on plane on the substrate, see, have in the semiconductor layer side part 1 that prolongs along the 1st direction, the 2nd direction overlapping and that extend along sweep trace is (in other words with the part of sweep trace, the direction that intersects with the 1st direction, perhaps many data lines direction of arranging promptly, directions X) part 2 that prolongs.That is, contact hole is formed the ditch (perhaps contact ditch) of flat shapes such as for example having L word shape or T word shape on the 1st dielectric film by for example etching etc. by part 1 and part 2.

Thereby, can when keeping high aperture, reduce the contact resistance between gate electrode and sweep trace.Promptly, in the present invention, particularly, because contact hole has the 1st and part 2, the situation that for example has flat shapes such as circle, square, rectangle with the supposition contact hole is compared, and can enlarge the area in this contact hole zone that forms in limited non-open area.Thereby, can in the resistance that reduces between gate electrode and sweep trace, improve aperture opening ratio.In addition, so-called " aperture opening ratio " represents the ratio that the open area accounts in the whole zone (that is, the total of open area and non-open area) corresponding to each pixel here, and aperture opening ratio is big more, and the liquid-crystal apparatus display performance is high more.

In addition, in the present invention, particularly as mentioned above, the part 1 of contact hole prolongs along the 1st direction in the semiconductor layer side.That is, part 1 separates the distance of regulation in the side of the semiconductor layer that extends along the 1st direction, forms along the strip of the 1st direction.Thereby the gate electrode that forms in part 1 or the part of sweep trace are seen on three-dimensional, along semiconductor layer, form wall shape occulter.Thereby, can use part 1 (part of gate electrode that forms in the part 1 or sweep trace or rather) to block light (that is, having) along the light of the component of real estate for the semiconductor layer oblique incidence.That is, can strengthen the light-proofness that blocks the light of semiconductor layer oblique incidence with the part 1 that forms the occulter that is configured near for example wall shape the semiconductor layer.As a result, can in image shows, reduce flicker and pixel irregular.

As mentioned above, if adopt according to the 1st electro-optical device of the present invention, have the 1st and part 2 owing to connect contact hole that sweep trace and gate electrode use on electric, can improve aperture opening ratio, when reducing the generation of light leakage current in the transistor, can realize good being electrically connected between transistorized gate electrode and sweep trace.The high-quality image that just may become clear as a result,, minimizing is glimmered and pixel is irregular shows.

In a kind of form according to the 1st electro-optical device of the present invention, above-mentioned gate electrode has: overlap the main part on the above-mentioned channel region; With from main part, see that on the aforesaid substrate plane to extend the gate electrode extension of setting with the overlapping mode of above-mentioned contact hole, above-mentioned sweep trace has: the main line part of extending along above-mentioned the 2nd direction; With from this main line partly, on the aforesaid substrate plane, see, to extend the sweep trace extension of setting with the overlapping mode of above-mentioned part 1.

If adopt this form,, when can be reliably between gate electrode and sweep trace, connecting on electric, can strengthen light-proofness reliably to semiconductor layer then owing to can in contact hole, form gate electrode extension or sweep trace extension.

In another form according to the 1st electro-optical device of the present invention, above-mentioned semiconductor layer has: the 2nd interface that is connected electrically to the data line side source-drain area of above-mentioned data line, the pixel electrode side source-drain area that is connected electrically to pixel electrodes, the 1st interface that forms and forms between above-mentioned channel region and pixel electrodes side source-drain area between above-mentioned channel region and above-mentioned data line side source-drain area, above-mentioned part 1 is along at least one square one-tenth in the above-mentioned the 1st and the 2nd interface.

If adopt this form, then part 1 (or rather, the gate electrode that forms in part 1 or the part of sweep trace) is seen on 3 dimensions, and at least one for example, forms the occulter of wall shape in the 1st and the 2nd interface in the semiconductor layer.Thereby, can block light with part 1 at least one oblique incidence in the 1st in semiconductor layer and the 2nd interface.That is, for example can be used near the configuration of semiconductor layer, form the part 1 of the occulter of wall shape, strengthen the light-proofness that blocks the light of semiconductor layer oblique incidence.

In addition, be in the zone of the bound fraction formation of channel region and data line side source-drain area according to " the 1st interface " of the present invention, be the zone that on the bound fraction of channel region and pixel electrode side source-drain area, forms according to " the 2nd interface " of the present invention.Promptly, the the 1st and the 2nd interface is represented, for example, transistor for example forms NPN type or PNP transistor (promptly, N channel-type or P channel transistor) situation under the PN junction district and transistor have LDD structure situation under the LDD district (that is, for example, impurity by ion implantation etc. injects the impurity injection rate IR zone littler than source-drain area in semiconductor layer).

Under the form of above-mentioned part 1 at least one formation in the 1st and the 2nd interface, above-mentioned contact hole is seen on the aforesaid substrate plane, form in the both sides of above-mentioned semiconductor layer, above-mentioned part 1 also can be arranged on above-mentioned at least one both sides.

In this case, the part 1 of contact hole (or rather, the gate electrode that in part 1, forms or the part of sweep trace), the both sides of at least one form for example wall shape occulter in the 1st and the 2nd interface in semiconductor layer.Thereby, at least one interface, can block from the light of both sides oblique incidence.Thereby, can reduce the light leakage current in the transistor reliablely.

In addition, because contact hole in each self-forming of the both sides of semiconductor layer, can reduce the resistance between gate electrode and sweep trace reliablely.

Under the form of above-mentioned part 1 at least one formation in the 1st and the 2nd interface, above-mentioned part 1 is seen on the aforesaid substrate plane, also can be provided with along above-mentioned the 2nd interface.

In this case, the part 1 of contact hole (or rather, the gate electrode that forms in part 1 or the part of sweep trace) forms for example wall shape occulter along the 2nd interface.Wherein,, in theory, during transistor work,, compare, the trend of relatively easier generation light leakage current is arranged, even also obtained proof experimentally with the 1st interface in the 2nd interface according to present inventor's research.Under this form, by the part 1 of contact hole, block the light in incident semiconductor layer the 2nd interface reliablely, thereby just may further reduce the light quantity in incident semiconductor layer the 2nd interface.The result is just to reduce the generation of light leakage current in the transistor more effectively.

Under the form of above-mentioned part 1 at least one square one-tenth in the 1st and the 2nd interface, the above-mentioned the 1st and the 2nd interface also can be the LDD district.

In this case, transistor has the LDD structure.Thereby, during the transistor inoperative, the cut-off current that flows through data line side source-drain area and pixel electrode side source-drain area reduces, and the electric field of drain electrode end relaxes can reduce the transistor operate in saturation time, and the threshold value that can suppress to cause because of the hot carrier phenomenon rises, and conducting electric current that (relating to the problem on the relevant reliability of characteristics of transistor deterioration) cause descends and cut-off leakage current rises.

Under another form according to the 1st electro-optical device of the present invention, above-mentioned sweep trace is configured in the lower layer side of above-mentioned semiconductor layer.

If adopt this form, sweep trace is configured in the transistorized lower layer side of top gate type across the 1st dielectric film.Thereby sweep trace can play the effect of blocking the downside photomask or the back side photomask of light echo to transistor.That is,, in substrate in backside reflection and the compound plate formula projector etc., can send light that passes combining optical etc. as other electro-optical devices, go into the back light of injection device from substrate-side for transistor blocks by sweep trace as the downside photomask.Thereby, can reduce the generation of light leakage current in the transistor reliablely.

In another form according to the 1st electro-optical device of the present invention, above-mentioned gate electrode and above-mentioned sweep trace comprise the light-proofness conductive material.

If adopt this form, gate electrode and sweep trace can work to block the photomask of the transistorized light of incident reliably.Particularly, can make the part of gate electrode or sweep trace, the part a kind that rises reliably at contact hole for example forms the function of wall shape occulter.Thereby, can reduce the generation of light leakage current in the transistor reliablely

In another form according to the 1st electro-optical device of the present invention, the width of above-mentioned part 1 is narrower than the width of above-mentioned part 2.

If adopt this form, the width of part 1, since also narrower than the width of part 2, can cause the increase (in other words aperture opening ratio decline) of non-open area owing to forming part 1 hardly.In addition, because the width of part 2 is wideer than the width of part 1, can be reliably by the contact resistance between part 2 minimizing gate electrode and sweep trace.That is, when keeping high aperture opening ratio reliably, mainly can strengthen part 1 to transistorized light-proofness, can be mainly with the contact resistance between part 2 minimizing gate electrode and sweep trace.

In another form according to the 1st electro-optical device of the present invention, also have across the 2nd dielectric film, be configured in above-mentioned transistorized upper layer side, the memory capacitance that in above-mentioned non-open area, forms, this memory capacitance forms in the mode that covers the recess that produces on above-mentioned the 2nd dielectric film upper layer side surface because of above-mentioned contact hole, possesses the concavity part that has along the concavity section shape of recess surface.

If adopt this form, be configured in transistorized upper layer side across the 2nd dielectric film in the lit-par-lit structure of memory capacitance on substrate.Memory capacitance in addition in non-open area, typically covers channel region and for example is adjacent, and LDD district etc. are seen on plane on the substrate, form partly overlappingly with semiconductor layer at least.Memory capacitance, typically, comprise light-proofness conducting film (more particularly, at least one that constitutes in a pair of capacitance electrode of memory capacitance for example formed by the light-proofness conducting film of metal film etc.), work to block built-in photomask from the transistorized light of upper layer side incident.Thereby, can reduce the generation of light leakage current in the transistor.

Under this form, particularly, memory capacitance forms on the upper layer side surface of the 2nd dielectric film, makes it to cover the recess that produces because of contact hole, possesses the concavity part that has along the concavity section shape of this recess surface.

That is, on the 1st dielectric film of the lower layer side that is configured in the 2nd dielectric film, as mentioned above, because the formation of contact hole, on the upper layer side surface of the 2nd dielectric film, for example, roughly the inwall along contact hole produces recess.Memory capacitance forms to such an extent that cover this recess, thereby its part is formed in recess, possesses the concavity part that has along the concavity section shape of recess surface.Concavity part typically wall portion and the bottom in the recess forms.

Thereby memory capacitance is by having the concavity part, and capacitance increases.Thereby, can improve the current potential retention performance in the pixel electrode.In other words, the situation (that is, the situation that memory capacitance only forms in the plane) that does not have concavity part with memory capacitance is compared, and the memory capacitance with capacitance of realizing the desired display performance of goods can be made on the substrate in the narrow region.Thereby it is irregular to reduce flicker and the pixel of image in showing, in addition, and miniaturization that can implement device.

In addition, because recess is owing to contact hole produces, recess (reaching concavity part) has the flat shape roughly the same with the flat shape of contact hole.In other words, the concavity part is seen on plane on the substrate, has in the semiconductor layer side part that prolongs along the 1st direction and the part overlapping and that prolong along the 2nd direction that sweep trace extends with the part of sweep trace.Thereby, can easily partly be configured in concavity in the non-open area, cause the decline of aperture opening ratio hardly, can increase the capacitance of memory capacitance.

In addition, recess is owing to contact hole produces, so almost or fully can not cause the complicated of manufacturing process or increase.

As mentioned above, if adopt this form, when former state is kept the capacitance that high aperture can increase memory capacitance, can reduce the generation of light leakage current among the TFT.The result is just may produce high-quality image and show.

Have under the form of above-mentioned memory capacitance, above-mentioned semiconductor layer has the data line side source-drain area that is connected to above-mentioned data line on electric, be connected to the 2nd interface that forms between the 1st interface that forms between the pixel electrode side source-drain area of pixel electrodes, above-mentioned channel region and the above-mentioned data line side source-drain area and above-mentioned channel region and the pixel electrodes side source-drain area on electric, above-mentioned memory capacitance is seen on the aforesaid substrate plane, also can be configured overlapping with above-mentioned the 2nd interface at least.

In this case, can block the 2nd interface of comparing the trend that easier generation light leakage current is arranged with the 1st interface reliablely.Thereby, just may reduce the generation of light leakage current in the transistor more effectively.

Have under the form of above-mentioned memory capacitance, above-mentioned memory capacitance also can be configured and comprise the light-proofness conductive material.

In this case, can make memory capacitance work to block the photomask of the transistorized light of incident reliably.

Above-mentioned memory capacitance at least with the overlapping form in the 2nd interface under, above-mentioned memory capacitance also can be configured to have along above-mentioned the 1st direction extends and covers the 1st capacitive part in above-mentioned the 1st interface and cover width 2nd capacitive part wideer than above-mentioned the 1st capacitive part of above-mentioned the 2nd interface and above-mentioned the 2nd direction.

In this case, in memory capacitance, cover the 2nd capacitive part in the 2nd interface, construct to such an extent that make the width of the 2nd direction wideer than the 1st capacitive part that covers the 1st interface.That is, the 2nd capacitive part is constructed, and for the semiconductor layer that extends along for example Y direction, for example, the width of directions X is wideer than the 1st capacitive part.Thereby, compare with the light in incident the 1st interface, can block the light in incident the 2nd interface more reliably, and the trend with relative easier generation light leakage current is compared with the 1st interface in the 2nd interface.That is, can improve (that is, strengthening) to the light-proofness that blocks the light that arrives the 2nd interface must be higher than the light-proofness that blocks the light that arrives the 1st interface.

In order to address the above problem,, on substrate, possess cross one another data line and sweep trace according to the 2nd electro-optical device of the present invention; Pixel electrode, corresponding setting with the point of crossing of this data line and sweep trace; And transistor, be arranged in the intersection region corresponding in the non-open area spaced apart from each other, the open area of pixel with above-mentioned point of crossing, comprise: (i) semiconductor layer, across the 1st dielectric film, be configured on the layer that differs from one another with above-mentioned sweep trace, form the long channel region of raceway groove that has along the direction of above-mentioned data line extension, (ii) gate electrode, with respect to this semiconductor layer, be configured on the layer of an opposite side with above-mentioned sweep trace, overlapping with above-mentioned channel region; Wherein, on above-mentioned the 1st dielectric film, be formed for being electrically connected the contact hole of above-mentioned gate electrode and above-mentioned sweep trace, it sees to have on the aforesaid substrate plane: part 1, and the direction of extending along above-mentioned sweep trace in above-mentioned semiconductor layer side prolongs; And part 2, overlapping and prolong with the part of above-mentioned data line along the direction that above-mentioned data line extends.

If adopt, when its work and above-mentioned roughly the same, can in pixel region, carry out image and show according to the 1st electro-optical device of the present invention according to the 2nd electro-optical device of the present invention.

Transistor is included in and is arranged on the intersection region corresponding with data line and sweep trace point of crossing (that is, be arranged on intersection region all or part of) in the non-open area, have the semiconductor layer of channel region and overlap gate electrode on the channel region.

In the lit-par-lit structure on substrate, semiconductor layer is configured in the layer that differs from one another with sweep trace across the 1st dielectric film and goes up (that is, across the 1st dielectric film, being configured in the lower layer side or the upper layer side of sweep trace).Channel region, the raceway groove with the direction of extending along sweep trace (many directions that data line is arranged in other words, that is, directions X) is long.That is, semiconductor layer typically forms the direction extension of extending along sweep trace.

In the lit-par-lit structure on substrate, with respect to semiconductor layer, gate electrode is configured on the layer of an opposite side with sweep trace.In this case, should on electric, connect gate electrode and sweep trace at the square one-tenth contact hole of semiconductor layer side.

In the lit-par-lit structure on substrate, (perhaps this dielectric film and for example gate insulating film) contact hole that form or perforate connects gate electrode and sweep trace on the dielectric film between gate electrode and the sweep trace on electric through being configured in.

In the present invention, particularly, connect the contact hole that gate electrode and sweep trace are used on electric, on plane on the substrate, see, have the part 1 that the direction of extending along sweep trace in the semiconductor layer side prolongs; The part 2 that prolongs with a part that overlaps onto data line and the direction of extending (in other words the multi-strip scanning line direction of arranging promptly, Y direction) along data line.That is, contact hole is formed by for example etching etc. on the 1st dielectric film by part 1 and part 2 and has for example ditch (perhaps contact ditch) of flat shape such as L word shape or T word shape.

Thereby, when keeping high aperture opening ratio, can reduce the contact resistance between gate electrode and sweep trace.That is, in the present invention, particularly, contact hole is owing to have the 1st and part 2, and the situation that has flat shapes such as circle, square, rectangle with the supposition contact hole is compared, and in limited non-open area, can enlarge the region area that forms this contact hole.Thereby, in the resistance that reduces between gate electrode and sweep trace, can improve aperture opening ratio.

In addition, in the present invention, particularly, as mentioned above, the part 1 of contact hole prolongs along the direction that sweep trace extends in the semiconductor layer side.That is, part 1, form the direction of extending along sweep trace semiconductor layer side one side of extending, separate the distance of regulation, the direction of extending along sweep trace forms strip.Thereby the gate electrode that forms in part 1 or the part of sweep trace are seen on three-dimensional, along semiconductor layer, form for example wall shape occulter.Thereby, can pass through the light (that is, having) that part 1 (part of gate electrode that forms or sweep trace or rather) is blocked the oblique incidence semiconductor layer along the light of the component of real estate in part 1.That is,, can strengthen the light-proofness of the light that blocks the oblique incidence semiconductor layer by being configured near the part 1 that for example forms wall shape occulter the semiconductor layer.As a result, the flicker and the pixel that can reduce in the image demonstration is irregular.

As mentioned above, if adopt according to the 2nd electro-optical device of the present invention, connect the contact hole that sweep trace and gate electrode are used on electric, owing to have the 1st and part 2, be suitable for the raising aperture opening ratio, in the generation that can reduce light leakage current in the transistor, can realize good being electrically connected between transistorized gate electrode and sweep trace.As a result, might become clear, reduce the irregular high-quality image of flicker and pixel shows.

In a form according to the 2nd electro-optical device of the present invention, also have across the 2nd dielectric film, be configured in above-mentioned transistorized upper layer side, the memory capacitance that in above-mentioned non-open area, forms, this memory capacitance forms in the mode that covers the recess that produces on above-mentioned the 2nd dielectric film upper layer side surface because of above-mentioned contact hole, possesses the concavity part that has along the concavity section shape of recess surface.

If adopt this form, be configured in transistorized upper layer side through the 2nd dielectric film in the lit-par-lit structure of memory capacitance on substrate.In addition, memory capacitance form in non-open area, typically cover channel region and adjacent with it for example LDD district etc., on plane on the substrate, see overlapping at least in part semiconductor layer.Memory capacitance typically comprises the light-proofness conducting film, works to block the built-in photomask from the transistorized light of upper layer side incident.Thereby, can reduce the generation of light leakage current in the transistor.

Under this form, particularly, memory capacitance forms to such an extent that cover the recess that produces owing to contact hole on the 2nd dielectric film upper layer side surface, possesses the concavity part that has along the concavity section shape of this recess surface.

That is because contact hole forms on the 1st dielectric film of the lower layer side that is configured in the 2nd dielectric film as mentioned above, on the surface of the 2nd dielectric film upper layer side, produce because of this contact hole for example roughly along the recess of contact hole inwall.Memory capacitance forms to such an extent that cover this recess, thereby its part is formed in recess, possesses the concavity part that has along the concavity section shape of recess surface.Concavity part typically wall portion and the bottom in the recess forms.

Thereby memory capacitance is by having the concavity part, and capacitance increases.Thereby, can improve the current potential retention performance in the pixel electrode.In other words, the situation (that is, the situation that memory capacitance only forms in the plane) that does not have the concavity part with memory capacitance is compared, and can be made into narrow region on the substrate to the memory capacitance with capacitance of realizing the desired display performance of goods.Thereby it is irregular to reduce flicker and the pixel of image in showing, miniaturization that can implement device.

In addition, recess is owing to contact hole produces, so recess (and concavity part) has the flat shape roughly the same with the flat shape of contact hole.In other words, concavity part sees on plane on the substrate, has part that the direction of extending along sweep trace in the semiconductor layer side prolongs and part that the direction of extending along data line overlapping the time with the part of data line prolongs.Thereby the concavity part can easily be configured in the non-open area, causes the decline of aperture opening ratio hardly, can increase the capacitance of memory capacitance.

In addition, because recess produces because of contact hole, do not cause the complicated of manufacturing process or increase hardly or fully.

As mentioned above,, keep high aperture, when can increase the capacitance of memory capacitance, can reduce the generation of light leakage current among the TFT in former state if adopt this form.The result is to realize that high-quality image shows.

In order to address the above problem, electronic equipment of the present invention has above-mentioned according to the 1st electro-optical device of the present invention.

If adopt according to electronic equipment of the present invention, owing to have above-mentioned according to the 1st electro-optical device of the present invention, high-quality demonstration can be carried out, projection type image display apparatus, portable phone, electronics miscellanies basis, word processor can be realized, various electronic equipments such as find a view type or monitor direct viewing type video tape recorder, workstation, videophone, POS terminal, touch-screen.In addition, as according to electronic equipment of the present invention, for example, can also realize electrophoretic apparatuss such as electronic paper etc.

With reference to the accompanying drawing of following simple declaration, the detailed description that contact most preferred embodiment of the present invention is done below reading, character of the present invention, practicality and other features will become more obvious.

Description of drawings

Fig. 1 is the integrally-built planimetric map of the expression liquid-crystal apparatus relevant with the 1st embodiment;

Fig. 2 is the sectional view along the II-II line of Fig. 1;

Fig. 3 is the equivalent circuit diagram of a plurality of pixel portions of the liquid-crystal apparatus relevant with the 1st embodiment;

Fig. 4 is the planimetric map (underclad portion) of a plurality of pixel portions of the liquid-crystal apparatus relevant with the 1st embodiment;

Fig. 5 is the planimetric map (top section) of a plurality of pixel portions of the liquid-crystal apparatus relevant with the 1st embodiment;

Fig. 6 is along the sectional view of VI-VI line under the overlapping situation of Fig. 4 and Fig. 5;

Fig. 7 is the contact hole between sweep trace and gate electrode and the planimetric map of memory capacitance;

Fig. 8 is the sectional view along the VIII-VIII line of Fig. 7;

Fig. 9 is the sectional view along the IX-IX line of Fig. 7;

Figure 10 be among the 2nd embodiment with the planimetric map of the same intention of Fig. 7;

Figure 11 be among the 3rd embodiment with the planimetric map of the same intention of Fig. 4;

Figure 12 be among the 3rd embodiment with the planimetric map of the same intention of Fig. 5;

Figure 13 is along the sectional view of XIII-XIII line under the overlapping situation of Figure 11 and Figure 12;

Figure 14 be among the 3rd embodiment with the planimetric map of the same intention of Fig. 7; And

Figure 15 is the planimetric map of expression as the structure of the projector of an example of the electronic equipment that adopts electro-optical device.

Embodiment

Below, do an explanation with reference to accompanying drawing with regard to most preferred embodiment of the present invention.In addition, in following embodiment, with as the liquid-crystal apparatus of the tft active matrix type of drive of the driving circuit internally-arranged type of an example of electro-optical device of the present invention as example.

The 1st embodiment

Referring now to Fig. 1 to Fig. 9 the 1st embodiment is described.

At first with reference to the one-piece construction of Fig. 1 and Fig. 2 explanation according to the liquid-crystal apparatus of present embodiment.

Fig. 1 is the liquid-crystal apparatus planimetric map when substrate one side is seen each inscape that tft array substrate forms thereon from the negative, and Fig. 2 is the sectional view along the II-II line of Fig. 1.

In Fig. 1 and Fig. 2, in the liquid-crystal apparatus according to present embodiment, tft array substrate 10 and reverse side substrate 20 dispose in opposite directions.The TFT10 array base palte for example is, the transparency carrier of quartz base plate, glass substrate, silicon substrate etc.Reverse side substrate 20 and tft array substrate 10 are the same also to be transparency carrier.Between tft array substrate 10 and reverse side substrate 20, enclose liquid crystal layer 50.Tft array substrate 10 and reverse side substrate 20 bond mutually with the encapsulant 52 that is set in place the sealing area around the image display area 10a that is provided with a plurality of pixel portions.

In Fig. 1, inboard parallel with the sealing area that has disposed encapsulant 52, the frame photomask 53 of the light-proofness of the frame region of specified image viewing area 10a is arranged on reverse side substrate 20 sides.Wherein, part or all of such frame photomask 53 also can be used as the photomask setting that is built in tft array substrate 10 sides.In the neighboring area, the zone in the outside that is arranged in the sealing area that has disposed encapsulant 52, data line drive circuit 101 and external circuit-connecting terminal 102 are provided with along one side of tft array substrate 10.Scan line drive circuit 104 is along the both sides adjacent with this limit, and, be provided with to such an extent that cover on the frame photomask 53.In addition, like this,, a plurality of wirings 105 are set, make it to extend, and cover frame photomask 53 along tft array substrate 10 remaining one side in order to connect 104 of two scan line drive circuits that are arranged on image display area 10a both sides.

At 4 jiaos of reverse side substrate 20, disposed between two substrates the conductive material up and down 106 of the effect of conducting terminal up and down.On the other hand, in tft array substrate 10, conducting terminal up and down is set in their bights of subtend.By them, 20 of tft array substrate 10 and reverse side substrates can conductings on electric.

At Fig. 2, on tft array substrate 10, form TFT that has made pixel switching usefulness and the lit-par-lit structure that sweep trace, data line etc. connect up.In image display area 10a, switch the TFT of usefulness and for example, the upper strata that sweep trace, data line etc. connect up, the rectangular pixel electrode 9a that is provided with in pixel.On pixel electrode 9a, form alignment films.On the other hand, on one side opposite on the reverse side substrate 20, form photomask 23 with tft array substrate 10.Photomask 23 for example, is formed by light-proofness metal film etc., in the image display area 10a on reverse side substrate 20, for example, forms the lattice-shaped figures.Then, on photomask 23, the counter electrode 21 by transparent materials such as ITO are formed forms sheet with a plurality of pixel electrode 9a subtends.On counter electrode 21, form alignment films.In addition, liquid crystal layer 50 for example, is made up of liquid crystal a kind of or that several nematic crystals mix, between this a pair of alignment films, takes the state of orientation of stipulating.

In addition, also can be on the tft array substrate 10 of Figure 1 and Figure 2, add the driving circuit of these data line drive circuits 101, scan line drive circuit 104 etc., form to the picture signal on the image signal line sample and offer data line sample circuit, applying the pre-charge circuit of the precharging signal of assigned voltage level, checking the check circuit etc. of the usefulness such as quality, defective of this electro-optical device in manufacture process and during shipment to many data lines respectively before the picture signal.

Then, with reference to the electrical structure of Fig. 3 explanation according to the pixel portions of the liquid-crystal apparatus of present embodiment.

Fig. 3 is the equivalent circuit diagram that forms various elements in rectangular a plurality of pixels, wiring etc. that constitutes according to the image display area of the liquid-crystal apparatus of present embodiment.

In Fig. 3, composing images viewing area 10a forms in rectangular a plurality of pixels, forms pixel electrode 9a and the conduct TFT30 according to an example of " transistor " of the present invention.TFT30 is connected electrically to pixel electrode 9a, switch control pixel electrode 9a when liquid-crystal apparatus is worked.The data line 6a that picture signal is provided is connected to the source electrode of TFT30 on electric.Write the picture signal S1 of data line 6a, S2 ..., Sn also can provide with the line order by such order, for many adjacent data line 6a, also can every group provides.

Sweep trace 11 is connected to the grid of TFT30 on electric, according to the liquid-crystal apparatus of present embodiment, the timing of constructing in accordance with regulations with pulse mode sweep signal G1, G2 ..., Gm puts on sweep trace 11 by such order with the line order.Pixel electrode 9a is connected to the drain electrode of TFT30 on electric, closes its switch as the TFT30 of on-off element by certain cycle, thus the picture signal S1 that provides from data line 6a, S2 ..., Sn timing in accordance with regulations writes.Process pixel electrode 9a writes the picture signal S1 of the specified level of the liquid crystal that constitutes liquid crystal layer 50 (with reference to Fig. 2), S2 ..., Sn, and the reverse side substrate on form and keep some cycles between counter electrode.

Constitute the liquid crystal of liquid crystal layer 50,, change the orientation and the order of elements collection, thereby light modulated can be carried out gray scale and be shown owing to apply voltage level.Under normal white mode, corresponding with the voltage that applies at each pixel unit, reduce transmissivity to incident light, if adopt normal black formula, then corresponding with the voltage that applies at each pixel unit, increase is to the transmissivity of incident light, and as a whole from liquid-crystal apparatus, outgoing has the light with the corresponding contrast of picture signal.

For the leakage of the picture signal that prevents to preserve here, increased with pixel electrode 9a and counter electrode 21 (with reference to Fig. 2) between the liquid crystal capacitance memory capacitance 70 in parallel that forms.Memory capacitance 70 is a kind of capacity cells that play a part according to the maintenance electric capacity of each pixel electrode 9a current potential of the temporary transient preservation of providing of picture signal.An electrode of memory capacitance 70,9a is in parallel with pixel electrode, is connected to the drain electrode of TFT30 on electric, and another electrode connects the fixing electric capacity line 300 of current potential on electric, to become constant potential.If be used in memory capacitance 70, then can improve the current potential retention performance among the pixel electrode 9a, can the raising contrast, reduce display characteristic such as flicker grade.In addition, memory capacitance 70 as described later, also works to block the built-in photomask of the light of incident TFT30.

The concrete structure of the pixel portions that realizes above-mentioned action then, is described with reference to Fig. 4 to Fig. 6.

Fig. 4 and Fig. 5 are the planimetric maps that forms adjacent a plurality of pixel portions such as the tft array substrate of data line, sweep trace, pixel electrode etc.Fig. 4 and Fig. 5 show underclad portion (Fig. 4) and the top section (Fig. 5) in the lit-par-lit structure described later respectively.Fig. 6 is along the sectional view of VI-VI line under the overlapping situation of Fig. 4 and Fig. 5.

In addition, in Fig. 6, for each layer/each parts are amplified to the degree that can discern on figure, the engineer's scale of this each layer/each parts is different.In addition, for convenience of explanation, in Fig. 5 and Fig. 6, be positioned at the more not demonstration of part of upside of pixel electrode 9a.

In Fig. 5, pixel electrode 9a is rectangular on tft array substrate 10 to be provided with a plurality of (representing its profile by dotted line).

As Fig. 4 and shown in Figure 5, the border in length and breadth along pixel electrode 9a is provided with data line 6a and sweep trace 11 respectively.That is, sweep trace 11 extends along directions X, and data line 6a extends along the Y direction, makes it to intersect with sweep trace 11.TFT30 is separately positioned on sweep trace 11 and data line 6a intersection region intersected with each other.

Sweep trace 11, data line 6a, memory capacitance 70, relay layer 93 and TFT30, plane on tft array substrate 10 is seen, be configured in encirclement (promptly corresponding to the open area of each pixel of pixel electrode 9a, on each pixel, transmission or the reflection in fact to showing the zone of contributive light) non-open area.That is, these sweep traces 11, memory capacitance 70, data line 6a, relay layer 93 and TFT30 are not configured in the open area of each pixel, and are configured in the non-open area, make it not hinder demonstration.In addition, sweep trace 11, memory capacitance 70, data line 6a and relay layer 93, the part of the non-open area of separate provision.

As shown in Figure 6, on tft array substrate 10, various textural elements such as sweep trace 11, TFT30, memory capacitance 70, data line 6a, pixel electrode 9a are set to form lit-par-lit structure.This lit-par-lit structure is made up of the 5th layer (the superiors) comprising the 1st layer of sweep trace 11, comprise the 2nd layer of TFT30 with gate electrode 3 etc., comprise the 3rd layer of memory capacitance 70, comprise the 4th layer of data line 6a etc. and comprise pixel electrode 9a etc. successively from following.In addition, between the 1st layer and the 2nd layer, underlayer insulating film 12 is set respectively, between the 2nd layer and the 3rd layer, interlayer dielectric 41 is set, the 2nd interlayer dielectric 42 is set between the 3rd layer and the 4th layer, the 3rd interlayer dielectric 43 is set between the 4th layer and the 5th layer, prevents short circuit between above-mentioned each key element.In addition, in these various dielectric films 12,41,42 and 43, for example, form contact hole 81 etc., data line side source-drain area 1d and data line 6a on electric among the semiconductor layer 1a of connection TFT30.Below, these each key elements are described successively.In addition, in the above-mentioned lit-par-lit structure from the 1st layer to the 1st interlayer dielectric, show in Fig. 4 as underclad portion, show at Fig. 5 as top section from the 3rd layer to the 5th layer.

Structure-sweep trace of the 1st layer etc.

In Fig. 6, sweep trace 11 is set as the 1st layer.Sweep trace 11 is made up of light-proofness conductive materials such as for example tungsten (W), titanium (Ti), titanium nitride refractory metals such as (TiN) materials.

As shown in Figure 4, sweep trace 11 forms tape shape figure, makes it along directions X (extension).If more detailed observation, sweep trace 11 has the main line that extends along directions X and partly and from main line part 11x extends the extension 11y that is provided with to the Y direction.In addition, the extension 11y of adjacent sweep trace 11 does not interconnect, thereby this sweep trace becomes the form that disconnects one by one.

Structure-TFT of the 2nd layer etc.

In Fig. 6,, TFT30 is set as the 2nd layer.

As Fig. 4 and shown in Figure 6, TFT30 constructs to such an extent that comprise semiconductor layer 1a and gate electrode 3.

Semiconductor layer 1a for example, is made up of polysilicon, forms by have raceway groove long channel region 1a ', data line side LDD district 1b, pixel electrode side LDD district 1c, data line side source-drain area 1d and pixel electrode side source-drain area 1e along the Y direction.That is, TFT30 has the LDD structure.In addition, data line side LDD district 1b is an example according to " the 1st interface " of the present invention, and pixel electrode side LDD district 1c is an example according to " the 2nd interface " of the present invention.

Data line side source-drain area 1d and pixel electrode side source-drain area 1e, roughly form along Y direction mirror image as benchmark symmetrically with channel region 1a '.Data line side LDD district 1b forms between channel region 1a ' and data line side source-drain area 1d.Pixel electrode side LDD district 1c forms between channel region 1a ' and pixel electrode side source-drain area 1e.Data line side LDD district 1b, pixel electrode side LDD district 1c, data line side source-drain area 1d and pixel electrode side source-drain area 1e for example, are by the implanted dopant doped region that implanted dopant forms in semiconductor layer 1a with ion implantation etc.Data line side LDD district 1b and pixel electrode side LDD district 1c form the doped region of impurity concentration a little less than data line side source-drain area 1d and pixel electrode side source-drain area 1e respectively.If adopt such doped region, when TFT30 is inoperative, can reduce the cut-off current that flows in source area and drain region, and the decline of the conducting electric current that flows through can suppress TFT30 work time the and the rising of cut-off leakage current.In addition, TFT30, preferably has the LDD structure, but also can be not to the offset configuration of data line side LDD district 1b, pixel electrode side LDD district 1c implanted dopant, also can be with gate electrode as mask, by the high concentration implanted dopant form data line side source-drain area and pixel electrode side source-drain area from matching type.

Between sweep trace 11 and the semiconductor layer 1a, insulate by the underlayer insulating film 12 of conduct according to an example of " the 1st dielectric film " of the present invention.Base insulating layer 12, except that working to make semiconductor layer 1a to sweep trace 11 insulation, on whole of tft array substrate 10, form, thereby have roughening when grinding tft array substrate 10 surperficial, prevent to clean the function that the residual pollutant in back etc. causes the deterioration of the TFT30 characteristic that pixel switch uses.

In addition, in Fig. 4, in underlayer insulating film 12,, form contact hole 810 as a example according to " contact hole " of the present invention.Describe the structure of relevant contact hole 810 in detail referring now to Fig. 7 to Fig. 9.

As Fig. 4 and shown in Figure 6, gate electrode 3 is configured in the upper layer side of semiconductor layer 1a across gate insulating film 2.That is, TFT30 forms top gate type TFT.Gate electrode 3 for example, is made up of the light-proofness conductive material of tungsten (W), titanium (Ti), titanium nitride refractory metals such as (TiN) material etc.In addition, gate electrode 3 also can be by for example, and the electric conductivity polysilicon forms.

As shown in Figure 4, gate electrode 3 has the main part 3a of the channel region 1a ' that overlaps TFT30, extends extension 32 that is provided with and the extension 31 of extending setting from this main part 3a along the Y direction from this main part 3a along directions X.In addition, extension 31 and 31 is examples according to " gate electrode extension " of the present invention.The contact hole 810 of perforate is connected to each other on electric with sweep trace 11 gate electrode 3 through running through gate insulating film 2 and underlayer insulating film 12.

In addition, in the present embodiment, separate the gate electrode 3 of each TFT30 respectively and form, but for example, also can form the gate electrode 3 of the TFT30 (that is, along directions X adjacent one another are TFT30) corresponding with same sweep trace 11 is connected to each other.In other words, also can be with respect to semiconductor layer 1a, form the gate electrode 3 that comprises the TFT30 corresponding, be configured in other sweep traces on the layer with sweep trace 11 opposite sides with same sweep trace 11.In this case, can constitute two to sweep trace and reroute, can provide sweep signal to gate electrode 3 reliablely.

Structure-memory capacitance of the 3rd layer etc.

In Fig. 6, memory capacitance 70 is set as the 3rd layer.Memory capacitance 70 is arranged on the upper layer side of TFT30 across first interlayer dielectric 41 of conduct according to an example of " the 2nd dielectric film " of the present invention.

Dispose bottom capacitance electrode 71 and top capacitor electrode 300a opposite to each other across dielectric film 75, thereby form memory capacitance 70.

As Fig. 5 and shown in Figure 6, top capacitor electrode 300a forms the part of electric capacity line 300.Electric capacity line 300 extends setting from the image display area 10a that disposes pixel electrode 9a around it.Top capacitor electrode 300a connects constant pressure source through electric capacity line 300 on electric, be the set potential lateral capacitance electrode that maintains on the set potential.Top capacitor electrode 300a by for example, comprises the opaque metal film formation of Al (aluminium), Ag metal or alloy such as (silver), also plays the upper light shielding (built-in photomask) to the TFT30 shading.In addition, top capacitor electrode 300a, for example comprise, at least a in Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), the Pd refractory metals such as (palladiums), metal monomer, alloy, metal silicide, poly-silicide also can be made of their stacked grade.

Bottom capacitance electrode 71 is the pixel electrode side source-drain area 1e of TFT30 and the pixel current potential lateral capacitance electrode that is connected to pixel electrode 9a on electric.More particularly, bottom capacitance electrode 71, on electric, be connected in the pixel electrode side source-drain area 1e through contact hole 83, the contact hole 84 (with reference to Fig. 5) of perforate through running through the 2nd interlayer dielectric 42 and dielectric film 75, on electric, be connected to the relay layer 93 that is configured in the same one deck of data line 6a described later (that is, the 4th layer).Relay layer 93 (with reference to Fig. 5) through the contact hole 85 (with reference to Fig. 5) in 43 perforates of the 3rd interlayer dielectric, connects pixel electrode 9a on electric in addition.That is, bottom capacitance electrode 71 and relay layer 93 together, being electrically connected between relaying pixel electrode side source-drain area 1e and pixel electrode 9a.Bottom capacitance electrode 71 is formed by the polysilicon of electric conductivity.Thereby memory capacitance 70 has so-called MIS structure.In addition, bottom capacitance electrode 71 except that playing pixel current potential lateral capacitance electrode, also has as the function that plays light absorbing zone or photomask between top capacitor electrode 300a that is configured in upper light shielding and the TFT30.

Dielectric film 75 has the monolayer constructions will that is made of the silicon oxide film of HTO (high-temperature oxide) film, LTO (low temperature oxide) film etc. or silicon nitride film etc., perhaps multi-ply construction.

In addition, also can form bottom capacitance electrode 71 by metal film as top capacitor electrode 300a.That is, memory capacitance 70 also can form to such an extent that have a so-called MIM structure of metal film-dielectric film (dielectric film)-3 layers of structure of metal film.

In addition, as Fig. 4 and shown in Figure 5, in the present embodiment, particularly, memory capacitance forms to such an extent that cover contact hole 810.Therefore, although the back also will describe in detail with reference to Fig. 7 to Fig. 9, memory capacitance 70 has the concavity part 70t that forms along recess 710 surfaces that produce on the upper layer side surface of the 1st interlayer dielectric 41 because of contact hole 810.

Structure-data line of the 4th layer etc.

In Fig. 6, data line 6a is set as the 4th layer.In addition, in the 4th layer, relay layer 93 (with reference to Fig. 5) is by forming with the same film of data line 6a.

As Fig. 5 and shown in Figure 6, data line 6a through running through the contact hole 81 of the 1st interlayer dielectric 41, dielectric film 75 and the 2nd interlayer dielectric 42, is connected to the data line side source-drain area 1d of semiconductor layer 1a on electric.Data line 6a and contact hole 81 inside, for example, the multilayer film that is contained Al (aluminium) material or Al monomer or Al layer and TiN layer etc. by Al-Si-Cu, Al-Cu etc. is formed.Data line 6a also has the function to the TFT30 shading.

In Fig. 5, relay layer 93 is on interlayer dielectric 42, in the layer upward formation same with data line 6a (with reference to Fig. 6).Data line 6a and relay layer 93 for example, adopt the film forming method to form on interlayer dielectric 42 with the film that conductive materials such as metal film constitute, and partly remove this film, that is, by form figure be in state spaced apart from each other.Thereby, because data line 6a and relay layer 93 can form in same operation, manufacturing process that can simplification device.

Structure-pixel electrode of the 5th layer etc.

In Fig. 6, pixel electrode 9a is set as the 5th layer.Pixel electrode 9a forms across the upper layer side of the 3rd interlayer dielectric 43 at data line 6a.

As Fig. 5 and shown in Figure 6, pixel electrode 9a through bottom capacitance electrode 71, contact hole 83,84 and 85 and relay layer 93, is connected to the pixel electrode side source-drain area 1e of semiconductor layer 1a on electric.On the uper side surface of pixel electrode 9a, the alignment films of the orientation process that has applied regulations such as milled processed is set.

The above structure of Shuo Ming pixel portions, as Fig. 4 and shown in Figure 5, each pixel portions all is the same.On image display area 10a (with reference to Fig. 1), form such pixel portions periodically.

Then, with reference to Fig. 7 to Fig. 9, in the shape of explanation memory capacitance, describe sweep trace according to the liquid-crystal apparatus of present embodiment, gate electrode in detail, be connected the flat shape of the contact hole between this sweep trace and the gate electrode on electric.

Fig. 7 is a planimetric map, and expression is connected the contact hole between this sweep trace and the gate electrode and the flat shape of memory capacitance according to the sweep trace of the liquid-crystal apparatus of present embodiment, gate electrode, on electric.Fig. 8 is the sectional view along the VIII-VIII line of Fig. 7.Fig. 9 is the sectional view along the IX-IX line of Fig. 7.

In addition, in Fig. 7, in the inscape that constitutes pixel portions shown in Figure 4, sweep trace 11, TFT30 and memory capacitance 70 are to amplify to show that other inscapes are omitted in the drawings.In addition, in Fig. 8 and Fig. 9, omitted the textural element of the upper layer side of the 2nd interlayer dielectric.

In Fig. 7, sweep trace 11 with reference to Fig. 4 as mentioned above, has along the main line part 11x of directions X extension and the extension 11y that extension is provided with from main line part 11x along the Y direction.Extension 11y forms by comprising the 1st extension 11y1 that forms with the zone of data line side LDD district 1b subtend and comprising the 2nd extension 11y2 that forms with the zone of pixel electrode side LDD district 1c subtend.Thereby, from the light of lower layer side incident data line side LDD district 1b and pixel electrode side LDD district 1c, can block with the 1st extension 11y1 and the 2nd extension 11y2.Thereby, can reduce the generation of light leakage current among data line side LDD district 1b and the pixel electrode side LDD district 1c.

In addition, in the present embodiment, the 2nd extension 11y2 in the sweep trace 11 constructs to such an extent that the width of directions X is wideer than the 1st extension 11y1.That is, the directions X width W 2 of the 2nd extension 11y2, wideer than the directions X width W 1 of the 1st extension 11y1.Thereby, from the light of lower layer side incident pixel electrode side LDD district 1c, can be blocked more reliably than light from lower layer side incident data line side LDD district 1b.Thereby, can improve light-proofness to the pixel electrode side LDD district 1c of relatively easy generation light leakage current, can reduce the light leakage current that flows through TFT30 effectively.

Extremely shown in Figure 9 as Fig. 7, gate electrode 3 and sweep trace 11, the contact hole 810 of perforate links together on electric through running through gate insulating film 2 and underlayer insulating film 12.

As shown in Figure 7, in the present embodiment, particularly, contact hole 810, on tft array substrate 10, see in the plane, in the side of semiconductor layer 1a, has the part 1 811 that prolongs along the Y direction and part 2 812 overlapping and that prolong along directions X with the part of the main line part 11x of sweep trace 11.That is, contact hole 810 connects part 1 811 and part 2 812, we can say to have the flat shape with L word sigmoid.In addition, gate electrode 3, as above described with reference to Fig. 4, have the main part 3a on the channel region 1a ' that overlaps TFT30 and extend and be set to the extension 31 and 32 overlapping with contact hole 810 from this main part 3a.Setting is extended along the Y direction in extension 31, covers the part 1 811 of contact hole 810, and setting is extended along directions X in extension 32, covers the part 2 812 of contact hole 810.Thereby as shown in Figure 8, the part of extension 31 forms in the part 1 811 of contact hole 810, contacts with sweep trace 11 (part of the 2nd extension 11y2 in more detail).Similarly, as shown in Figure 9, the part of extension 32 forms in the part 2 812 of contact hole 810, contacts with sweep trace 11 (part of main line part 11x in more detail).

Owing to constitute like this, can when keeping high aperture, reduce the contact resistance between gate electrode 3 and the sweep trace 11.

Promptly, in the present embodiment, particularly, as mentioned above, because contact hole 810 has part 1 811 and part 2 812, with supposition contact hole 810 for example, rounded, square etc. has the situation as the Typical Planar shape of general contact hole, suppose that perhaps contact hole 810 compared by any one situation about forming in part 1 811 and the part 2 812, can enlarge the region area that forms this contact hole 810 in limited non-open area.Thereby, in the resistance that reduces between gate electrode 3 and the sweep trace 11, can improve aperture opening ratio.

In addition, as present embodiment, contact hole 810 connects part 1 811 and part 2s 812, we can say by having the flat shape of L word sigmoid, can avoid between gate electrode 3 and the sweep trace 11 unconnected problem electric.Promptly, suppose that contact hole 810 is inferior by any one situation about forming in part 1 811 and the part 2 812, have at contact hole under the situation of flat shape of rectangle or strip, along with high apertureization and miniaturization, when contact hole forms carefully, abundant perforate to make contact hole reach sweep trace and probably can become difficult.Yet, as present embodiment, contact hole 810 be we can say under the situation of the flat shape with L word sigmoid, at least (in other words at this sweep, part that part 1 811 is connected with part 2 or intersection), perforate may be than being easier to making contact hole 810 can reach sweep trace on experience.Thereby, can on electric, connect gate electrode 3 and sweep trace 11 reliably.

In addition, in the present embodiment, particularly, as mentioned above, the part 1 811 of contact hole 810 prolongs along the Y direction in the side of semiconductor layer 1a.More particularly, part 1 811, form the side of the semiconductor layer 1a that extends along the Y direction, separate the distance L 1 of regulation, form strip along the Y direction.

Thereby as shown in Figure 8, the gate electrode 3 that forms in part 1 811 (see on three-dimensional or rather, extension 31, forms wall shape occulter along semiconductor layer 1a by) a part.Thereby, can be (or rather with part 1 811, the part of the gate electrode 3 that forms in the part 1 811) block oblique incidence semiconductor layer 1a light (that is, for example, in Fig. 8, light along the direction incident shown in the arrow P 1, that is, has the light of directions X or Y durection component in the incident light, perhaps along the light of direction incident shown in the arrow P 2, that is the light that, has directions X or Y durection component in the back light).That is, can strengthen the light-proofness that blocks the light of semiconductor layer 1a oblique incidence with near the part 1 811 that forms wall shape occulter the configuring semiconductor layer 1a.As a result, the flicker and the pixel that can reduce in the image demonstration is irregular.

In addition, as shown in Figures 7 and 8, in the present embodiment, particularly, contact hole 810 respectively is provided with one in semiconductor layer 1a both sides respectively, and the part 1 811 of contact hole 810 forms wall shape occulter in the both sides of semiconductor layer 1a.Thereby, can block from the light of both sides oblique incidence semiconductor layer 1a.Thereby, can reduce the light leakage current among the TFT30 reliablely.

In addition, also can be only on (that is, in Fig. 7, left side or right side) contact hole 810 be set, only simultaneously forms part 1 811 at semiconductor layer 1a in the side of semiconductor layer 1a.Even also can correspondingly strengthen in this case, the light-proofness of the light that blocks oblique incidence semiconductor layer 1a.But, from the viewpoint of strengthening light-proofness and the viewpoint that reduces contact resistance,, contact hole 810 is set in the both sides of semiconductor layer 1a as present embodiment, form part 1 811 in the both sides of semiconductor layer 1a.

In addition, as shown in Figure 7, in the present embodiment, particularly, the part 1 811 of contact hole 810 is arranged on the both sides of pixel electrode side LDD district 1c, and is not arranged on the both sides of data line side LDD district 1b.Thereby, can make the light-proofness that blocks the light that arrives pixel electrode side LDD district 1c, also higher than the light-proofness that blocks the light that arrives data line side LDD district 1b, maybe can strengthen it.Wherein, the present inventor reaches a conclusion, and during TFT30 work, at pixel electrode side LDD district 1c, compares with data line side LDD district 1b, and light leakage current relatively easily takes place.That is, reach a conclusion, during TFT30 work, be subjected to light-struck situation, compared by light-struck situation with data line side LDD district 1b, easier generation light leakage current in TFT30 at pixel electrode side LDD district 1c.Thereby, part 1 811 is arranged on the both sides of pixel electrode side LDD district 1c, and is not arranged on the both sides of data line side LDD district 1b, light-proofness can be improved like this, the light leakage current that flows through TFT30 can be reduced effectively the pixel electrode side LDD district 1c of relatively easy generation light leakage current.Otherwise, by not extending contact hole 810 is set in the both sides of the data line side LDD district 1b that compares relative difficult generation light leakage current with pixel electrode side LDD district 1c, can prevent the decline that aperture opening ratio is meaningless.

In addition, as shown in Figure 7, in the present embodiment, particularly, the width W T1 of contact hole 810 part 1s 811 is narrower than the width W T2 of part 2 812.Thereby, cause the increase of the non-aperture opening ratio that causes because of formation part 1 811 hardly, i.e. the decline of aperture opening ratio.In addition, the width W T2 of part 2 812, wideer than the width W T1 of part 1 811, so can reduce contact resistance between gate electrode 3 and the sweep trace 11 reliably.That is, when keeping high aperture reliably, the light-proofness that can mainly strengthen TFT30, the contact resistance that can mainly reduce between gate electrode 3 and the sweep trace 11 by part 2 812 by part 1 811.

To shown in Figure 9, constitute the top capacitor electrode 300a of memory capacitance 70 as Fig. 7, have the 1st electrode part 301 of cover data line side LDD district 1b and the 2nd electrode part 302 of covering pixel electrode side LDD district 1c.In addition, constitute the bottom capacitance electrode 71 of memory capacitance 70, have the 1st electrode part 71a of cover data line side LDD district 1b and the 2nd electrode part 71b of covering pixel electrode side LDD district 1c.In addition, the 1st electrode part 301 and 71a and be arranged on the part between the 1st electrode part 301 and 71a in the dielectric film 75, formation is according to an example of " the 1st capacitive part " of the present invention, the 2nd electrode part 302 and 71b and the part that is arranged on the 2nd electrode part 302 and 71b in the dielectric film 75 constitute an example according to " the 2nd capacitive part " of the present invention.

Thereby, can block from the light of upper layer side incident data line side LDD district 1b by the 1st electrode part 301 and 71a.In addition, can block from the light of upper layer side incident pixel electrode side LDD district 1c by the 2nd electrode part 302 and 71b.Thereby, can reduce the generation of light leakage current among data line side LDD district 1b and the pixel electrode side LDD district 1c.

In the present embodiment, particularly, memory capacitance 70 has and forms to such an extent that cover the recess 710 that produces because of contact hole 810 on the 1st interlayer dielectric 41 upper layer side surfaces, has the concavity part 70t of concavity section shape along the surface of recess 710.

Promptly, as Fig. 8 and shown in Figure 9, owing in underlayer insulating film 12 that is disposed at the 1st interlayer dielectric 41 lower layer sides and gate insulating film, form contact hole 810, therefore on the upper layer side surface of the 1st interlayer dielectric 41, for example produce roughly along the recess 710 of the inwall of contact hole 810 because of contact hole 810.Memory capacitance 70 forms to such an extent that cover recess 710, thereby its part forms in recess 710, possesses the concavity part 70t that has along the concavity section shape on the surface of recess 710.Concavity part 70t is made up of the part that overlaps part on the top capacitor electrode 300a center dant 710, overlaps the part on dielectric film 75 inner fovea parts 710 and overlap the recess 710 in the bottom capacitance electrode 71.

Thereby memory capacitance 70 is by having concavity part 70t, and capacitance increases.Thereby, can improve the current potential retention performance among the pixel electrode 9a.In other words, the situation that does not have a concavity part 70t with memory capacitance 70 (promptly, 70 situations about forming in the plane of memory capacitance) compare, can be made into narrow region on the tft array substrate 10 to the memory capacitance of the capacitance of realizing having the desired display performance of goods.Thereby it is irregular to reduce flicker and the pixel of image in showing, miniaturization that can implement device.

In addition, recess 710 produces because of contact hole 810, so recess 710 (and concavity part 70t) has the flat shape roughly the same with the flat shape of contact hole 810 (omitting among the figure).In other words, concavity part 70t is seeing on the plane on the tft array substrate 10, has in the side of semiconductor layer 1a the part that prolongs along the Y direction and the part overlapping and that prolong along directions X with the part of sweep trace 11 main line part 11x.Thereby, can be configured in concavity part 70t in the non-open area easily, cause the decline of aperture opening ratio hardly, can increase the capacitance of memory capacitance 70.

In addition, the part 1 811 of contact hole 810 and part 2 812 are preferably formed as to such an extent that make separately width surpass the twice of the thickness of gate electrode 3.In this case, can reduce or prevent to be produced the recess 710 that causes because of contact hole 810 by the filling of the part of gate electrode 3, the 1st interlayer dielectric on the 41 upper layer side surfaces fully in the contact hole 810, promptly, on the upper layer side surface of the 1st interlayer dielectric 41, can produce the recess 710 that causes because of contact hole 810 reliablely.Thereby, can make memory capacitance 70 have concavity part 70t reliably, increase the capacitance of memory capacitance 70 reliably.But, the part 1 811 of contact hole 810 and the width separately of part 2 812, even below 2 times of thickness at gate electrode 3, coverage rate by adjusting contact hole 810 madial walls (promptly, in the gate electrode 3, with respect to the thickness of the part that forms along the real estate of tft array substrate 10, the thickness of the part that forms on the sidewall in the contact hole 810 (promptly, the thickness of counting from side wall surface) ratio less than 100% just can make recess 710 produce.

In addition, because recess 710 is because of contact hole 810 produces, do not cause the complicated of manufacturing process or increase hardly or fully.

As mentioned above, if adopt liquid-crystal apparatus according to present embodiment, the contact hole 810 that connects sweep trace 11 and gate electrode 3 usefulness on electric, owing to have part 1 811 and part 2 812, can improve aperture opening ratio, when can reduce the generation of light leakage current among the TFT30 that pixel switch uses, realize that good electrical connects between the gate electrode 3 of TFT30 and the sweep trace 11.In addition, can when keeping high aperture, increase the capacitance of memory capacitance 70.Consequently, it is irregular to reduce flicker and pixel, can realize that the high-quality image that becomes clear shows.

The 2nd embodiment

Referring now to Figure 10 the 2nd embodiment is described.

Figure 10 is among the 2nd embodiment and the planimetric map same intention of Fig. 7.In addition, in Figure 10, all identical textural elements of inscape of being correlated with to the 1st embodiment shown in Figure 9 with Fig. 1, all attached with same quotation mark, so suitably omit its explanation.

In Figure 10, the liquid-crystal apparatus difference relevant with the 2nd embodiment is: the contact hole 810 in need not above-mentioned the 1st embodiment, and form contact hole 820; Gate electrode 3 also has extension 33 except that main part 3a, extension 31 and 32; The 1st extension 11y1 of sweep trace 11 in need not above-mentioned the 1st embodiment, and have the 1st extension 11y3; Bottom capacitance electrode 71 is without part 1 71a, and has part 1 71c; And top capacitor electrode 300a is without part 1 301, and has part 1 303, and on other aspects, its formation is roughly the same with the liquid-crystal apparatus structure relevant with above-mentioned the 1st embodiment.

In the present embodiment, particularly, contact hole 820, seeing on the plane on the tft array substrate 10, the part 1 821b that has the part 1 821a that prolongs along pixel electrode side LDD district 1c, prolongs along data line side LDD district 1b, with the part of sweep trace 11 main line part 11x overlapping the time along the part 2 822 of directions X prolongation.That is, contact hole 820 by part 1 821a and 821b and part 2 822, we can say to have T word shape flat shape.In addition, gate electrode 3 have the main part 3a overlapping with the channel region 1a ' of TFT30, from extension 31,32 and 33 that this main part 3a and contact hole 820 overlap extensions are provided with.Setting is extended along the Y direction in extension 31, covers the part 1 821a of contact hole 820, setting is extended along directions X in extension 32, covers the part 2 822 of contact hole 820, setting is extended along the Y direction in extension 33, covers the part 1 821b of contact hole 820.Thereby, the part of extension 31, in the part 1 821a of contact hole 820, form, with sweep trace 11 (in more detail, the part of the 2nd extension 11y2) contact, the part of extension 32, in the part 2 822 of contact hole 820, form, with sweep trace 11 (in more detail, the part of main line part 11x) contact, the part of extension 33 forms in the part 1 821b of contact hole 820, contact with sweep trace 11 (part of the 1st extension 11y3 in more detail).

Owing to constitute like this, except that the part 1 821a of contact hole 820,, can block the light of incident semiconductor layer 1a by part 1 821b reliablely, make the possibility that becomes that reduces light leakage current among the TFT30 reliablely.

In addition, contact hole 820 owing to except that part 1 821a, also have part 1 821b, can reduce contact resistance reliablely, can realize better being electrically connected between gate electrode 3 and the sweep trace 11.

In addition, in the present embodiment, particularly, memory capacitance 70 forms to such an extent that cover the recess that produces because of contact hole 820 on the upper layer side surface of the 1st interlayer dielectric 41 (promptly, the 1st electrode part 303 and 71c, form to such an extent that cover the recess that the part 1 821b because of contact hole 820 produces, the 2nd electrode part 302 and 71b form to such an extent that cover the recess that the part 1 821a because of contact hole 820 produces), possess the concavity part that has along the concavity section shape of recess surface.Thereby memory capacitance 70 is by having the concavity part, and capacitance increases.Thereby, can improve the current potential retention performance among the pixel electrode 9a.In addition, such recess, owing to because of contact hole 820 produces, recess (and concavity part) has the identical flat shape (omitting among the figure) of flat shape of the contact hole 820 of making peace greatly.In other words, the concavity part, on tft array substrate 10 planes, see to have near data line side LDD district 1b and pixel electrode side LDD district 1c, separately the part that prolongs along the Y direction and with the part of sweep trace 11 main line part 11x part overlapping and that prolong along directions X.Thereby easily configuration concavity part in non-open area is caused the decline of aperture opening ratio hardly, can increase the capacitance of memory capacitance 70.

In addition, in the present embodiment, construct contact hole 820 to such an extent that have the flat shape of so-called T word shape, but for example, also can prolong to such an extent that make part 2 822 near semiconductor layer 1a.In this case, can further increase the area that forms contact hole 820, further reduce contact resistance.In addition, owing to making the recess that produces because of contact hole 820 become big, the concavity part is further increased.Thereby, can further increase the capacitance of memory capacitance 70.

The 3rd embodiment

Referring now to Figure 11 to Figure 14 the 3rd embodiment is described.

At first, with reference to the structure of Figure 11 to Figure 13 explanation according to the pixel portions of the liquid-crystal apparatus of present embodiment.

Figure 11 is among the 3rd embodiment and the planimetric map same intention of Fig. 4, Figure 12 be among the 3rd embodiment with the planimetric map of the same intention of Fig. 5, Figure 13 is along the sectional view of XIII-XIII line under the overlapping situation of Figure 11 and Figure 12.In addition, in Figure 11 to Figure 13, all identical textural elements of textural element of being correlated with to the 1st embodiment shown in Figure 9 with Fig. 1, all attached with same quotation mark, so suitably omit its explanation.In addition, in Figure 13, for each layer/each parts are amplified to the degree that can discern on figure, the engineer's scale of this each layer/each parts is different.

In Figure 11 to Figure 13, the liquid-crystal apparatus relevant with the 3rd embodiment, the liquid-crystal apparatus dissimilarity relevant with above-mentioned the 1st embodiment is: do not have sweep trace 11, TFT30, memory capacitance 70 and data line 6a among above-mentioned the 1st embodiment, and have sweep trace 13, TFT35, memory capacitance 73 and data line 6c; Contact hole 810 in need not above-mentioned the 1st embodiment, and form contact hole 830, in addition, roughly the same with the liquid-crystal apparatus structure relevant with the 1st embodiment.

In addition, although the back also will illustrate with reference to Figure 11, but in the liquid-crystal apparatus relevant with the 3rd embodiment, constitute the semiconductor layer 5a of TFT35, the direction (that is, directions X) of extending along sweep trace forms, and the direction that the semiconductor layer 1a that constitutes the TFT30 among above-mentioned the 1st embodiment extends along data line (promptly, the Y direction) forming, is different in this.

As Figure 11 and shown in Figure 12, data line 6c and sweep trace 13 are provided with along the border in length and breadth of pixel electrode 9a separately.That is, sweep trace 13 extends along directions X, and data line 6c extends along the Y direction, makes it to intersect with sweep trace 13.TFT35 is arranged on sweep trace 13 and the data line 6c intersection region intersected with each other.

Sweep trace 13, data line 6c, memory capacitance 73, relay layer 93c and TFT35 see on tft array substrate 10 planes, are configured in the non-open area of the open area that surrounds each pixel corresponding with pixel electrode 9a.

Structure-sweep trace of the 1st layer etc.

In Figure 13, sweep trace 13 is set as the 1st layer.Sweep trace 13, by for example, light-proofness conductive materials such as tungsten (W), titanium (Ti), titanium nitride refractory metals such as (TiN) material are formed.

As shown in figure 11, sweep trace 13 forms tape shape figure along directions X.If having along the main line part 13a of directions X extension with from this main line part 13a, more detailed observation, sweep trace 13 extend the extension 13b that is provided with in the Y direction.Extension 13b sees on tft array substrate 10 planes, forms overlappingly with contact hole described later 830 at least.In addition, the extension 13b of 1 adjacent sweep trace 13 does not interconnect, thereby the shape of this sweep trace 13 is to disconnect one by one.

Structure-TFT of the 2nd layer etc.

In Figure 13, TFT35 is set as the 2nd layer.

As Figure 11 and shown in Figure 13, TFT35 is configured and comprises semiconductor layer 5a and gate electrode 33.

Semiconductor layer 5a is by for example, and polysilicon is formed, and forms by have raceway groove long channel region 5a ', data line side LDD district 5b, pixel electrode side LDD district 5c, data line side source-drain area 5d and pixel electrode side source-drain area 5e along directions X.That is, TFT35 has the LDD structure.

Data line side source-drain area 5d and pixel electrode side source-drain area 5e are benchmark with channel region 5a ', are symmetrically formed along the directions X substantial mirror images.Data line side LDD district 5b forms between channel region 5a ' and source-drain area 5d.Pixel electrode side LDD district 5c forms between channel region 5a ' and pixel electrode side source-drain area 5e.

Between sweep trace 13 and semiconductor layer 5a, by underlayer insulating film 12 insulation.In underlayer insulating film 12, form contact hole 830.Describe the structure of contact hole 830 in detail referring now to Figure 14.

As Figure 11 and shown in Figure 13, gate electrode 33 is configured in the upper layer side of semiconductor layer 5a across gate insulating film 2.Gate electrode 33 is by for example, and light-proofness conductive materials such as tungsten (W), titanium (Ti), titanium nitride refractory metals such as (TiN) material are formed.In addition, gate electrode 33 also can be formed by the electric conductivity polysilicon.

As shown in figure 11, gate electrode 33 has, and overlaps main part 33a on the channel region 5a ' of TFT35, extends the extension 331 that is provided with from this main part 33a along directions X, extends the extension 332 that is provided with from this main part 33a along the Y direction.Gate electrode 33 is connected to each other with sweep trace 13 on electric through running through the contact hole 830 of gate insulating film 2 and underlayer insulating film 12 perforates.

Structure-memory capacitance of the 3rd layer etc.

In Figure 13, memory capacitance 73 is set as the 3rd layer.Memory capacitance 73 is arranged on the upper layer side of TFT35 across the 1st interlayer dielectric 41.

Across dielectric film 75, the bottom capacitance electrode 731 and the top capacitor electrode 330a of memory capacitance 73 dispose opposite to each other and form.

As Figure 12 and shown in Figure 13, top capacitor electrode 330a forms the part of electric capacity line 330.Electric capacity line 330 is along the wiring of Y direction, and the electric capacity line 300 among above-mentioned the 1st embodiment is along the directions X wiring, and is different in this.Electric capacity line 330 from having disposed the image display area 10a of pixel electrode 9a, extends setting around it.Top capacitor electrode 330a through electric capacity line 330, is connected to constant pressure source on electric, be the set potential lateral capacitance electrode of keeping set potential.Top capacitor electrode 330a by for example, comprises the non-transparent metals film formation of Al (aluminium), Ag metal or alloy such as (silver), works to give the upper light shielding of TFT35 shading.

Bottom capacitance electrode 731 is to be connected to the pixel electrode side source-drain area 5e of TFT35 and the pixel current potential lateral capacitance electrode of pixel electrode 9a on electric.More particularly, bottom capacitance electrode 731, on electric, connect in the pixel electrode side source-drain area through contact hole 89, the contact hole 85c (with reference to Figure 12) of perforate through running through the 2nd interlayer dielectric 42 and dielectric film 75, be connected to the relay layer 93c that is configured in the same one deck of data line 6c (that is, the 4th layer) described later on electric.In addition, relay layer 93c (with reference to Figure 12) connects pixel electrode 9a through the contact hole 84c (with reference to Figure 12) in 43 perforates of the 3rd interlayer dielectric on electric.That is, bottom capacitance electrode 731 and relay layer 93c together, being electrically connected between relaying pixel electrode side source-drain area 5e and pixel electrode 9a.Bottom capacitance electrode 731 is formed by the polysilicon of electric conductivity.

In addition, as Figure 11 and shown in Figure 12, in the present embodiment, memory capacitance 73 forms to such an extent that cover contact hole 830.Therefore, memory capacitance 73 has the concavity part that forms along the surface of the recess that produces because of contact hole 830 on the upper layer side surface of the 1st interlayer dielectric 41.As what in above-mentioned the 1st embodiment, describe in detail with reference to Fig. 7 to Fig. 9, memory capacitance 70 has the concavity part 70t that forms along the surface of the recess 710 that produces on the upper layer side surface of the 1st interlayer dielectric 41 because of contact hole 810, in this, roughly be same.

Structure-data line of the 4th layer etc.

In Figure 13, data line 6c is set as the 4th layer.In addition, in the 4th layer, relay layer 93c (with reference to Figure 12) and data line 6c are formed by same film.

As Figure 12 and shown in Figure 13, data line 6c has along the main line part 6cy of Y direction extension and the extension 6cx that extension is provided with from this main line part branch along directions X.Data line 6c on this part 6cx that extend to be provided with, is connected to the data line side source-drain area 5d of semiconductor layer 5a on electric through the contact hole 87 that runs through the 1st interlayer dielectric 41, dielectric film 75 and the 2nd interlayer dielectric 42.

In Figure 12, relay layer 93c, on interlayer dielectric 42, with same one deck of data line 6a (with reference to Figure 13) on form.

Structure-pixel electrode of the 5th layer etc.

In Figure 13, pixel electrode 9a is set as the 5th layer.Pixel electrode 9a forms across the upper layer side of the 3rd interlayer dielectric at data line 6c.

As Figure 12 and shown in Figure 13, pixel electrode 9a, through bottom capacitance electrode 731, contact hole 89,84c and 85c and relay layer 93c are connected to the pixel electrode side source-drain area 5e of semiconductor layer 5a on electric.

The above structure of Shuo Ming pixel portions, as Figure 11 and shown in Figure 12, each pixel portions all is the same.At image display area 10a (with reference to Fig. 1), form such pixel portions periodically.

Then, when describing the shape of memory capacitance in detail, describe sweep trace according to the liquid-crystal apparatus of present embodiment, gate electrode in detail, be connected the flat shape of the contact hole between sweep trace and the gate electrode on electric with reference to Figure 14.

Figure 14 is among the 3rd embodiment and the planimetric map same intention of Fig. 7.

In Figure 14, sweep trace 13, as above described with reference to Figure 11, have the main line part 13a along directions X, the extension 13b that extension is provided with from main line part 13a along the Y direction.Extension 13b is by forming to such an extent that overlap the part 13b1 on the main line part 6cy of data line 6c and forming at the part 13b2 that pixel electrode side LDD district 5c side forms as benchmark with data line 6c.Part 13b2 by forming in this pixel electrode side LDD district 5c side can improve the light-proofness to the pixel electrode side LDD district 5c of relatively easy generation light leakage current, can reduce the light leakage current that flows through TFT35 effectively.

The contact hole 830 of perforate is connected on electric gate electrode 33 through running through gate insulating film 2 and underlayer insulating film 12 with sweep trace 13.

As shown in figure 14, in the present embodiment, particularly, contact hole 830 has, on the plane of tft array substrate 10, see the part 1 831 that prolongs along directions X in semiconductor layer 5a side, part 2 832 overlapping and that prolong along the Y direction with the part of the main line part 6cy of data line 6c.That is, contact hole 830 connects part 1 831 and part 2 832, we can say the flat shape with L word sigmoid.In addition, as above described with reference to Figure 11, gate electrode 33 has, overlap on the channel region 5a ' of TFT35 main part 33a and from this main part 33a and the extension 331 and 332 that is provided with contact hole 830 overlap extensions.Setting is extended along directions X in extension 331, covers the part 1 831 of contact hole 830, and setting is extended along the Y direction in extension 332, covers the part 2 832 of contact hole 830.Thereby the part of extension 331 forms in the part 1 831 of contact hole 830 and sweep trace 13 (part of extension 13b2 in more detail) contact.Similarly, the part of extension 332 forms in the part 2 832 of contact hole 830 and sweep trace 13 (part of extension 13b1 in more detail) contact.

Because such formation and above-mentioned the 1st embodiment are roughly similarly, when keeping high aperture, can reduce the contact resistance between gate electrode 33 and the sweep trace 13.

Promptly, in the present embodiment, particularly, as mentioned above, contact hole 830 is owing to have part 1 831 and part 2 832, for example have as the situation of the Typical Planar shape of general contact hole such as circle, square or supposition contact hole with supposition contact hole 830 and to compare, can enlarge the region area that forms this contact hole 830 in limited non-open area by any one situation about forming in part 1 831 and the part 2 832.Thereby, in the resistance that reduces between gate electrode 33 and the sweep trace 13, can improve aperture opening ratio.

In addition, in the present embodiment, particularly, as mentioned above, the part 1 831 of contact hole 830 prolongs along directions X in the side of semiconductor layer 5a.More particularly, part 1 831, form the side of the semiconductor layer 5a that extends along directions X, separate predetermined distance L2, form strip along directions X.

Thereby the gate electrode 33 that forms in part 1 831 (see on three-dimensional or rather, extension 331, forms wall shape occulter along semiconductor layer 5a by) a part.Thereby, can pass through the light that part 1 831 (part of the gate electrode 33 that forms or rather) is blocked oblique incidence semiconductor layer 5a in part 1 831.That is,, can strengthen the light-proofness of the light that blocks the oblique incidence semiconductor layer by forming the part 1 831 that is configured near the wall shape occulter the semiconductor layer 5a.As a result, the flicker and the pixel that can reduce in the image demonstration is irregular.

As shown in figure 14, constitute the top capacitor electrode 330a of memory capacitance 73, have the 1st electrode part 330a1 of cover data line side LDD district 1b and the 2nd electrode part 330a2 of covering pixel electrode side LDD district 5c.In addition, constitute the bottom capacitance electrode 731 of memory capacitance 73, have the 1st electrode part 731a of cover data line side LDD district 5b and the 2nd electrode part 731b of covering pixel electrode side LDD district 5c.

Thereby, can block from the light of upper layer side incident data line side LDD district 5b by the 1st electrode part 330a1 and 731a.In addition, can block from the light of upper layer side incident pixel electrode side LDD district 5c by the 2nd electrode part 330a2 and 731b.Thereby, can reduce the generation of the light leakage current among data line side LDD district 5b and the pixel electrode side LDD district 5c.

In the present embodiment, particularly, memory capacitance 73 forms to such an extent that cover the recess that produces because of contact hole 830 on the 1st interlayer dielectric 41 upper layer side surfaces, possesses the concavity part that has along the concavity section shape of recess surface.

Promptly, in the underlayer insulating film 12 and gate insulating film 2 of the lower layer side that is configured in the 1st interlayer dielectric 41, owing to form contact hole 830, on the upper layer side surface of the 1st interlayer dielectric 41, roughly along the recess that produces at the inwall of for example contact hole 830 because of contact hole 830.Memory capacitance 73, by forming to such an extent that cover this recess, its part forms in recess, possesses the concavity part that has along the concavity section shape of recess surface.As what in above-mentioned the 1st embodiment, describe in detail with reference to Fig. 7 to Fig. 9, memory capacitance 70, having the concavity part 70t that forms along the surface of the recess 710 that produces on the upper layer side surface of the 1st interlayer dielectric 41 because of contact hole 810, is roughly the same in this.

Thereby memory capacitance 73 is by having the concavity part, and capacitance increases.Thereby, can improve the current potential retention performance among the pixel electrode 9a.In other words, do not have concavity situation partly (promptly with memory capacitance 73,73 situations about forming in the plane of memory capacitance) compare, can be made into narrow region on the tft array substrate 10 to memory capacitance 73 with capacitance of realizing the desired display performance of goods.Thereby it is irregular just can to reduce flicker and the pixel of image in showing, in addition, and miniaturization that can implement device.

In addition, owing to recess produces because of contact hole 830, this recess (and concavity part) has the flat shape roughly the same with the flat shape of contact hole 830 (omitting among the figure).In other words, the concavity part is seen on the plane of tft array substrate 10, has in the side of semiconductor layer 5a the part of main line part 6cy of the part that prolongs along directions X and data line 6c part overlapping and that prolong along the Y direction.Thereby, can easily partly be configured in concavity in the non-open area, cause the decline of aperture opening ratio hardly, can increase the capacitance of memory capacitance 73.

As mentioned above, if employing is kept high aperture according to the liquid-crystal apparatus of present embodiment in former state, when increasing the capacitance of memory capacitance 73, can reduce the generation of light leakage current among the TFT35.The result is to realize that high-quality image shows.

Electronic equipment

Then, illustrate the situation that is applied to various electronic equipments as the liquid-crystal apparatus of above-mentioned electro-optical device with reference to Figure 15.

Figure 15 is the planimetric map of the structure example of expression projector.Below, just this liquid-crystal apparatus is done an explanation as the projector that light valve adopts.

As shown in figure 15, in projector 1100 inside, the lamp unit of being made up of white light sources such as Halogen lamp LEDs 1102 is set.1102 projection lights that penetrate by being configured in 4 pieces of catoptrons 1106 and the 2 pieces of dichronic mirrors 1108 in the photoconduction 1104, are separated into the RGB3 primary colors from the lamp unit, and incident is as liquid crystal panel 1110R, 1110B, the 1110G of the light valve corresponding with each primary colors.

The structure of liquid crystal panel 1110R, 1110B and 1110G, identical with above-mentioned liquid-crystal apparatus, R, the G that provides from imaging signal processing circuit, the primary signal of B are driven respectively.Then, the light by the modulation of these liquid crystal panels is from 3 direction incident colour splitting prisms 1112.In this dichromatism prism 1112, bendingof light 90 degree of R and B, on the other hand, G light directly advances.Thereby, the result that each color image is synthetic, through projection lens 1114, colour image projection on screen etc.

Wherein, if be conceived to the demonstration picture of each liquid crystal panel 1110R, 1110B and 1110G formation, then the demonstration picture of liquid crystal panel 1110G formation must reverse about the demonstration picture with respect to 1110R, 1110B formation.

In addition, at liquid crystal panel 1110R, among 1110B and the 1110G, because corresponding to R, therefore G, the light of each primary colors of B needn't be provided with chromatic filter by dichronic mirror 1108 incidents.

In addition, except that electronic equipment with reference to Figure 15 explanation, can also enumerate mobile personal computing machine, portable phone, LCD TV, the type of finding a view, monitor direct viewing type video tape recorder, auto-navigation system device, beeper, electronics miscellanies basis, desk-top computer, word processor, workstation, videophone, POS terminal, have the device of touch-screen etc.Then, they certainly are applied to various electronic equipments.

The present invention in addition, except the liquid-crystal apparatus of explanation in the above-described embodiments, on silicon substrate, form element reflective liquid crystal device (LCOS), plasma scope (PDP), electric field release type display (FED, SED), OLED display, digital micro-mirror device (DMD), electrophoretic apparatus etc. also can be suitable for.

The present invention under the situation that does not break away from its spirit and essential characteristic, also can realize with other forms of determining.Thereby, present embodiment, have a few and all should regard illustration as, and be not limited thereto, scope of the present invention, be above-mentioned explanation, not equal to represent by the scope of appended claim.Drop on and the meaning of the scope equivalence of claim and the change of scope, all be included in the present invention.

The Japanese patent application No. 2006-338049 that the Japanese patent application No. 2006-338048 that on Dec 15th, 2006 filed an application and on Dec 15th, 2006 file an application, comprise that scope, the accompanying drawing of instructions, claim and whole disclosures of making a summary are incorporated into this instructions as a whole, as a reference.

Claims (16)

1. electro-optical device is characterized in that possessing on substrate:

Cross one another data line and sweep trace;

Pixel electrode, it was provided with accordingly with intersecting of this data line and sweep trace; With

Transistor, it is arranged on intersecting in the corresponding intersection region with above-mentioned in the non-open area spaced apart from each other, the open area of pixel, comprise: (i) semiconductor layer, it is across the 1st dielectric film, be configured on the layer that differs from one another with above-mentioned sweep trace, formation has the long channel region of raceway groove along the 1st direction of above-mentioned data line extension, (ii) gate electrode, it is with respect to this semiconductor layer, be configured in across gate insulating film on the layer of an opposite side with above-mentioned sweep trace, overlapping with above-mentioned channel region;

Wherein, on above-mentioned the 1st dielectric film and above-mentioned gate insulating film, be formed for being electrically connected the contact hole of above-mentioned gate electrode and above-mentioned sweep trace, it is seen on the aforesaid substrate plane, have: part 1 prolongs along above-mentioned the 1st direction in above-mentioned semiconductor layer side; And part 2, overlapping with the part of above-mentioned sweep trace, and prolong along the 2nd direction that above-mentioned sweep trace extends.

2. the electro-optical device of claim 1 record is characterized in that,

Above-mentioned gate electrode has: overlap the main part on the above-mentioned channel region; With from main part, on the aforesaid substrate plane, see, extending the gate electrode extension of setting with the overlapping mode of above-mentioned contact hole,

Above-mentioned sweep trace has: along the main line part of above-mentioned the 2nd direction extension; With from this main line partly, on the aforesaid substrate plane, see, to extend the sweep trace extension of setting with the overlapping mode of above-mentioned part 1.

3. the electro-optical device of claim 1 record is characterized in that,

Above-mentioned semiconductor layer has: the 2nd interface that is connected electrically to the data line side source-drain area of above-mentioned data line, the pixel electrode side source-drain area that is connected electrically to pixel electrodes, the 1st interface that forms and forms between above-mentioned channel region and pixel electrodes side source-drain area between above-mentioned channel region and above-mentioned data line side source-drain area;

Above-mentioned part 1 is along at least one square one-tenth in the above-mentioned the 1st and the 2nd interface.

4. the electro-optical device of claim 3 record is characterized in that,

Above-mentioned contact hole is seen on the aforesaid substrate plane, forms in the both sides of above-mentioned semiconductor layer,

Above-mentioned part 1 is arranged on the above-mentioned the 1st and at least one side's in the 2nd interface both sides.

5. the electro-optical device of claim 3 record is characterized in that,

Above-mentioned part 1 is seen on the aforesaid substrate plane, is provided with along above-mentioned the 2nd interface.

6. the electro-optical device of claim 3 record is characterized in that,

The the above-mentioned the 1st and the 2nd interface is the LDD district.

7. the electro-optical device of claim 1 record is characterized in that,

Above-mentioned sweep trace is configured in the lower layer side of above-mentioned semiconductor layer.

8. the electro-optical device of claim 1 record is characterized in that,

Above-mentioned gate electrode and above-mentioned sweep trace comprise the light-proofness conductive material.

9. the electro-optical device of claim 1 record is characterized in that,

The width of above-mentioned part 1 is narrower than the width of above-mentioned part 2.

10. the electro-optical device of claim 1 record is characterized in that,

Also have across the 2nd dielectric film, be configured in above-mentioned transistorized upper layer side, and the memory capacitance that in above-mentioned non-open area, forms,

This memory capacitance forms in the mode that covers the recess that produces on above-mentioned the 2nd dielectric film upper layer side surface because of above-mentioned contact hole, possesses the concavity part that has along the concavity section shape of recess surface.

11. the electro-optical device of claim 10 record is characterized in that,

Above-mentioned semiconductor layer has: be electrically connected above-mentioned data line data line side source-drain area, be electrically connected the 1st interface that forms between the pixel electrode side source-drain area of pixel electrodes, above-mentioned channel region and the above-mentioned data line side source-drain area and the 2nd interface that between above-mentioned channel region and pixel electrodes side source-drain area, forms;

Above-mentioned memory capacitance is seen on the aforesaid substrate plane, and is overlapping with above-mentioned the 2nd interface at least.

12. the electro-optical device of claim 10 record is characterized in that,

Above-mentioned memory capacitance comprises the light-proofness conductive material.

13. the electro-optical device of claim 11 record is characterized in that,

Above-mentioned memory capacitance has: the 1st capacitive part of extending and cover above-mentioned the 1st interface along above-mentioned the 1st direction; With width 2nd capacitive part wideer that covers above-mentioned the 2nd interface and above-mentioned the 2nd direction than above-mentioned the 1st capacitive part.

14. an electro-optical device is characterized in that possessing on substrate:

Cross one another data line and sweep trace;

Pixel electrode, it was provided with accordingly with intersecting of this data line and sweep trace; With

Transistor, it is arranged on intersecting in the corresponding intersection region with above-mentioned in the non-open area spaced apart from each other, the open area of pixel, comprise: (i) semiconductor layer, it is configured on the layer that differs from one another with above-mentioned sweep trace across the 1st dielectric film, forms the long channel region of raceway groove that has along the direction of above-mentioned sweep trace extension, (ii) gate electrode, it is configured in across gate insulating film on the layer of an opposite side with above-mentioned sweep trace with respect to this semiconductor layer, and is overlapping with above-mentioned channel region;

Wherein, on above-mentioned the 1st dielectric film and above-mentioned gate insulating film, be formed for being electrically connected the contact hole of above-mentioned gate electrode and above-mentioned sweep trace, it is seen on the aforesaid substrate plane, have: part 1, the direction of extending along above-mentioned sweep trace in above-mentioned semiconductor layer side prolongs; And part 2, overlapping and prolong with the part of above-mentioned data line along the direction that above-mentioned data line extends.

15. the electro-optical device of claim 14 record is characterized in that,

Also have across the 2nd dielectric film, be configured in above-mentioned transistorized upper layer side, and the memory capacitance that in above-mentioned non-open area, forms,

This memory capacitance forms in the mode that covers the recess that produces on above-mentioned the 2nd dielectric film upper layer side surface because of above-mentioned contact hole, possesses the concavity part that has along the concavity section shape of recess surface.

16. an electronic equipment is characterized in that,

Electro-optical device with claim 1 record.

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