CN101188222A - 集成电路及其制作方法 - Google Patents
集成电路及其制作方法 Download PDFInfo
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- CN101188222A CN101188222A CN200710137031.1A CN200710137031A CN101188222A CN 101188222 A CN101188222 A CN 101188222A CN 200710137031 A CN200710137031 A CN 200710137031A CN 101188222 A CN101188222 A CN 101188222A
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
本发明提供一种集成电路及其制作方法。上述集成电路,包含蚀刻停止层,形成于基底上;起始层,形成于该蚀刻停止层上,且该起始层具有高消光系数;低介电常数的介电层,形成于该起始层的上方;以及形成金属线于该低介电常数的介电层之中。本发明可降低在固化步骤所引起的应力转变,因此蚀刻停止层可以是具有较低介电常数的介电材料,而且也会降低晶圆龟裂的可能。
Description
技术领域
本发明有关于集成电路,特别是有关于集成电路中内连线结构的制作方法。
背景技术
一般而言,半导体装置中使用导电线或内连线结构来连接集成电路内的元件及外部的接合焊盘。在形成互连线结构时,金属线间的寄生电容(parasiticcapacitance)是一个十分重要的问题。上述寄生电容会导致电阻电容延迟(RCdelay)的增加。在一些高速电路中,互连线的电容可能会成为集成电路运作速度的限制因素。因此,降低互连线电容,可制作合适的集成电路的互连线结构。由此,也大大增加低介电常数(low-k)材料的使用。
图1显示制作具有低介电常数的介电层的互连线结构的中间步骤。在形成铜线4于介电层2之中后,形成蚀刻停止层(etch stop layer;ESL),接着再形成低介电常数的介电层8。上述蚀刻停止层6的主要目的是用来终止低介电常数的介电层8的蚀刻工艺。另外,蚀刻停止层6会提供压缩应力至上方及/或下方的介电层。一般而言,低介电常数的介电层具有内部的拉伸应力(tensile stress),使得低介电常数的介电层的厚度接近所谓的龟裂临界点(cracking threshold)时,具有拉伸应力的低介电常数的介电层的堆叠层(例如图1中的介电层2及低介电常数的介电层8)会很容易地产生龟裂现象。因此,一般而言,会形成具有内在压缩应力的蚀刻停止层6,使得可提供支撑半导体装置的结构,以预防上方及下方的低介电常数的介电层免于龟裂。
在沉积低介电常数的介电层8之后,进行紫外线固化(UV curing)步骤,以驱离低介电常数的介电层8内的成孔剂(porogen),使得在低介电常数的介电层中形成孔洞。然而,由于紫外线会穿透低介电常数的介电层8,因此紫外线固化步骤,也会影响蚀刻停止层6。一般而言,在紫外线曝光后,在蚀刻停止层6的应力会转变朝向拉伸边(tensile side)。例如,实施例的蚀刻停止层起初的压缩压力(compressive stress)约为281MPa,当曝光于紫外线约9分钟后,上述压缩应力会转变成约290MPa的拉伸应力。若曝光于紫外线超过九分钟,上述拉伸应力会更增加至约481MPa。
在传统中,解决上述问题的其中一种方法,是在沉积时,形成具有超高压缩应力的蚀刻停止层。上述超高压缩的应力,甚至在紫外线固化后导致蚀刻停止层的应力转变朝向拉伸边时,虽然上述超高压缩应力会变小,但蚀刻停止层的最终应力仍可保持是压缩应力。然而,上述方式仍具有缺点。一般来说,较高压缩应力的蚀刻停止层具有较高的介电常数,会导致电阻电容延迟的衰退,且较高压缩应力也会导致晶圆的龟裂。另外,由于较高压缩应力的制作方式较为复杂,因此也会降低生产量。
因此,亟需要一种新的集成电路及其制作方法,以解决上述的问题。
发明内容
有鉴于此,本发明的第一目的在于提供一种集成电路。上述集成电路,包含蚀刻停止层,形成于基底上;起始层,形成于该蚀刻停止层上,且该起始层具有高消光系数;以及低介电常数的介电层,形成于该起始层的上方。
上述集成电路还包含金属线及导通孔,形成于该低介电常数的介电层之中。
如上所述的集成电路,其中该起始层的消光系数大于或等于0.11,而该起始层的折射率大于或等于1.75。
如上所述的集成电路,其中起始层包括选自硅、氧、碳、氢及其组合的群组的材质。
如上所述的集成电路,其中起始层的厚度介于70纳米至450纳米之间。
如上所述的集成电路,其中该蚀刻停止层包含一压缩应力。
如上所述的集成电路,其中该低介电常数的介电层的介电常数小于2.5。
如上所述的集成电路,其中该蚀刻停止层包括选自碳氮化硅、氧氮化硅、碳化硅、氮化硅、氧碳化硅及其组合的群组的材料。
本发明的第二目的在于提供一种半导体结构。上述半导体结构,包含介电层,形成于半导体基底上;包含碳氮化硅的蚀刻停止层,形成于该介电层上方;起始层,形成于该蚀刻停止层上,且对于固化时的紫外线,该起始层具有大于或等于0.11的消光系数及大于或等于1.75的折射率;低介电常数的介电层,形成于该起始层;以及铜图案,形成于该低介电常数的介电层之中。
上述半导体结构,其中该起始层为该低介电常数的介电层及该蚀刻停止层的粘着促进层(adhesion promoter)。
本发明的第三目的在于提供一种集成电路的制作方法。上述集成电路的制作方法,包括形成介电层于半导体基底上;形成蚀刻停止层于该介电层上;形成起始层于该蚀刻停止层上,且对于紫外线,该起始层具有大于或等于0.11的消光系数;形成低介电常数的介电层于该起始层上;以及以该紫外线,固化该低介电常数的介电层。
如上所述的集成电路的制作方法,其中形成该起始层的方式由等离子体加强式化学气相沉积法完成。
如上所述的集成电路的制作方法,其中形成该起始层的工艺条件包括:介于250℃至350℃之间的晶圆温度;介于1托至10托之间的反应室压力;以及介于100瓦至500瓦之间的射频功率。
如上所述的集成电路的制作方法,其中形成该起始层的工艺条件,包括:提供介于100sccm至500sccm之间的前驱物流量,其中该前驱物包含二甲基二乙氧基硅烷及氧气。
如上所述的集成电路的制作方法,其中该固化步骤的紫外线波长范围介于200纳米至300纳米之间。
如上所述的集成电路的制作方法,其中形成该起始层的步骤,还包括:决定该紫外线的波长;以及依据该紫外线的波长,调整形成该起始层的工艺条件,以增加该起始层的消光系数。
本发明的第四目的在于提供一种集成电路的制作方法。上述集成电路的制作方法,包括形成具有压缩应力的蚀刻停止层于半导体基底上;形成低介电常数的介电层于该蚀刻停止层上;以紫外线,固化该低介电常数的介电层;以及通过形成阻挡层于该低介电常数的介电层与该蚀刻停止层之间,以减低照射至该蚀刻停止层的紫外线,其中调整形成该阻挡层的工艺条件,以增加该紫外线穿透该阻挡层的衰减率。
上述集成电路的制作方法,其中该阻挡层与该蚀刻停止层及该低介电常数的介电层间的粘着性优于该低介电常数的介电层与该蚀刻停止层间的粘着性。
通过蚀刻停止层上方的紫外线阻挡层,可降低在紫外线固化时,蚀刻停止层内应力的转变。
本发明可降低在固化步骤所引起的应力转变,因此蚀刻停止层可以是具有较低介电常数的介电材料,而且也会降低晶圆龟裂的可能。
附图说明
接下来,配合附图说明,以更加了解本发明及其优点,其中:
图1显示制作包含低介电常数的介电层的互连线结构的中间步骤的剖面图;以及
图2-图6显示制作本发明优选实施例的中间步骤的剖面图。
其中,附图标记说明如下:
现有技术
2~介电层;4~铜线;
6~蚀刻停止层;8~低介电常数的介电层。
本发明实施例
10~半导体基底; 20~介电层; 22~金属线;
24~蚀刻停止层; 26~起始层; 28~低介电常数的介电层;
30~导通孔开口; 32~沟槽开口; 52~扩散阻挡层;
54~导通孔; 56~金属线。
具体实施方式
接下来,详细说明本发明优选实施例的制作及使用。然而,可以了解的是,本发明提供许多可应用于各种不同的广泛领域的发明概念。因此,实施例仅是用来说明制作及使用本发明的具体实施方式,并不用以限制本发明。
本发明提供一种新的形成内连线结构的方法,且以制作本发明的优选实施例的中间步骤作为说明。在本发明的说明的实施例及附图中,相同的元件符号代表相同的元件。虽然,本发明的优选实施例以双镶嵌式工艺(dualdamascene process)说明,但可以了解的是,本领域技术人员通过本发明公开的内容,当可应用于单镶嵌式工艺(single damascene process)。
图2显示一种介电层20中形成有金属线22的起始结构。上述金属线22及介电层20形成于半导体基底10上方,且上述半导体基底10优选可以在上方形成有半导体元件的硅基底。在实施例中,金属线22优选可以是例如铜(copper)、钨(tungsten)、铝(aluminum)、银(sliver)、金(gold)或其组合的金属材质。上述金属线22可用以连接下方的元件(未显示),例如导通孔(via)或接触插塞(contact plug)。在实施例中,介电层20可以是层间介电层(inter-layerdielectric;ILD)或金属层间介电层(inter-metal dielectric;IMD),且介电层20优选可以是具有低介电常数(low-k)的介电材质。为了简化说明,后续附图的半导体基底10可以被省略。
在图3中,形成蚀刻停止层(etch stop layer;ESL)24于介电层20的上方之后,接着形成起始层(initiation layer)26。在优选实施例中,蚀刻停止层24可以是碳氮化硅(silicon carbonitride;SiCN),且蚀刻停止层24的厚度优选可以是介于150埃(angstrom;)至550埃(angstrom;)之间。当然,上述蚀刻停止层24也可以是例如氮化硅(silicon nitride;SiN)、氧碳化硅(silicon oxycarbide;SiOC)、碳化硅(silicon carbide;SiC)、氮氧化硅(silicon oxynitride;SiON)及其相似物。在实施例中,形成上述蚀刻停止层24的方式可以是等离子体加强式化学气相沉积(plasma enhanced chemical vapor deposition;PECVD)法或其它合适的方式。在具体实施例中,用来形成蚀刻停止层24的前驱物(precursor)可以是包括四甲基硅烷(tetramethylsilane;4MS)及氨气(NH4),且形成蚀刻停止层24时的晶圆温度范围可以是介于345℃至350℃之间,优选为350℃。
形成上述起始层26于蚀刻停止层24上,且起始层26可作为粘着促进层(adhesion promoter)。起始层26对于其下方的蚀刻停止层24及后续形成于起始层26上方的低介电常数的介电层间的粘着性优于直接形成于蚀刻停止层24上方的低介电常数的介电层与蚀刻停止层24间的粘着性,由此,起始层26可增加蚀刻停止层24与后续形成的低介电常数的介电层的粘着性。在实施例中,起始层26优选可以是包括硅、氧、碳、氢或其组合的材质。
上述起始层26也可以作为紫外线阻挡层(UV blocker layer),因此在本说明书中也可称为紫外线阻挡层。当形成低介电常数的介电层在起始层26上方,且进行紫外线固化步骤,以固化上述低介电常数的介电层时,起始层26会尽可能的阻挡大量的紫外线,使得起始层26下方的蚀刻停止层24会尽可能照射较少量的紫外线。在优选实施例中,起始层26具有相对较高的消光系数(extinction coefficient;k)及/或相对较高的折射率(refractive index;n)。如公知的,较高的消光系数及折射率,特别是较高的消光系数,较有利于降低紫外线的穿透。在实施例中,上述起始层26的消光系数优选可以是约大于或等于0.11,而起始层26的折射率优选可以是约大于或等于1.74。在实施例中,上述起始层26的厚度优选可以是介于0.7纳米至45纳米(nm)之间,且优选由等离子体加强式化学气相沉积法、高密度等离子体化学气相沉积(high-density plasma chemical vapor deposition;HDPCVD)法、次常压化学气相沉积(sub-atmospheric chemical vapor deposition;SACVD)法或其它合适的方式形成。
可以发现到,起始层26的消光系数及折射率会明显地受到工艺条件的影响。在一个研究工艺条件对起始层的消光系数及折射率影响的实验中,以一组工艺条件形成第一实验例的起始层,且测量其消光系数及折射率。接着,改变工艺条件,以形成不同实验例的起始层。结果显示,通过降低反应室的压力、降低二甲基二乙氧基硅烷(dimethyldiethylsilane;mDEOS)的流量、降低射频功率(RF power)及/或降低氧气的流量的方式,所形成的实验例的起始层的消光系数及折射率较高于第一实验例的起始层的消光系数及折射率。由此,可以明显的看出,工艺条件对消光系数及折射率的影响。
在优选实施例中,形成起始层26优选可以是,包括介于约250℃至约350℃的晶圆温度、介于约1托(torr)至约10托(torr)的反应室压力、介于约100瓦至500瓦的射频功率,以及介于约100sccm(立方厘米/分钟)至500sccm(立方厘米/分钟)的前驱物(precursor)流量的工艺条件,其中上述前驱物优选可以是包括二甲基二乙氧基硅烷及氧气。上述氧气的流量可以是低于450sccm,甚至可以不提供氧气。另外,上述反应室可以包括承载气体,例如氦(helium)、氩(argon)、氮(nitride)及/或其它的惰性气体。
在具体实施例中,实验例的起始层26可以是与起始层26上方的低介电常数的介电层同一步骤形成,且可以是在约260℃的晶圆温度、约4托的反应室压力及约300瓦的射频功率的工艺条件下制作。值得注意的是,上述具体实施例中,前驱物可以是仅包括二甲基二乙氧基硅烷(未加入氧气)。在本具体实施例中,可是使用氦气作为承载气体,且二甲基二乙氧基硅烷与氦气的流量比可以是约0.04。接着,测量上述起始层26的消光系数及折射率,在波长约248纳米的紫外线下,本具体实施例中的实验例起始层的折射率约1.74,及消光系数约0.11。而,在波长约193纳米的紫外线下,上述实验例起始层的折射率约1.85,且消光系数约0.2。
如图4所示,形成低介电常数的介电层28,以作为金属层间的隔离层。由此,低介电常数的介电层28也可以称为金属层间介电层。上述低介电常数的介电层28的介电常数优选可以是小于约3.5,其介电常数也可以是更优选的小于2.5(因此,低介电常数的介电层也可以称为极低介电常数(extremelow-k;ELK)介电层。上述低介电常数的介电层28可以是具有成孔剂(porogen)的含碳材质。低介电常数的介电层28可以是以化学气相沉积法的方法形成,优选也可以是以等离子体加强式化学气相沉积法的方式形成。当然,上述低介电常数的介电层28也可以是低压化学气相沉积(low-pressure chemicalvapor deposition;LPCVD)法、原子层气相沉积(atomic layer chemical vapordeposition;ALCVD)法或旋转涂布(spin-on)的沉积方式形成。在优选实施例中,低介电常数的介电层28可以是包含硅、氧、碳、氢或其组合的材质。在具体实施例中,形成上述低介电常数的介电层的前驱物可以是包括二甲基二乙氧基硅烷、氧气及1-异丙基-4-甲基-1.3-环己二烯(1-isopropyl-4-methyl-1.3-cyclohexadiene)的有机化合物(由原子转移自由基聚合的方式形成)。在优选实施例中,低介电常数的介电层28优选可以是与起始层26在同一步骤形成。
如公知地,消光系数与折射率为紫外线波长的函数,且在不同波长的紫外线下,所测量的消光系数及折射率也不同。因此,在优选实施中,还包括预先决定紫外线的波长,以及决定形成具有高消光系数及折射率的起始层的理想工艺条件的步骤。
接着,进行紫外线固化步骤(UV curing),其中紫外线固化步骤可以是在等离子体加强式化学气相沉积、原子层气相沉积、低压化学气相沉积等的生产设备中进行。在固化步骤的具体实施例,可以是利用紫外线照射设备(ultraviolet radiator tool)的方式完成固化步骤。上述紫外线的波长优选可以是介于200纳米至300纳米之间。上述紫外线的波长当然也可以是小于或大于上述波长的范围。由于消光系数是紫外线波长的函数,在形成起始层26之后,测量不同紫外线对起始层26的消光系数,且选择紫外线的波长,使其对应较高的起始层26消光系数,以进行后续的紫外线固化步骤。上述紫外线固化步骤也具有驱离低介电常数的介电层28内的成孔剂的作用,以改善低介电常数的介电层28的机械性质。在上述驱离成孔剂之后,接着会在低介电常数的介电层28之中产生孔洞,使得降低其介电常数。
在紫外线固化的步骤中,紫外线会穿透低介电常数的介电层28。而,具有高消光系数及高折射率的起始层26会减弱大部分照射至起始层26下方的蚀刻停止层24的紫外线,因此,起始层26可作为紫外线阻挡层。由此,可降低蚀刻停止层24中应力调变(stress modulation)现象的发生(应力转变至拉伸边)。
在图5中,形成导通孔开口30及沟槽开口32于低介电常数的介电层28之中。实施例中,以非等向性干蚀刻(anisotropic dry etching),切开低介电常数的介电层28,且终止于蚀刻停止层24,以形成上述导通孔开口30。接着,再形成沟槽开口32。在另一实施例中,形成导通孔开口30及沟槽开口32的方式可以是沟槽优先(trench-first)制作的方式,其中沟槽优先制作的方式指在形成导通孔开口30之前,先形成沟槽开口32。在形成导通孔开口30及沟槽开口32之后,接着,通过导通孔开口30移除蚀刻停止层30,以暴露下方的金属线22。
图6显示形成扩散阻挡层52、导通孔54及金属线56。在图6中,形成优选例如是钛(titanium)、钽(tantalum)、氮化钛(titanium nitride)、氮化钽(tantalum nitride)及其相似物的扩散阻挡层52于导通孔开口30及沟槽开口32之中。上述扩散阻挡层52可防止特别是铜的导通孔材料扩散至低介电常数的介电层28之中,进而避免因导通孔材料扩散至低介电常数的介电层28之中所引起的电路失效(circuit degradation)。在完成上述扩散阻挡层52后,形成籽晶层(未显示)于扩散阻挡层52上方之后,接着,填充导电材料于导通孔开口30及沟槽开口32之中。上述导电材料优选可以是包括铜、钨、金属合金(metal alloy)、金属硅化物(metal silicide)、氮化金属(metal nitride)或其相似物的金属材料。接着,通过化学机械研磨(chemical mechanical polish;CMP),移除多余的金属材料,以形成金属线56及导通孔54。
可以了解的是,若固化步骤对蚀刻停止层的应力会有不利的影响,上述优选实施例中的固化步骤,除了可以是紫外线固化的方式外,也可以是电子束固化(e-Beam curing)、激光固化(laser curing)或其类似的方式进行固化步骤。
进行实验,以验证起始层26的效果。在第一实验例的元件中,形成具有消光系数为2E4及折射率为1.5的起始层于蚀刻停止层上。在第二实验例的元件中,形成具有消光系数为0.11及折射率为1.7的优选的起始层于与第一实验例相同的蚀刻停止层上。在第三实验例的元件中,形成与上述第一实验例相同的蚀刻停止层,且其上方并未形成起始层。接着,在波长约为248纳米的紫外线下曝光上述实验例的元件。在进行上述紫外线曝光后(第一次紫外线曝光),可以发现,在第一实验例的元件中,其起始层具有相对较低的消光系数及相对较低的折射率,且第一实验例的元件中蚀刻停止层的应力转变约小于19%的未形成起始层的第三实验例的元件中蚀刻停止层的应力转变。在第二实验例的元件中,其起始层具有相对较高的消光系数及相对较高的折射率,且第二实验例的元件中蚀刻停止层的应力转变约小于34%的未形成起始层的第三实验例的元件中蚀刻停止层的应力转变。也就是说,由于紫外线曝光,起始层会明显地降低蚀刻停止层内应力的转变,特别是具有高消光系数及高折射率的起始层,更可降低蚀刻停止层内应力的转变。若再进行一次紫外线曝光(第二次紫外线曝光),其对应的蚀刻停止层的应力转变,在第一实验例的元件中的蚀刻停止层约为11%,而在第二实验例的元件中的蚀刻停止层约为28%。
通过上述实施例中的方式,可降低在固化步骤所引起的应力转变。因此,在沉积时,蚀刻停止层并不需要很高的压缩应力。由此,蚀刻停止层可以是具有较低介电常数的介电材料,而且也会降低晶圆龟裂的可能。
虽然本发明及其优点已详细说明如上,可以了解到的是,不同的变化、组成及替换在不脱离本发明的精神及范围内皆应属于本发明的范围。再者,本发明的范围并不局限于说明书所叙述的工艺、机构、制造、组成、功能、制作方法以及步骤的特定实施例。本领域技术人员很轻易了解到,从本发明公开的制造工艺、机构、制造、组成、功能、制作方法或步骤,并且根据本发明利用目前存在的或之后将发展的,其可大体上完成与上述对应的实施例中相同的功能或可大体上达到与上述对应的实施例相同的结果。据此,所附的权利要求书的范围应包括在制造工艺、机构、制造、组成、功能、制作方法以及步骤的范围内。
Claims (13)
1.一种集成电路,包含:
蚀刻停止层,形成于基底上;
起始层,形成于该蚀刻停止层上,且该起始层具有高消光系数;
低介电常数的介电层,形成于该起始层的上方;以及
金属线,形成于该低介电常数的介电层之中。
2.如权利要求1所述的集成电路,其中该起始层的消光系数大于或等于0.11,而该起始层的折射率大于或等于1.75。
3.如权利要求1所述的集成电路,其中起始层包括选自硅、氧、碳、氢及其组合的群组的材质。
4.如权利要求1所述的集成电路,其中起始层的厚度介于70纳米至450纳米之间。
5.如权利要求1所述的集成电路,其中该蚀刻停止层包含一压缩应力。
6.如权利要求1所述的集成电路,其中该低介电常数的介电层的介电常数小于2.5。
7.如权利要求1所述的集成电路,其中该蚀刻停止层包括选自碳氮化硅、氧氮化硅、碳化硅、氮化硅、氧碳化硅及其组合的群组的材料。
8.一种集成电路的制作方法,包括:
形成介电层于半导体基底上;
形成蚀刻停止层于该介电层上;
形成起始层于该蚀刻停止层上,且对于紫外线,该起始层具有大于或等于0.11的消光系数;
形成低介电常数的介电层于该起始层上;以及
以该紫外线,固化该低介电常数的介电层。
9.如权利要求8所述的集成电路的制作方法,其中形成该起始层的方式由等离子体加强式化学气相沉积法完成。
10.如权利要求8所述的集成电路的制作方法,其中形成该起始层的工艺条件包括:
介于250℃至350℃之间的晶圆温度;
介于1托至10托之间的反应室压力;以及
介于100瓦至500瓦之间的射频功率。
11.如权利要求8所述的集成电路的制作方法,其中形成该起始层的工艺条件,包括:
提供介于100sccm至500sccm之间的前驱物流量,其中该前驱物包含二甲基二乙氧基硅烷及氧气。
12.如权利要求8所述的集成电路的制作方法,其中该固化步骤的紫外线波长范围介于200纳米至300纳米之间。
13.如权利要求8所述的集成电路的制作方法,其中形成该起始层的步骤,还包括:
决定该紫外线的波长;以及
依据该紫外线的波长,调整形成该起始层的工艺条件,以增加该起始层的消光系数。
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CN103681596A (zh) * | 2012-09-26 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其制作方法 |
CN110534499A (zh) * | 2019-09-29 | 2019-12-03 | 武汉新芯集成电路制造有限公司 | 半导体器件及其制作方法 |
CN115955913A (zh) * | 2023-02-13 | 2023-04-11 | 广州粤芯半导体技术有限公司 | 电容结构及其制备方法、半导体结构 |
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US20120235304A1 (en) * | 2011-03-18 | 2012-09-20 | Globalfoundries Inc. | Ultraviolet (uv)-reflecting film for beol processing |
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US6774432B1 (en) * | 2003-02-05 | 2004-08-10 | Advanced Micro Devices, Inc. | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL |
US20050156208A1 (en) * | 2003-09-30 | 2005-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device having multiple silicide types and a method for its fabrication |
US7193325B2 (en) * | 2004-04-30 | 2007-03-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects |
US7354852B2 (en) * | 2004-12-09 | 2008-04-08 | Asm Japan K.K. | Method of forming interconnection in semiconductor device |
US7732923B2 (en) * | 2004-12-30 | 2010-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Impurity doped UV protection layer |
US7195969B2 (en) * | 2004-12-31 | 2007-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained channel CMOS device with fully silicided gate electrode |
US7335920B2 (en) * | 2005-01-24 | 2008-02-26 | Cree, Inc. | LED with current confinement structure and surface roughening |
US20070013070A1 (en) * | 2005-06-23 | 2007-01-18 | Liang Mong S | Semiconductor devices and methods of manufacture thereof |
US8105908B2 (en) * | 2005-06-23 | 2012-01-31 | Applied Materials, Inc. | Methods for forming a transistor and modulating channel stress |
US20080064173A1 (en) * | 2006-09-08 | 2008-03-13 | United Microelectronics Corp. | Semiconductor device, cmos device and fabricating methods of the same |
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CN103681596A (zh) * | 2012-09-26 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其制作方法 |
CN103681596B (zh) * | 2012-09-26 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其制作方法 |
CN110534499A (zh) * | 2019-09-29 | 2019-12-03 | 武汉新芯集成电路制造有限公司 | 半导体器件及其制作方法 |
CN115955913A (zh) * | 2023-02-13 | 2023-04-11 | 广州粤芯半导体技术有限公司 | 电容结构及其制备方法、半导体结构 |
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