CN101169924A - Display device and driving method thereof - Google Patents

Display device and driving method thereof Download PDF

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Publication number
CN101169924A
CN101169924A CNA2007101671501A CN200710167150A CN101169924A CN 101169924 A CN101169924 A CN 101169924A CN A2007101671501 A CNA2007101671501 A CN A2007101671501A CN 200710167150 A CN200710167150 A CN 200710167150A CN 101169924 A CN101169924 A CN 101169924A
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China
Prior art keywords
signal
voltage
gate
storage
display device
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CNA2007101671501A
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Chinese (zh)
Inventor
李明雨
朴商镇
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to CN201210101486.9A priority Critical patent/CN102622984B/en
Priority to CN201210102004.1A priority patent/CN102622985B/en
Publication of CN101169924A publication Critical patent/CN101169924A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

A liquid crystal display includes: a plurality of gate lines which transmits gate signals having a gate-on voltage and a gate-off voltage; a plurality of data lines which transmits data voltages; a plurality of storage electrode lines which transmits storage signals; a plurality of pixels, wherein each pixel of the plurality of pixels includes a liquid crystal capacitor connected to a switching element and a common voltage, and a storage capacitor connected to the switching element and a storage electrode line of the plurality of storage electrode lines; a gate driver which generates the gate signals; and a plurality of signal generating circuits which generates the storage signals based on at least one control signal and at least one gate signal. The storage signal applied to each pixel has a voltage level which changes after a charging of the data voltage into the liquid crystal capacitor and the storage capacitor.

Description

Display device and driving method thereof
Cross
The application requires the right of priority of korean patent application 10-2007-0041300 number of korean patent application 10-2006-0103375 number that proposed on October 24th, 2006 and proposition on April 27th, 2007, quotes in full hereby, for your guidance.
Technical field
The present invention relates to display device and driving method thereof, relate in particular to display device and driving method thereof that brightness increase and power consumption have reduced.
Background technology
In general, LCD (" LCD ") comprises first display panel that contains pixel electrode and contains second display panel of common electrode and the therebetween liquid crystal layer that contains the anisotropy dielectric material.Pixel electrode is arranged in the approximate matrix pattern and is connected with on-off element as for example thin film transistor (TFT) (" TFT "), so that receive data voltage successively.Common electrode forms on the whole surface of second display panel and can receive utility voltage.Liquid crystal capacitor is formed by each pixel electrode, common electrode and liquid crystal layer therebetween.Liquid crystal capacitor forms pixel cell with the on-off element that is connected with liquid crystal capacitor.
In LCD, voltage is applied on pixel electrode and the common electrode, between them, for example in liquid crystal layer, form electric field.The decision of the intensity of electric field pass liquid crystal layer light transmissivity and be applied to pixel electrode and common electrode on Control of Voltage form required image.When electric field only along a direction (for example polarity) when being applied on the liquid crystal layer, LCD may variation.In order to prevent variation, can be about for example each frame, row or pixel inversion data voltage with respect to the polarity of utility voltage polarity.
But the scope of data voltage that is used to utilize row counter-rotating (for example inverting method of the polarity of capable reversal data voltage according to pixels) display image is less than the scope of the data voltage that is used for utilizing some counter-rotating (for example pressing the inverting method of the polarity of each pixel inversion data voltage) display image.Therefore, if as in perpendicular alignmnet (" VA ") mode LCD, the starting voltage of liquid crystal that is used for driving liquid crystal layer is higher, and the low-voltage that then is used for the data voltage range that image gray-scale displayed voltage represents becomes the same with starting voltage low.Therefore, be difficult to accurately represent brightness.
In addition, the polarity that the small LCD those in being used in mobile phone is for example carried out capable reversal data voltage according to pixels to be reducing the row counter-rotating of power consumption, but because the demanding resolution of small LCD, thereby improved power consumption.
Summary of the invention
Display device according to one exemplary embodiment comprises: many door lines are used to transmit the gate signal with open the door voltage and pass gate voltage; Many data lines are used to transmit data voltage; Many storage electrode lines are used to transmit storage signal; Be arranged in a plurality of pixels of approximate matrix pattern, wherein, each pixel of a plurality of pixels comprise with many door lines in the on-off element that is connected with a data line in many data lines of door line, the liquid crystal capacitor that is connected with utility voltage with on-off element with on-off element and many storage electrode lines in a holding capacitor that storage electrode line is connected; Gate driver is used for along first direction of scanning or second direction of scanning generates gate signal; And a plurality of signal generating circuits, be used for generating storage signal according at least one control signal and at least one gate signal.
Be applied to storage signal at least one pixels of a plurality of pixels and have at the charging data voltage and be charged to the voltage level that changes after liquid crystal capacitor and the holding capacitor, and storage signal becomes from the output order of a plurality of signal generating circuits direction of scanning with gate driver.
When the charging data voltage had positive polarity, storage signal can change over high level from low level, and when the charging data voltage had negative polarity, storage signal can change over low level from high level.
The storage signal that is applied on the given storage electrode line of many storage electrode lines is can every successive frames anti-phase.
Utility voltage can be a fixed voltage.
A plurality of pixels can comprise first pixel of supplying with first gate signal, adjacent with first pixel and be supplied to second pixel of second gate signal and adjacent with first pixel and be supplied to the 3rd pixel of the 3rd gate signal.
A plurality of signal generating circuits can comprise with first storage signal be sent to first signal generating circuit of the storage electrode line of first pixel, second storage signal is sent to second pixel storage electrode line the secondary signal generative circuit and the 3rd storage signal is sent to the 3rd signal generating circuit of the storage electrode line of the 3rd pixel.
In alternative one exemplary embodiment of the present invention, first gate signal or the 3rd gate signal are supplied to the secondary signal generative circuit, maybe second gate signal can be supplied to the secondary signal generative circuit.
At least one control signal can comprise first control signal, second control signal and the 3rd control signal.At least one signal generating circuit of a plurality of signal generating circuits can comprise the signal input unit that receives at least one gate signal and export drive control signal according at least one gate signal, receive first control signal and transmit the storage signal applying unit of first control signal as storage signal according to drive control signal from signal input unit, receive second control signal and the 3rd control signal and change the control module of mode of operation of control module and second control signal and the 3rd control signal that applies according to mode of operation according to drive control signal, keep signal holding unit from the storage signal of storage signal applying unit according to control module.
Signal input unit can further receive each and have first direction signal and second direction signal based on the signal condition of gate driver direction of scanning.First direction signal and second direction signal can have in fact opposite phases.
At least one gate signal can comprise first gate signal and second gate signal, and the mistiming of opening the door between the voltage application time of open the door the voltage application time and second gate signal of first gate signal is about two horizontal cycles (" 2H ").
Signal input unit can be selected one of first gate signal and second gate signal according to first direction signal and second direction signal, and according to selected first gate signal or second gate signal output drive control signal.
Each can keep in fact consistent level first direction signal and second direction signal.
First direction signal and second direction signal can have first level voltage and second level voltage respectively, and first direction signal and second direction signal can be whenever in succession predetermined period between first level voltage and second level voltage alternately.Predetermined period can be an about horizontal cycle (" 1H ").
Being applied to the phase place of the first direction signal on first signal generating circuit of a plurality of signal generating circuits and being applied to the phase place of the second direction signal on the secondary signal generative circuit of a plurality of signal generating circuits adjacent with first signal generating circuit can be in fact opposite.
Signal input unit can comprise and contains the control end that is connected with the first direction signal, the first transistor of input end that is connected with first gate signal and the output terminal that is connected with drive control signal.Signal input unit may further include and contains the control end that is connected with the second direction signal, the transistor seconds of input end that is connected with second gate signal and the output terminal that is connected with drive control signal.
At least one gate signal can comprise first gate signal and second gate signal, and the mistiming of opening the door between the voltage application time of open the door the voltage application time and second gate signal of first gate signal is about four horizontal cycles (" 4H ").
Signal input unit can be selected one of first direction signal and second direction signal according to first gate signal and second gate signal, and according to selected direction signal output drive control signal.
Each level that can be consistent of first direction signal and second direction signal.
Can be further the clock signal with first level voltage and second level voltage different with first level voltage be supplied to signal input unit, and clock signal can be whenever in succession predetermined period between first level voltage and second level voltage alternately.Predetermined period can be about two horizontal cycles (" 2H ").
Be applied to the phase place of the clock signal on first signal generating circuit of a plurality of signal generating circuits and be applied to the phase place of the clock signal on the second adjacent signals generative circuit of a plurality of signal generating circuits in fact opposite.
Signal input unit can be by changing the state of operation signal holding unit based on the drive control signal of first direction signal or second direction signal according to clock signal.
In alternative one exemplary embodiment, signal input unit can comprise: contain the input end that is connected with the first direction signal, the first transistor of control end that is connected with first gate signal and the output terminal that is connected with drive control signal; Contain the input end that is connected with the second direction signal, the transistor seconds of control end that is connected with second gate signal and the output terminal that is connected with drive control signal; And contain and close the input end that gate voltage is connected, the 3rd transistor of control end that is connected with clock signal and the output terminal that is connected with drive control signal.
Be applied to the voltage level of the storage signal on first storage electrode line of many storage electrode lines and be applied to the voltage level of the storage signal on the second adjacent storage electrode line of many storage electrode lines practically identical.In fact every successive frames of making peace is anti-phase in given frame for the voltage level of the voltage level of the voltage level of first control signal, second control signal and the 3rd control signal.
Can with the gateable clock signal with have first level voltage and give signal input unit with second level voltage supplies different with first level voltage, and clock signal can be whenever in succession predetermined period between first level voltage and second level voltage alternately.Predetermined period can be about two horizontal cycles (" 2H ").
Be applied to the phase place of the clock signal on first signal generating circuit of a plurality of signal generating circuits and be applied to the phase place of the clock signal on the second adjacent signals generative circuit of a plurality of signal generating circuits in fact opposite.
In alternative one exemplary embodiment, signal input unit can be by changing the state of operation signal holding unit based on the drive clock signal of at least one gate signal according to clock signal.And signal input unit can comprise the first transistor of the output terminal that contains each control end that all is connected with gate signal and input end and be connected with drive control signal; And the transistor seconds that contains the control end that is connected with clock signal, the input end that is connected with gate signal and the output terminal that is connected with drive control signal.
The storage signal applying unit can comprise and contains the control end that is connected with the output terminal of signal input unit, the first transistor of input end that is connected with first control signal and the output terminal that is connected with storage electrode line.
Control module can comprise transistor seconds that contains control end that is connected with the output terminal of signal input unit and the input end that is connected with second control signal and the 3rd transistor that contains control end that is connected with the output terminal of signal input unit and the input end that is connected with the 3rd control signal.
The signal holding unit can comprise the 4th transistor that contains the control end that is connected with the 3rd transistorized output terminal, input end that is connected with first driving voltage and the output terminal that is connected with storage electrode line and contain the control end that is connected with the output terminal of transistor seconds, the 5th transistor of input end that is connected with second driving voltage and the output terminal that is connected with storage electrode line.The signal holding unit may further include and is connected first capacitor between the 4th transistorized input end and the control end and is connected second capacitor between the 5th transistorized input end and the control end.
The voltage level of the storage signal on the voltage level that is applied to the storage signal on first storage electrode line of many storage electrode lines and the second adjacent storage electrode line that is applied to many storage electrode lines is different.
Each can have first level voltage and second level voltage first control signal, second control signal and the 3rd control signal, and the level separately of first control signal, second control signal and the 3rd control signal can every subsequent cycles replace between first level voltage and second level voltage in given frame.And the level separately of first control signal, second control signal and the 3rd control signal can be anti-phase every a frame.
The display device of one exemplary embodiment may further include at least one extra gate line that gate signal is sent to a signal generating circuit in a plurality of signal generating circuits according to the present invention.
Be sent to the voltage and be sent at least a portion of the voltage predetermined time cycle of opening the door of second gate signal of adjacent second line of many door lines overlapped in time of opening the door of first gate signal of first line of many door lines.
The interval of predetermined period of time can be an about horizontal cycle (" 1H ").
Another one exemplary embodiment of the present invention provides a kind of driving method of LCD.This LCD comprises many door lines, is used to transmit the gate signal with the voltage that opens the door; Many data lines are used to transmit data voltage; Many storage electrode lines are used to transmit storage signal; Door line in a plurality of on-off elements, each on-off element of a plurality of on-off elements and many door lines is connected with a data line in many data lines; A plurality of pixels, each pixel of a plurality of pixels comprise with a plurality of on-off elements in on-off element and many storage electrode lines in a holding capacitor that storage electrode line is connected; Gate driver is used for along first direction of scanning or second direction of scanning generates gate signal; And a plurality of signal generating circuits, be used to generate storage signal.
This driving method comprises first gate signal is applied on first line of many door lines that are connected with first pixel of a plurality of pixels, first data voltage is applied on first data line of many data lines that are connected with first pixel, second gate signal is applied on second line of many door lines that are connected with second pixel of a plurality of pixels, and storage signal is outputed to first pixel according to second gate signal.The output order of storage signal becomes with first direction of scanning or second direction of scanning of gate driver.
The voltage application time of opening the door of first gate signal and the voltage application time of opening the door of second gate signal about two horizontal cycles (" 2H ") of being separated by, or in an alternative one exemplary embodiment, about four horizontal cycles (" 4H ") of being separated by.
In another one exemplary embodiment, provide a kind of driving method of LCD.This LCD comprises many door lines, is used to transmit the gate signal with the voltage that opens the door; Many data lines are used to transmit data voltage; Many storage electrode lines are used to transmit storage signal; Door line in a plurality of on-off elements, each on-off element of a plurality of on-off elements and many door lines is connected with a data line in many data lines; A plurality of pixels, each pixel of a plurality of pixels comprise with a plurality of on-off elements in on-off element and many storage electrode lines in a holding capacitor that storage electrode line is connected; Gate driver is used for along first direction of scanning or second direction of scanning generates gate signal; And a plurality of signal generating circuits, be used to generate storage signal.
This driving method comprises on the door line in the many door lines that gate signal is applied to a pixel in a plurality of pixels is connected, data voltage is applied on the data line in many data lines that are connected with this pixel, and storage signal outputed to this pixel according to gate signal.The output order of storage signal becomes with first direction of scanning or second direction of scanning of gate driver.
Description of drawings
In conjunction with the drawings one exemplary embodiment of the present invention is described in further detail, of the present invention above and others, feature and advantage will become more apparent, in the accompanying drawings:
Fig. 1 is the calcspar of the LCD of an one exemplary embodiment according to the present invention;
Fig. 2 is the equivalent circuit diagram of a pixel of the LCD of the one exemplary embodiment according to the present invention;
Fig. 3 is the schematic circuit of the signal generating circuit of an one exemplary embodiment according to the present invention;
Fig. 4 is the signal timing diagram according to the signal generating circuit of the one exemplary embodiment of the present invention among Fig. 3;
Fig. 5 is the calcspar of the LCD of another one exemplary embodiment according to the present invention;
Fig. 6 is the schematic circuit according to the signal generating circuit of the storage signal generative circuit of the one exemplary embodiment of the present invention among Fig. 5;
Fig. 7 A and Fig. 7 B are the signal timing diagrams according to the signal generating circuit of the one exemplary embodiment of the present invention among Fig. 6;
Fig. 8 A and Fig. 8 B are the signal timing diagrams of the signal generating circuit of an alternative one exemplary embodiment according to the present invention;
Fig. 9 is the calcspar of the LCD of another one exemplary embodiment according to the present invention;
Figure 10 is the schematic circuit according to the signal generating circuit of the one exemplary embodiment of the present invention among Fig. 9;
Figure 11 is the plane figure according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 10;
Figure 12 be illustration one exemplary embodiment according to the present invention be applied on the gate driver the gateable clock signal be applied to the signal timing diagram of the relation of the store clock signal on the storage signal generator;
Figure 13 A and Figure 13 B are the signal timing diagrams according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 10;
Figure 14 is the calcspar of the LCD of another one exemplary embodiment according to the present invention;
Figure 15 is the schematic circuit according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 14;
Figure 16 is the plane figure according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 15;
Figure 17 A is the signal timing diagram according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 15 that utilizes the row counter-rotating; And
Figure 17 B is the signal timing diagram according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 15 that utilizes frame counter-rotating.
The present invention describes in detail
Now, with reference to the accompanying drawing that one exemplary embodiment of the present invention is shown the present invention is described more fully hereinafter.But the present invention can should not be construed and be confined to embodiment given here with many multi-form enforcements.Or rather, it is for the disclosure is become comprehensively thoroughly that these embodiment are provided, and passes on scope of the present invention to those of ordinary skill in the art fully.Identical label is represented components identical from start to finish.
Should be understood that when an element be called as " " another element " on " time, it can be directly on other element or can have insertion element (intervening element) therebetween.In contrast to this, when an element be called as " directly existing " another element " on " time, do not have insertion element.As used herein, term " and/or " comprise one or more relevant any and all combinations of listing.
Can be used to describe various elements, parts, zone, layer and/or part in this article although should be understood that term " first ", " second ", " the 3rd " etc., these elements, parts, zone, layer and/or part are not limited by these terms should.These terms only are used for an element, parts, zone, layer or part and another element, parts, zone, layer or part are distinguished.Therefore, can not depart from the present invention instruct with first element, parts, zone, layer or part called after second element, parts, zone, layer or the part discussed below.
Term used herein is just in order to describe specific embodiment, rather than plans restriction the present invention.As used herein, unless context clearlys show that in addition singulative " ", " a kind of " and " being somebody's turn to do " also have a mind to comprise plural form.It is also to be understood that, term " comprise " or " comprising " where used in this disclosure, regulation exists described feature, zone, integer, step, operation, element and/or parts, does not exist or additional one or more further features, zone, integer, step, operation, element, parts and/or their cohort but do not get rid of.
And, as D score or " end " and " on " or " top " relative terms can be used in this article describing as shown in the figure the relation of an element and other element.Should be understood that relative terms has a mind to comprise the different orientation of equipment except describing orientation (orientation) in the drawings.For example, if the equipment among the figure is turned, so, the element that is described as be at other element D score side become other element " on " side.Therefore, the concrete orientation of view and deciding, the exemplary term D score can comprise D score and " on " orientation.Similarly, if the equipment among the figure is turned, so, be described as " " other element " below " or the element of " below " become " " other element " above ".Therefore, exemplary term " ... following " or " in ... below " can comprise above and following orientation.
Unless otherwise defined, have with those of ordinary skill in the art with in this article all terms (comprising technology and scientific terminology) and understand identical implication usually.It is also to be understood that, term in being defined in common dictionary those should be interpreted as having with they in the consistent implication of the implication under the background of related, unless and clear and definite in this article definition like this, should not idealize or too formally be explained.
Here with reference to section illustration one exemplary embodiment of the present invention is described as the schematic illustration of idealized embodiment of the present invention.Like this, owing to for example reason such as manufacturing technology and/or tolerance limit, expect to have and be different from illustrative shape.Therefore, embodiments of the invention should not be understood as that the given shape that is confined to the illustrative zone of this paper, but comprise that the shape that for example manufacturing causes departs from.For example, illustration or be described as smooth zone and have coarse and/or non-linear characteristics usually.In addition, illustrative wedge angle may be round.Therefore, illustration zone in the drawings is that schematically their shape is not intended to the definite shape in illustration zone, also is not intended to limit the scope of the invention.
Referring now to accompanying drawing the present invention is described in further detail.
Fig. 1 is the calcspar of the LCD of an one exemplary embodiment according to the present invention, and Fig. 2 is the equivalent circuit diagram of the pixel PX of the LCD of an one exemplary embodiment according to the present invention.
As shown in Figure 1, the LCD of an one exemplary embodiment according to the present invention (" LCD ") comprises for example signal controller 600 of liquid crystal panel assembly 300, gate driver 400, data driver 500, the grayscale voltage generator 800 that is connected with data driver 500, storage signal generator 700 and the top element of control, but is not limited to these.
Liquid crystal panel assembly 300 comprises many signal line (G 1-G 2n, G d, D 1-D mAnd S 1-S 2n) and with many signal line (G 1-G 2n, G d, D 1-D mAnd S 1-S2 n) connect and be arranged in a plurality of pixel PX of approximate matrix pattern.
With reference to Fig. 2, liquid crystal panel assembly 300 comprises aspectant lower panel 100 and top panel 200 and the liquid crystal layer 3 between lower panel 100 and top panel 200.
With reference to Fig. 1, many signal line (G 1-G 2n, G d, D 1-D mAnd S 1-S 2n) comprise many door line G 1-G 2nAnd G d, many data line D 1-D mWith many storage electrode line S 1-S 2n
Many door line G 1-G 2nAnd G dMany normal door line G that comprise transmission gate signal (hereinafter being referred to as " sweep signal ") 1-G 2nWith extra gate line G dMany storage electrode line S 1-S 2nWith many normal door line G 1-G 2nConnect and the transmission storage signal.Many data line D 1-D mTransmit data voltage.
Many door line G 1-G 2n, G dWith many storage electrode line S 1-S 2nAlong first approximate (substantially) line direction extend and in fact (substantially) be parallel to each other and many data line D 1-D mAlso in fact be parallel to each other along the second approximate column direction extension vertical with first direction.
Referring again to Fig. 2, each pixel PX is (for example, with i normal door line G i(i=1,2 ..., 2n), i normal storage signal wire S i(i=1,2 ..., 2n) with j data line D j(i=1,2 ..., m) the pixel PX of Lian Jieing) comprise and signal wire G iAnd D jThe on-off element Q that connects and with on-off element Q and storage signal line S iThe liquid crystal capacitor Clc and the holding capacitor Cst that connect.
In an one exemplary embodiment, on-off element Q can be embodied as the three-terminal element (three-terminal element) that for example is installed on the lower panel 100, as thin film transistor (TFT) (" TFT "), but is not limited to this.As shown in Figure 2, three-terminal element contains and normal door line G iThe control end that connects, with data line D jInput end that connects and the output terminal that is connected with holding capacitor Cst with liquid crystal capacitor Clc.
The pixel electrode 191 of lower panel 100 and the common electrode 270 of top panel 200 are respectively first end and second ends of liquid crystal capacitor Clc.Liquid crystal layer 3 between pixel electrode 191 and common electrode 270 plays dielectric material.Pixel electrode 191 is connected with on-off element Q.Common electrode 270 is positioned on the whole top panel 200 and receives utility voltage Vcom (not shown).Alternately, form common electrode 270 below on the plate 100, in this case, at least one of pixel electrode 191 and common electrode 270 can have the shape of approximately linear.
In alternative one exemplary embodiment of the present invention, utility voltage Vcom can comprise direct current (" the DC ") voltage that for example has predetermined value, but is not limited to this.
Holding capacitor Cst assists liquid crystal capacitor Clc, and by form be therebetween insulator, with storage electrode line S iThe pixel electrode 191 that intersects forms.
Show that for colour each pixel PX can represent a kind of primary colors, for example, empty branch (apatialdivision), or alternately, each pixel PX can represent the different primary colors that depend on preset time, for example, the time-division.In any case, required color all passes through primary colors, for example, and red, green and blue space or time and showing.
Fig. 2 shows and utilizes empty one exemplary embodiment of the present invention of dividing.As shown in the figure, each pixel PX with the zone of pixel electrode 191 corresponding top panels 200 on, contain and represent one of three primary colors, for example, one of red, green and blue color filter 230.In alternative one exemplary embodiment of the present invention, color filter 230 is the following or top formation of the pixel electrode 191 of plate 100 below.
The polarizer (not shown) of light polarization is attached on the liquid crystal panel assembly 300.
Refer back to Fig. 1, grayscale voltage generator 800 can generate all grayscale voltages relevant with the required transmissivity of pixel PX or limited grayscale voltage (hereinafter referred to as " reference gray level voltage ").Some (reference) grayscale voltages have positive polarity with respect to utility voltage Vcom, and other (reference) grayscale voltage has negative polarity with respect to utility voltage Vcom.
Gate driver 400 comprises the first gate drive circuit 400a and the second gate drive circuit 400a of the opposite side that for example is positioned at liquid crystal panel assembly 300 as left side and right side, but is not limited to this.
The first gate drive circuit 400a and many door line G 1-G 2nAnd G dOdd number normal door line G 1, G 3..., and G 2n-1With extra gate line G dAn end connect.The second gate drive circuit 400b and many door line G 1-G 2nAnd G dEven number normal door line G 2, G 4..., and G 2nAn end connect.Alternately, the second gate drive circuit 400b can with many door line G 1-G 2nAnd G dOdd number normal door line G 1, G 3..., and G 2n-1With extra gate line G dAn end connect, and the first gate drive circuit 400a can with many door line G 1-G 2nAnd G dEven number normal door line G 2, G 4..., and G 2nAn end connect.
The first gate drive circuit 400a and the second gate drive circuit 400b each utilize the voltage that opens the door (gate-on voltage) Von and pass gate voltage (gate-offvoltage) Voff generation to be applied to many door line G 1-G 2nAnd G dOn gate signal.
In an one exemplary embodiment of the present invention, gate driver 400 and many signal line G 1-G 2n, G d, D 1-D mAnd S 1-S 2nBe integrated into together in the liquid crystal panel assembly 300 with on-off element Q.In alternative one exemplary embodiment, gate driver 400 can comprise and being installed on the liquid crystal panel assembly 300, or is installed at least one integrated circuit (" the IC ") chip on flexible print circuit (" the FPC ") film in the thin-film package (" TCP ") that is attached on the liquid crystal panel assembly 300.Alternately, gate driver 400 can be installed on the discrete printed circuit board (PCB) (not shown).
For example, storage signal generator 700 comprises the opposite side that is arranged in liquid crystal panel assembly 300 and first storage signal generative circuit 700a and the second storage signal generative circuit 700b adjacent with the second gate drive circuit 400b with the first gate drive circuit 400a, but is not limited to this.
The first storage signal generative circuit 700a and odd number storage electrode line S 1, S 3..., S 2n-1With even number normal door line G 2, G 4..., G 2nConnect, and a plurality of storage signals that will have high level voltage and a low level voltage are applied to storage electrode line S 1, S 3..., S 2n-1On.
The second storage signal generative circuit 700b and even number storage electrode line S 2, S 4..., S and remove the 1st normal door line G 1Outside odd number normal door line G 3, G 5..., G 2n-1With extra gate line G dConnect, and a plurality of storage signals that will have high level voltage and a low level voltage are applied to storage electrode line S 2, S 4..., S 2nOn.
In an alternative one exemplary embodiment of the present invention, can be not with from the extra gate line G that is connected with gate driver 400 dSignal provision give storage signal generator 700.Or rather, can will for example give storage signal generator 700, but be not limited to this from the signal provision of the such separate unit of image signal controller 600 or discrete signals generator (not shown).In this case, as mentioned above, on liquid crystal panel assembly 300, can not form extra gate line G d
In an one exemplary embodiment of the present invention, storage signal generator 700 and many signal line G 1-G 2n, G d, D 1-D mAnd S 1-S 2nBe integrated into together in the liquid crystal panel assembly 300 with on-off element Q.In alternative one exemplary embodiment, storage signal generator 700 can comprise and being installed on the liquid crystal panel assembly 300, or is installed at least one the IC chip on the FPC film among the TCP that is attached on the liquid crystal panel assembly 300.Alternately, storage signal generator 700 can be installed on the discrete printed circuit board (PCB) (not shown).
Many data line D of data driver 500 and panel assembly 300 1-D mConnect, the data voltage that will select from the grayscale voltage of grayscale voltage generator 800 supplies is applied to many data line D 1-D mOn.But, when 800 of grayscale voltage generators generate some rather than all during grayscale voltage, data driver 500 can be divided reference gray level voltage, so that generate data voltage from grayscale voltage.
Signal controller 600 control gate drivers 400, data driver 500 and storage signal generator 700.
In an one exemplary embodiment, data driver 500, signal controller 600 and grayscale voltage generator 800 can comprise and be installed on the liquid crystal panel assembly 300 or be installed at least one IC chip on the FPC film among the TCP that is attached on the liquid crystal panel assembly 300.Alternately, at least one of data driver 500, signal controller 600 and grayscale voltage generator 800 can with many signal line G 1-G 2n, G d, D 1-D mAnd S 1-S 2nBe integrated into together in the liquid crystal panel assembly 300 with on-off element Q.In another alternative one exemplary embodiment, each of data driver 500, signal controller 600 and grayscale voltage generator 800 can be integrated in the single IC chip, but at least one of data driver 500, signal controller 600 and grayscale voltage generator 800, or at least one circuit component at least one of data driver 500, signal controller 600 and grayscale voltage generator 800 can be positioned at the outside of single IC chip.
Still with reference to Fig. 1 and 2, operation of LCD is described in further detail now.
Signal controller 600 receives received image signal R, G and B and from control received image signal R, the G of external graphics controller (not shown) and a plurality of input control signals of B.Received image signal R, G and B comprise the monochrome information of pixel PX and the gray-scale value that brightness has predetermined number, for example, and 1024 (=2 10), 256 (=2 8) or 64 (=2 6) individual gray-scale value, but be not limited to these.
For example, a plurality of input control signals comprise vertical synchronizing signal Vsync, horizontal-drive signal Hsync, master clock signal MCLK and data enable signal DE, but are not limited to these.
Signal controller 600 is according to input control signal (not shown) and received image signal R, G and B processing received image signal R, G and B, and, operating conditions according to liquid crystal panel assembly 300, generate gate control signal CONT1, data controlling signal CONT2 and storage control signal CONT3, gate control signal CONT1 is applied on the gate driver 400, data controlling signal CONT2 and data image signal DAT are applied on the data driver 500, and storage control signal CONT3 is applied on the storage signal generator 700.
Gate control signal CONT1 comprises open the door at least one clock signal (not shown) in output cycle of voltage Von of the first scanning commencing signal STV1 (not shown) of beginning of the voltage Von that determines to open the door and the second scanning commencing signal STV2 (not shown) and control.In an one exemplary embodiment, the first scanning commencing signal STV1 is applied on the first gate drive circuit 400a, and the second scanning commencing signal STV2 is applied on the second gate drive circuit 400b.In alternative one exemplary embodiment of the present invention, the first scanning commencing signal STV1 can be applied on the second gate drive circuit 400b, and the second scanning commencing signal STV2 is applied on the first gate drive circuit 400a.
Gate control signal CONT1 may further include the output enable signal OE (not shown) of the time cycle of limiting the voltage Von that opens the door.
Data controlling signal CONT2 comprise the beginning that data of each row of determining pixel PX transmit horizontal synchronization commencing signal STH (not shown), data voltage is applied to many data line D 1-D mOn Load Signal LOAD (not shown) and data clock signal HCLK (not shown).Data controlling signal CONT2 may further include the reverse signal RVS (not shown) of reversal data voltage with respect to the polarity of utility voltage Vcom.
Response is from the data controlling signal CONT2 of signal controller 600, data driver 500 receives the data image signal DAT of each row of pixel PX from signal controller 600, convert data image signal DAT to from grayscale voltage, select module data voltage, and module data voltage is applied to many data line D 1-D mOn.
Gate driver 400 response is from the gate control signal CONT1 of signal controller 600, and the voltage Von that opens the door is applied to the current line of a line, for example, on the capable corresponding normal door line of i, thus the related switch element Q that the capable line of normal door separately of conducting and i is connected.Therefore, analog data voltage is applied to data line D 1-D mOn, be supplied to capable each pixel PX of i by actuating switch transistor Q then, so that liquid crystal capacitor Clc among the capable pixel PX of i and holding capacitor Cst are charged by analog data voltage.
In an exemplary embodiment, extra gate line G dBe not connected with on-off element Q.
The difference that is applied to analog data voltage on each pixel PX and utility voltage Vcom appears as the voltage difference at the liquid crystal capacitor Clc two ends of pixel PX, is called pixel voltage.Liquid crystal molecule is orientated with the amplitude of pixel voltage among the liquid crystal capacitor Clc, the polarity that the light of liquid crystal layer 3 is passed in the orientation decision of liquid crystal molecule.The polarizer (not shown) converts the light polarization to light transmission, so that given pixel PX has and the analog data voltage that is applied on the pixel PX, for example, the brightness that the level of pixel voltage is directly proportional.
At the horizontal cycle (" 1H ") of the one-period that equals horizontal-drive signal Hsync and data enable signal DE afterwards, data driver 500 is applied to (i+1) OK with data voltage, for example, subsequently on the pixel PX of Hanging, to be applied to i capable and enabling signal Von is applied on (i+1) row of pixel and gate driver 400 will close gate signal Voff.Consequently, the on-off element Q that i is capable turn-offs, and the capable pixel electrode of i 191 is floated.
Storage signal generator 700 is according to storage control signal CONT3 and be applied to (i+1) door line G I+1On the change in voltage of gate signal, change and be applied to i storage electrode line S iOn the voltage level of storage signal.Therefore, the storage electrode line S that is connected with the other end of the voltage of the pixel electrode 191 that is connected with the end of holding capacitor Cst with holding capacitor Cst iChange in voltage and become.
By to all subsequently pixel column repeat aforesaid process, LCD will demonstrate the image of single frames.When the frame when subsequently began, control was applied to the reverse signal RVS (not shown) on the data driver 500, so that the polarity of counter-rotating analog data voltage.In other words, the polarity of the data voltage of given frame is identical, but with respect to the reversal of poles of the data voltage of former frame, claim that this is " frame counter-rotating ".
In addition, the polarity that is applied to the data voltage on the pixel PX of delegation may be similar to identical, and the polarity of adjacent lines and the data voltage on the pixel PX of back adjacent lines is (for example, the row counter-rotating) of counter-rotating before being applied to.
In the one exemplary embodiment of the present invention of conducting frame counter-rotating and/or row counter-rotating, the polarity that is applied to all data voltages on the pixel PX of delegation is positive and negative alternately with each consecutive line.And, when the data voltage by positive polarity charges to pixel electrode 191, be applied to many storage electrode line S 1-S 2nOn storage signal change over high level voltage from low level voltage.On the contrary, when the data voltage by negative polarity charged to pixel electrode 191, storage signal changed over low level voltage from high level voltage.Consequently, if by the positive data voltage of positive polarity pixel electrode 191 is charged, then the voltage of pixel electrode 191 raises, and if pixel electrode 191 is charged the then voltage of pixel electrode 191 decline by negative data voltage.Consequently, the scope of the voltage level of pixel electrode 191 has increased, thereby greater than the scope as the grayscale voltage on data voltage basis.Consequently, the scope that need not increase grayscale voltage just can increase brightness range.
The first storage signal generative circuit 700a and the second storage signal generative circuit 700b comprise and many storage electrode line S 1-S 2nThe a plurality of signal generating circuits 710 (Fig. 3) that connect.The example of signal generating circuit 710 is described in further detail referring now to Fig. 3 and 4.
Fig. 3 is the schematic circuit of the signal generating circuit of an one exemplary embodiment according to the present invention, and Fig. 4 is the signal timing diagram according to the signal generating circuit of the one exemplary embodiment of the present invention among Fig. 3.
With reference to Fig. 3, signal generating circuit 710 comprises input end IP and output terminal OP.In i signal generating circuit 710, for example, input end IP and supply (i+1) gate signal g I+1(i+1) door line G of (hereinafter referred to as " input signal ") I+1Connect (Fig. 1), and output terminal OP and output i storage signal V S1I storage electrode line S iConnect.Similarly, in (i+1) signal generating circuit 710, for example, input end IP and supply (i+2) gate signal g I+2(not shown) is as (i+2) door line G of input signal I+2Connect, and output terminal OP and output (i+1) storage signal V Sl+1(i+1) storage electrode line S of (not shown) I+1Connect.
To be supplied to signal generating circuit 710 from the first clock signal C K1, second clock signal CK1B and the 3rd clock signal C K2 of the storage control signal CONT3 of signal controller 600 (Fig. 1), and will be supplied to signal generating circuit 710 from the high pressure AVDD and the low pressure AVSS of signal controller 600 or external unit (not shown).
As shown in Figure 4, the cycle of the first clock signal C K1, second clock signal CK1B and the 3rd clock signal C K2 can be about 2H, and their dutycycle can be about 50%, but be not limited to this.The first clock signal C K1 and second clock signal CK1B have about 180 0Differ and anti-phase mutually.On the contrary, second clock signal CK1B and the 3rd clock signal C K2 have practically identical phase place.In addition, as shown in Figure 4, at each each subsequently in the frame each phase place of the first clock signal C K1, second clock signal CK1B and the 3rd clock signal C K2 be anti-phase.
The first clock signal C K1 and second clock signal CK1B for example can have the approximately first high level voltage Vh1 of 15V and for example first low level voltage Vl1 of about 0V.The 3rd clock signal C K2 for example can have the approximately second high level voltage Vh2 of 5V and for example second low level voltage Vl2 of about 0V.High pressure AVDD can be for example about 5V, and can approximate the second high level voltage Vh2 of the 3rd clock signal C K2 greatly.Low pressure AVSS can be for example about 0V, and can approximate the second low level voltage Vl2 of the 3rd clock signal C K2 greatly.
Signal generating circuit 710 comprises first to the 5th transistor Tr 1-Tr5 and the first capacitor C1 and the second capacitor C2 that contains control end, input end and output terminal respectively.
The control end of the first transistor Tr1 is connected with input end IP, and the input end of transistor Tr 1 is connected with the 3rd clock signal C K2, and the output terminal of transistor Tr 1 is connected with output terminal OP.
Each all is connected the control end of transistor seconds Tr2 and the 3rd transistor Tr 3 with input end IP, and the input end of transistor seconds Tr2 and the 3rd transistor Tr 3 is connected with second clock signal CK1B with the first clock signal C K1 respectively.
The control end of the 4th transistor Tr 4 and the 5th transistor Tr 5 is connected with the output terminal of the 3rd transistor Tr 3 with transistor seconds Tr2 respectively, and the input end of the 4th transistor Tr 4 and the 5th transistor Tr 5 is connected with high pressure AVDD with low pressure AVSS respectively.
The first capacitor C1 and the second capacitor C2 are connected between the control end and low pressure AVSS and high pressure AVDD of the 4th transistor Tr 4 and the 5th transistor Tr 5.
In an one exemplary embodiment, first to the 5th transistor Tr 1-Tr5 is formed by amorphous silicon (" a-Si ") or polysilicon (" p-Si ") TFT respectively.
The operation of signal generating circuit 710 is described in further detail now.
Referring again to Fig. 4, in general, the voltage Von that opens the door for example approximately is being applied on each bar of two adjacent door lines in predetermined cycle overlapping time of 1H (but being not limited to this).Consequently, in about 1H, utilize the data voltage on the pixel that is applied to previous row, in all the other 1H, utilize data voltage that all pixel PX of given row are charged with display image then.
Now, further describe i signal generating circuit 710 with reference to Fig. 3 and 4.
When input signal (for example, is applied to (i+1) door line G I+1On gate signal g I+1) change over when opening the door voltage Von first, second and the 3rd transistor Tr 1-Tr3 conducting respectively.The first transistor Tr1 of conducting is sent to output terminal OP with the 3rd clock signal C K2.Consequently, i storage signal V SiBe on the second low level voltage Vl2 of the 3rd clock signal C K2.The transistor seconds Tr2 of conducting is sent to the control end of the 4th transistor Tr 4 with the first clock signal C K1, and the 3rd transistor Tr 3 of conducting is sent to second clock signal CK1B the control end of the 5th transistor Tr 5.
Because there are anti-phase relation in the first and second clock signal C K1 and CK1B, the 4th transistor Tr 4 and the 5th transistor Tr 5 were reverse biased in preset time.For example, when 4 conductings of the 4th transistor Tr, the 5th transistor Tr 5 is turn-offed, on the contrary, when the 4th transistor Tr 4 is turn-offed, 5 conductings of the 5th transistor Tr.And when 4 conductings of the 4th transistor Tr and 5 shutoffs of the 5th transistor Tr, low pressure AVSS is sent to output terminal OP, and when 4 shutoffs of the 4th transistor Tr and 5 conductings of the 5th transistor Tr, high pressure AVDD is sent to output terminal OP.
As shown in Figure 4, gate signal g I+1For example approximately be on the voltage Von that opens the door in the interval of 2H.And approximately the period 1 of 1H is represented with period 1 T1, and represent with period T 2 subsequently the second round of about 1H.
The first clock signal C K1 is in period 1 T1 on the first high level voltage Vh1, and second clock signal and the 3rd clock signal C K1B and CK2 are in respectively on the first and second low level voltage Vl1 and the vl2, and low pressure AVSS is supplied to the output terminal OP that passes to the second low level voltage Vl2 of the 3rd clock signal C K2 by transistor Tr 1.Consequently, storage signal V SiThe maintenance amplitude equals the low level storage signal voltage V-of the amplitude of the second low level voltage Vl2 and low pressure AVSS.During period 1 T1, the first high level voltage Vh1 of the first clock signal C K1 and the voltage difference between the low pressure AVSS are charged to capacitor C1, and the first low level voltage Vl1 of second clock signal CK1B and the voltage difference between the high pressure AVDD are charged to capacitor C2.
During period T 2, the first clock signal C K1 remains on the first low level voltage Vl1, and the second and the 3rd clock signal C K1B and CK2 remain on respectively on the first and second high level voltage Vh1 and the Vh2, thus the 5th transistor Tr 5 conductings and the 4th transistor Tr 4 is turn-offed.
Consequently, the second high level voltage Vh2 of the 3rd clock signal C K2 that will transmit by the first transistor Tr1 of conducting is supplied to output terminal OP, and storage signal V SiState change over the high level storage signal voltage V+ that amplitude equals the amplitude of the second high level voltage Vh2 from low level storage signal voltage V-.In addition, amplitude is equaled the amplitude of high level storage signal voltage V+, the high pressure AVDD that applies by conducting the 5th transistor Tr 5 is supplied to output terminal OP.
Because it is approximate identical with the voltage difference between the low pressure AVSS with the first low level voltage Vl1 of the first clock signal C K1 to be charged to the voltage of capacitor C1, when the first low level voltage Vl1 of the first clock signal C K1 and low pressure AVSS become when approximate identical capacitor C1 discharge.Owing to be charged to the voltage of capacitor C2 based on the first high level voltage Vh1 of second clock signal CK1B and the voltage difference between the high pressure AVDD, when as mentioned above, the first high level voltage Vh1 and high pressure AVDD are mutually not simultaneously, the voltage that is charged to capacitor C2 is not equal to 0V, wherein, the first high level voltage Vh1 of second clock signal CK1B is that about 15V and high pressure AVDD are about 5V.Therefore, the voltage that is charged to capacitor C2 is about 10V.
When as shown in Figure 4, gate signal g I+1The i+1 level after having passed through period T 2, change over when closing gate voltage Voff from the voltage Von that opens the door, first to the 3rd transistor Tr 1-Tr3 turn-offs respectively.Consequently, being electrically connected between the first transistor Tr1 and the output terminal OP separates, and being electrically connected also between the control end of the 4th and the 5th transistor Tr 4 and Tr5 and the output terminal OP separated respectively.
Because uncharged to capacitor C1, the 4th transistor Tr 4 remains on off state.But the first high level voltage Vh1 of second clock signal CK1B and the voltage between the high pressure AVDD have been charged to capacitor C2.Therefore, when the charging voltage of capacitor C2 during greater than the starting voltage of the 5th transistor Tr 5, transistor Tr 5 remains on conducting state.Consequently, with high pressure AVDD as storage signal V SiOffer output terminal OP.So, storage signal V SiKeep high level storage signal voltage V+.
The operation of (i+1) signal generating circuit 710 then, is described in further detail with reference to Fig. 4.
As (i+2) gate signal g with the voltage Von that opens the door I+2When being applied on (i+1) signal generating circuit 710 (not shown), (i+1) signal generating circuit 710 is started working.
As shown in Figure 4, as (i+2) gate signal g I+2Switch to when opening the door voltage Von, first, second state with the 3rd clock signal C K1, CK1B and CK2 reverses respectively, and (i+1) gate signal g I-1Be on the voltage Von that opens the door.
(i+2) gate signal g I+2The operation of the previous voltage cycle T1 that opens the door approximate with (i+1) gate signal g I+1The operation of the back voltage cycle T2 that opens the door identical, cause the first, the 3rd and the 5th transistor Tr 1, Tr3 and Tr5 conducting respectively.So the second high level voltage Vh2 and the high pressure AVDD of the 3rd clock signal C K2 are applied on the output terminal OP.Consequently, storage signal V Si+1Be on the high level storage signal voltage V+.
Similarly, (i+2) gate signal g I+2The operation of the voltage cycle T2 that opens the door approximate with (i+1) gate signal g I+1The operation of the previous voltage cycle T1 that opens the door identical, cause first, second and the 4th transistor Tr 1, Tr2 and Tr4 conducting respectively.So the second low level voltage Vl2 and the low pressure AVSS of the 3rd clock signal C K2 are applied on the output terminal OP.Consequently, storage signal V Si+1Change over low level storage signal voltage V-from high level storage signal voltage V+.
As mentioned above, the first transistor Tr1 can apply the 3rd clock signal C K2 as storage signal when input signal keeps opening the door voltage Von, and, utilize the first and second capacitor C1 and C2 to make second to the 5th transistor Tr 2-Tr5 remain on the state of storage signal respectively up to next frame when by closing gate voltage Voff when the output terminal of output terminal OP and the first transistor Tr1 is separated.And the first transistor Tr1 can be applied to storage signal on the respective stored electrode wires, and second to the 5th transistor Tr 2-Tr5 keeps storage signal respectively.
In an one exemplary embodiment, the size of the first transistor Tr1 is more much bigger than the size of second to the 5th transistor Tr 2-Tr5 respectively.As equation 1 provides, pixel electrode voltage Vp response storage signal V sChange in voltage and become.
Vp=V DThe A=V of+/- DThe C of+/- St/ (C St+ C Lc) * [(V+)-(V-)] (equation 1) wherein: V DIt is data voltage; Δ is a voltage variety; C LcAnd C StRepresent the electric capacity of storage and liquid crystal capacitor respectively; V+ represents storage signal V sHigh level storage signal voltage; And V-represents storage signal V sLow level storage signal voltage.
By with storage signal V sThe voltage variety Δ add data voltage V DIn or from data voltage V DIn deduct storage signal V sThe voltage variety Δ, when the data voltage that utilizes positive polarity charged to pixel, pixel electrode voltage Vp had increased the voltage variety Δ, on the contrary, when the data voltage that utilizes negative polarity charged to pixel, pixel electrode voltage Vp had reduced the voltage variety Δ.Consequently, the voltage variety Δ of pixel voltage is by making pixel electrode voltage Vp and increase or reducing, and makes pixel voltage become scope greater than grayscale voltage, causes the scope of representative brightness also to increase.
And as mentioned above, because utility voltage is fixed on the predetermined value, the LCD of the prior art that replaces between high value and low value with utility voltage compares, and has reduced power consumption effectively.
Therefore, according to one exemplary embodiment of the present invention, utility voltage is fixed on the predetermined value and the periodically variable storage signal of level is applied on the storage electrode line, causes the scope of pixel electrode voltage to increase.Therefore, represent the scope of the voltage of grayscale voltage to increase, thereby the picture quality of LCD is improved.
And, as mentioned above, reduced power consumption owing to utility voltage is constant.
Hereinafter, further describe another one exemplary embodiment of the present invention with reference to Fig. 5-8B.
Fig. 5 is the calcspar of the LCD of another one exemplary embodiment according to the present invention, and Fig. 6 is the schematic circuit according to the signal generating circuit of the storage signal generative circuit of the one exemplary embodiment of the present invention among Fig. 5.Fig. 7 A and 7B are the signal timing diagrams according to the signal generating circuit of the one exemplary embodiment of the present invention among Fig. 6.More particularly, Fig. 7 A is that the direction of scanning of gate driver is the example under the situation of forward direction, and Fig. 7 B be the direction of scanning of gate driver is the example of back under the situation of direction.Fig. 8 A and 8B are the signal timing diagrams of the signal generating circuit of an alternative one exemplary embodiment according to the present invention.More particularly, figure BA is that the direction of scanning of illustration gate driver is the example of the signal sequence under the situation of forward direction, and Fig. 8 B be the direction of scanning of illustration gate driver is the example of the signal sequence of back under the situation of direction.
Except the different piece that describes in further detail below, according to identical to the LCD of the one exemplary embodiment of the present invention shown in 8B LCD approximate and shown in Fig. 1 to 3 as Fig. 5.Therefore, carry out the element of same or similar operation, and below will omit any of them is repeated in this description with identical labelled notation.
LCD according to as shown in Figure 5 one exemplary embodiment of the present invention comprises liquid crystal panel assembly 300a, gate driver 401, data driver 500, the grayscale voltage generator 800 that is connected with data driver 500, storage signal generator 701 and signal controller 601.
But different with as shown in Figure 1 one exemplary embodiment of the present invention, gate driver 401 is many normal door line G 1-G 2nThe bidirectional gate driver that becomes with selection signal (not shown) of direction of scanning from the external unit (not shown).More particularly, according to the state of selecting signal, gate driver 401 is along for example from the 1st normal door line G 1Normal door line G to the end 2nForward direction, or opposite, along for example from last normal door line G 2nTo the 1st normal door line G 1Back to direction, transmit the voltage Von that opens the door successively.In the bi-directional drive of gate driver 401, LCD may further include the selector switch (not shown), selector switch output has the State Selection signal that for example becomes with the user's selection that is input to signal controller 601, and, except as described above in greater detail such, be applied to respectively outside scanning commencing signal STV1 of first and second on the first and second gate drive circuit 401a and the 401b and the STV2 (not shown), signal controller 601 can also be at gate control signal CONT1a, and output additional third and fourth scans commencing signal STV3 and STV4 (not shown) respectively.Therefore, when gate driver 410 when forward direction scans, the first and second scanning commencing signal STV1 and STV2 can be applied to respectively on the first and second gate drive circuit 401a and the 401b, and when gate driver 410 along the back during to scanning direction, the third and fourth scanning commencing signal STV3 and STV4 can be applied to respectively on the first and second gate drive circuit 401a and the 401b.
Comprise according to each of the first and second storage signal generative circuit 701a of the storage signal generator 701 of the LCD of one exemplary embodiment and 701b storage signal is sent to many storage electrode line S 1-S 2nA plurality of signal generating circuit 710a.As shown in Figure 6, each signal generating circuit 710a of a plurality of signal generating circuit 710a is similar with signal generating circuit 710 as shown in Figure 3, for example, signal generating circuit 710a comprises output terminal OP, first to the 5th transistor Tr 1-Tr5 and the first capacitor C1 and the second capacitor C2.
But the signal generating circuit 710a of the one exemplary embodiment among Fig. 6 further comprises first input end IP11 and the second input end IP12 and first direction control end IP13 and second direction control end IP14.In i signal generating circuit 710a, first input end IP11 and supply (i+1) gate signal g I+1(i+1) door line G of (hereinafter referred to as " first input signal ") I+1Connect and the second input end IP12 and supply (i-1) gate signal g I-1(i-1) door line G of (hereinafter referred to as " second input signal ") I-1Connect.Similarly, in (i+1) signal generating circuit 710a, first input end IP11 and supply (i+2) gate signal g I+2(i+2) door line G as first input signal I+2Connect and the second input end IP12 and supply i gate signal g iI door line G as second input signal iConnect.
The same with signal generating circuit 710 as shown in Figure 3, to be supplied to signal generating circuit 710a respectively from first, second and the 3rd clock signal C K1, CK1B and the CK2 of the storage control signal CONT3a of signal controller 601, and will be supplied to signal generating circuit 710a from the high pressure AVDD and the low pressure AVSS of signal controller 601 or external unit (not shown).Respectively by first direction control end IP13 and second direction control end IP14, further will be supplied to signal generating circuit 710a from the first direction signal DIR of the storage control signal CONT3a of signal controller 601 or DIRa and second direction signal DIRB or DIRBa.
Signal generating circuit 710a further comprises the 6th transistor Tr 6 and the 7th transistor Tr 7 that each all contains control end, input end and output terminal.
As shown in Figure 6, the control end of the 6th transistor Tr 6 is connected with first direction control end IP13, the input end of the 6th transistor Tr 6 is connected with first input end IP11, is connected with the control end of first to the 3rd transistor Tr 1-Tr3 respectively with the output terminal of the 6th transistor Tr 6.
And the control end of the 7th transistor Tr 7 is connected with second direction control end IP14, and the input end of the 7th transistor Tr 7 is connected with the second input end IP12, is connected with the control end of first to the 3rd transistor Tr 1-Tr3 respectively with the output terminal of the 7th transistor Tr 7.
Except extra gate line G dOutside, LCD further comprises the second extra gate line G DaThe second extra gate line G DaBe connected with the end of the second gate drive circuit 401b, so that transmitting gate signal g 1The voltage Von that will open the door afterwards is sent to the first storage signal generative circuit 701a.
In an one exemplary embodiment, extra gate line G DaWith extra gate line G dDifferent on-off element Q connect.
The example of operation of signal generating circuit describes in further detail with reference to Fig. 7 A and 7B.
Shown in Fig. 7 A and 7B, being applied to the first and second direction signal DIR on the first and second direction control end IP13 and the IP14 and DIRB respectively keeps the 3rd high level voltage Vh3 or the 3rd low level voltage Vl3 and the first and second direction signal DIR and DIRB to have phases opposite respectively in a frame respectively.More particularly, when first direction signal DIR has the 3rd high level voltage Vh3, second direction signal DIRB has the 3rd low level voltage Vl3 and when first direction signal DIR had the 3rd low level voltage Vl3, second direction signal DIRB had the 3rd high level voltage Vh3.And the 3rd high level voltage Vh3 of the first and second direction signal DIR and DIRB has the amplitude of conducting the 6th and the 7th transistor Tr 6 and Tr7 respectively, and the amplitude of the 3rd high level voltage Vh3 can be for example about 15V, but is not limited to this.The 3rd low level voltage Vl3 of the first and second direction signal DIR and DIRB has the amplitude of turn-offing the 6th and the 7th transistor Tr 6 and Tr7, the amplitude of the 3rd low level voltage Vl3 can be for example approximately-10V, but be not limited to this.
Therefore, the the 6th and the 7th transistor Tr 6 and Tr7 have reciprocal biasing respectively in preset time, thereby when the 6th transistor Tr 6 is in conducting state, the 7th transistor Tr 7 is in off state, and when the 6th transistor Tr 6 was in off state, the 7th transistor Tr 7 was in conducting state.
In alternative one exemplary embodiment of the present invention, for example, can maybe can utilize the control signal of the direction of scanning of control gate driver 40 to export first and second direction signal DIR and the DIRB, but be not limited to this according to selecting signal.
The situation that present direction of scanning at gate driver 401 is a forward direction describes in further detail the operation of signal generating circuit 710a.
With reference to Fig. 6 and 7A, first direction signal DIR is among the last input of the 3rd high level voltage Vh3 first direction control end IP13 and second direction signal DIRB is among the last input of the 3rd low level voltage Vl3 second direction control end IP14.
Therefore, 6 conductings of the 6th transistor Tr and the 7th transistor Tr 7 are turn-offed, thus according to first input signal that is applied on the first input end IP11, for example, gate signal g I+1Operation signal generative circuit 710a.More particularly, when operation signal generative circuit 710a as i signal generating circuit 710a, by being applied to (i+1) door line G I+1Gate signal g (Fig. 1) I+1The voltage Von that opens the door operate i signal generating circuit 710a.Therefore, with reference to as described in Fig. 3 and 4, has the storage signal V of predetermined level as top by the operation output of first to the 5th transistor Tr 1-Tr5 and the first and second capacitor C1 and C2 Si
Similarly, when the direction of scanning of gate driver 401 is backs during to direction, shown in Fig. 7 B, first direction signal DIR is on the 3rd low level voltage Vl3 and second direction signal DIRB presents the 3rd high level voltage Vh3.
Therefore, the 6th transistor Tr 6 is turn-offed and 7 conductings of the 7th transistor Tr, thus by being applied to second input signal on the second input end IP12, for example, gate signal g I-1Operation signal generative circuit 710a.More particularly, when operation signal generative circuit 710a as i-1 signal generating circuit 710a, by being applied to (i-1) door line G I-1Gate signal g (Fig. 1) I-1The voltage Von that opens the door operate i signal generating circuit 710a.Therefore, with reference to as described in Fig. 3 and 4, has the storage signal V of predetermined level as top by the operation output of first to the 5th transistor Tr 1-Tr5 and the first and second capacitor C1 and C2 Si
Replacement directly is supplied to input signal signal generating circuit 710 (Fig. 3) conducting first to the 3rd transistor Tr 1-Tr3 respectively by input end IP, as shown in the figure, when the direction of scanning is forward direction, by the 6th transistor T 6 gate signal is supplied to signal generating circuit 710a, as the input signal on the control end that is applied to first to the 3rd transistor Tr 1-Tr3 respectively, and when the direction of scanning be that the back is during to direction, by the 7th transistor T 7 gate signal is supplied to signal generating circuit 710a, as the input signal on the control end that is applied to first to the 3rd transistor Tr 1-Tr3 respectively.The operation of first to the 5th transistor Tr 1-Tr5 and the first and second capacitor C1 and C2 is identical with those of the top signal generating circuit 710 that describes in further detail with reference to Fig. 3 respectively.
The operation of the signal generating circuit 710a of the alternative one exemplary embodiment according to the present invention is described in further detail referring now to Fig. 8 A and 8B.
Shown in Fig. 8 A and 8B, first direction signal DIRa and second direction signal DIRBa are applied to respectively on the first and second direction control end IP13 and the IP14, and have the 3rd high level voltage Vh3 and the 3rd low level voltage Vl3 respectively.And each is approximately remaining unchanged the 3rd high level voltage Vh3 and the 3rd low level voltage Vl3 in the 1H, and their dutycycle can be about 50%.More particularly, the every approximately 1H of first direction signal DIRa and second direction signal DIRBa replaces between the 3rd high level voltage Vh3 and the 3rd low level voltage Vl3.And first direction signal DIRa and second direction signal DIRBa have about 180 ° differing with anti-phase mutually.
As mentioned above, the 3rd high level voltage Vh3 of first direction signal DIRa and second direction signal DIRBa can be for example approximately 15V and their the 3rd low level voltage Vl3 can be for example approximately-10V.
For every row, respectively first direction signal DIRa and second direction signal DIRBa alternate supplies are given first direction control end IP13 and the second direction control end IP14 of signal generating circuit 710a.More particularly, with odd number storage electrode line S 1, S 3..., S 2n-1Among the signal generating circuit 710a that connects, first direction signal DIRa is supplied to first direction control end IP13, and second direction signal DIRBa is supplied to second direction control end IP14.On the contrary, with even number storage electrode line S 2, S 4..., S 2nAmong the signal generating circuit 710a that connects, second direction signal DIRBa is supplied to first direction control end IP13, and first direction signal DIRa is supplied to second direction control end IP14.
Now the direction of scanning at gate driver 401 is the situation of forward direction, and the operation of signal generating circuit 710a is described in further detail with reference to Fig. 6 and 8B.
At odd number signal generating circuit 710a, for example, among the i signal generating circuit 710a, when will be as (i+1) gate signal g of first input signal I+1The voltage Von that opens the door be supplied to first input end IP11, and will be as (i-1) gate signal g of second input signal I-1Pass gate voltage Voff when being supplied to the second input end IP12, give first direction control end IP13 with first direction signal DIRa as the first direction signal provision, and give second direction control end IP14 as the second direction signal provision second direction signal DIRBa.
At gate signal g I+1The period 1 T1 of the voltage Von that opens the door in, first direction signal DIRa is in that the 3rd low level voltage Vl3 goes up and second direction signal DIRBa is on the 3rd high level voltage Vh3, thus 6 shutoffs of the 6th transistor Tr, and the 7th transistor Tr 7 conductings.And second input signal is to close gate voltage Voff, and therefore, first to the 3rd transistor Tr 1-Tr3 turn-offs respectively, thus storage signal V SiRemain on shown in Fig. 8 A the preceding voltage status as low level storage signal voltage V-for example.
After about 1H, for example, at gate signal g I+1The period T 2 of the voltage Von that opens the door in, first direction signal DIRa changes over the 3rd high level voltage Vh3 from the 3rd low level voltage Vl3, and second direction signal DIRBa changes over the 3rd low level voltage Vl3 from the 3rd high level voltage Vh3.
Therefore, the 6th transistor Tr 6 is at gate signal g I+1The period T 2 of the voltage Von that opens the door in conductings, and the voltage Von that will open the door is sent to the control end of first to the 3rd transistor Tr 1-Tr3, conducting first to the 3rd transistor Tr 1-Tr3.
As top with reference to Fig. 3 and 4 described, the first clock signal C K1 is in period T 2 on the first low level voltage Vl1, and the second and the 3rd clock signal C K1B and CK2 are in respectively on the first high level voltage Vh1 and the Vh2.Therefore, the second high level voltage Vh2 and the high pressure AVDD with the 3rd clock signal C K2 is sent to output terminal OP.Therefore, storage signal V SiChange over high level storage signal voltage V+ from low level storage signal voltage V-, and the second capacitor C2 that charges.
When changing over the 3rd low level voltage Vl3 after first direction signal DIRa has passed through period T 2, the 6th transistor Tr 6 is turn-offed.But transistor Tr 5 remains on the conducting state by the voltage that is charged to the second capacitor C2, thereby still high pressure AVDD is sent to output terminal OP, causes storage signal V SiKeep high level storage signal voltage V+.
Then, even number signal generating circuit 710a is described in further detail, for example, the operation of (i+1) signal generating circuit 710a.
Still with reference to Fig. 6 and 8A, in (i+1) signal generating circuit 710a, when will be as (i+2) gate signal g of first input signal I+2The voltage Von that opens the door be supplied to first input end IP11, and will be as the i gate signal g of second input signal iPass gate voltage Voff when being supplied to the second input end IP12, give first direction control end IP13 with second direction signal DIRBa as the first direction signal provision, and give second direction control end IP14 as the second direction signal provision first direction signal DIRa.
Because at gate signal g I+1The period 1 T1 of the voltage Von that opens the door in, first direction signal DIRBa is in that the 3rd low level voltage Vl3 goes up and second direction signal DIRa is on the 3rd high level voltage Vh3, therefore the 6th transistor Tr 6 shutoffs, and 7 conductings of the 7th transistor Tr.Second input signal is that the pass gate voltage Voff and first to the 3rd transistor Tr 1-Tr3 turn-off respectively, thus storage signal V SiRemain on the preceding voltage status as high level storage signal voltage V+ for example.
After about 1H, for example, at gate signal g I+2The period T 2 of the voltage Von that opens the door in, first direction signal DIRBa changes over the 3rd high level voltage Vh3 and second direction signal DIRa changes over the 3rd low level voltage Vl3 from the 3rd high level voltage Vh3 from the 3rd low level voltage Vl3.
Therefore, the 6th transistor Tr 6 is at gate signal g I+2The period T 2 of the voltage Von that opens the door in conductings, and the voltage Von that will open the door is sent to the control end of first to the 3rd transistor Tr 1-Tr3 respectively, with conducting first to the 3rd transistor Tr 1-Tr3 respectively.
As top with reference to Fig. 3 and 4 described, the first clock signal C K1 is on the first high level voltage Vh1, be in respectively on the first low level voltage Vl1 and the Vl2 with the second and the 3rd clock signal C K1B and CK2, thereby low level voltage Vl2 and the low pressure AVSS of the 3rd clock signal C K2 is sent to output terminal OP.Therefore, storage signal V Si+1Change over low level storage signal voltage V-from high level storage signal voltage V+, and the first capacitor C1 that charges.
When changing over the 3rd low level voltage Vl3 after first direction signal DIRBa has passed through period T 2, the 6th transistor Tr 6 is turn-offed.But the 4th transistor Tr 4 remains on the conducting state by the voltage that is charged to the first capacitor C1, thereby still low pressure AVSS is sent to output terminal OP, and storage signal V Si+1Remain on the low level storage signal voltage V-.
Hereinafter, the direction of scanning with reference to gate driver 401 is the back describes in further detail operation from signal generating circuit 710a to Fig. 8 of direction B.In this case, the waveform of direction signal DIRa and DIRBa is opposite with top situation with reference to the described forward direction of Fig. 8 A.
With reference to Fig. 6 and 8B, at the cycle 1H of the voltage Von that opens the door that is applied to the respective doors signal on the second input end IP12 as second input signal, for example, be connected in the period T subsequently 2 of above-mentioned period T 2, transistor Tr 7 conductings, first to the 3rd transistor Tr 1-Tr3 is conducting respectively also.More particularly, state of operation first to the 5th transistor Tr 1-Tr5 and first and second capacitor C1 and the C2 according to first to the 3rd clock signal C K1, CK1B and CK2 are sent to the respective stored electrode wires with storage signal.The operation of first to the 5th transistor Tr 1-Tr5 and the first and second capacitor C1 and C2 is approximate and as mentioned above, the direction of scanning of gate driver is that the situation of forward direction is identical, therefore omits description of them here.
As mentioned above, in one exemplary embodiment of the present invention, the first and second direction signal DIRa and DIRBa are applied to respectively on the first and second direction control end IP13 and the IP14.And the first and second direction signal DIRa and the every 1H of DIRBa replace between the 3rd high level voltage Vh3 and the 3rd low level voltage Vl3.Therefore, transistorized operating characteristic can not degenerated because of the element that applies for a long time He cause thus of direction signal DIRa and DIRBa and be changed.
Except the polycrystal film transistor, the signal that is presented in the sequential chart of Fig. 8 A and 8B also can be applied to contain the transistorized LCD of noncrystal membrane.
In an one exemplary embodiment, gate driver 401 is bidirectional gate drivers, and one of first to the 4th scanning commencing signal STV1 and STV4 can be applied to the signal generating circuit 710a that supplies with gate signal according to the direction of scanning.
The LCD of the alternative one exemplary embodiment according to the present invention is described in further detail with reference to Fig. 9-13B hereinafter.
Fig. 9 is the calcspar of the LCD of another one exemplary embodiment according to the present invention, Figure 10 is the schematic circuit according to the signal generating circuit of the one exemplary embodiment of the present invention among Fig. 9, and Figure 11 is the plane figure according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 10.Figure 12 is that illustration is applied to the gateable clock signal and the signal timing diagram that is applied to the relation of the store clock signal on the storage signal generator on the gate driver according to an embodiment of the invention.Figure 13 A and 13B are the signal timing diagrams according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 10, wherein, Figure 13 A is that the direction of scanning of gate driver is the example of the signal sequence of forward direction, and Figure 13 B be the direction of scanning of gate driver is the example of back to the signal sequence of direction.
Except the different piece that describes in further detail below, identical according to the LCD of the one exemplary embodiment of the present invention shown in Fig. 9-13B LCD approximate and shown in Fig. 1 to 6.Therefore, represent to carry out the element of same or similar operation, and below will omit any of them is repeated in this description with identical label.
With reference to Fig. 9, LCD comprises liquid crystal panel assembly 300b, gate driver 402, data driver 500, the grayscale voltage generator 800 that is connected with data driver 500, storage signal generator 702 and signal controller 602.
The same with LCD as shown in Figure 5 with top more detailed description, gate driver 402 is bidirectional gate drivers.
The first and second storage signal generative circuit 702a and the 702b of storage signal generator 702 can comprise respectively and storage electrode line S 1-S 2nThe a plurality of signal generating circuit 710b and each the signal generating circuit 710b that connect are similar with signal generating circuit 710a as shown in Figure 6.
As shown in figure 10, signal generating circuit 710b comprises output terminal OP, first to the 5th transistor Tr 1-Tr5 and first and second capacitor C1 and the C2.
Signal generating circuit 710b further comprises input end IP21 and control end OP22.In i signal generating circuit 710b, for example, input end IP21 and supply i gate signal g iI door line G as first input signal iConnect, similarly, in (i+1) signal generating circuit 710b, input end IP21 and supply (i+1) gate signal g I+1(i+1) door line G as first input signal I+1Connect.
To be supplied to signal generating circuit 710b respectively from first, second and the 3rd clock signal C K1, CK1B and the CK2 of the storage control signal CONT3 of signal controller 602, and will be supplied to signal generating circuit 710b from the high pressure AVDD and the low pressure AVSS of signal controller 602 or external unit (not shown).
Further will give signal generating circuit 710b by control end IP22 from the store clock signal provision of a plurality of store clock signal CLK_L (for example, as shown in figure 10), CLK_R, CLKB_L and the CLKB_R of the storage control signal CONT3 of signal controller 602.
Shown in Fig. 9 and 11, the signal generating circuit 710b of the first storage signal generative circuit 702a is positioned at the left side of liquid crystal panel assembly 300b and generates even number storage signal V S2, V S4..., V S2n, and the store clock signal CLK_L of a plurality of store clock signal CLK_L, CLK_R, CLKB_L and the CLKB_R that will apply from the left side of liquid crystal panel assembly 300b and CLKB_L alternate supplies are given signal generating circuit 710b.The signal generating circuit 710b of the second storage signal generative circuit 702b is positioned at the relative right side of liquid crystal panel assembly 300b and generates odd number storage signal V S1, V S3..., V S2n-1, and the store clock signal CLKB_R of a plurality of store clock signal CLK_L, CLK_R, CLKB_L and the CLKB_R that will apply from the right side of liquid crystal panel assembly 300b and CLK_L alternate supplies are given signal generating circuit 710b.
In alternative one exemplary embodiment of the present invention, can change the first and second storage signal generative circuit 702a and 702b annexation between the position on the liquid crystal panel assembly 300b, the first and second storage signal generative circuit 702a and 702b and storage electrode line and the operative relationship of the first and second storage signal generative circuit 702a and 702b and a plurality of store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R.
And, in alternative one exemplary embodiment, a plurality of store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R can be relevant with the gate control signal CONT1 that generates gate signal, and can generate according to the gateable clock signal that is applied on gate drive circuit 402a and the 402b.
The example of the gateable clock signal of one exemplary embodiment and store clock signal is presented among Figure 12 according to the present invention.
Figure 12 shows when the direction of scanning of gate driver 402 is forward direction, generates i, (i+1), (i+2) and (i+3) gate signal g respectively when gateable clock signal GCK_L, GCK_R, GCKB_L and GCKB_R are applied to i, g I+1, g I+2And g I+3The first and second gate drive circuit 402a and during 402b, a plurality of store clock signal CLK_L, CLKB_R, CLKB_L and CLK_R are applied to and generate i, (i+1), (i+2) and (i+3) storage signal S respectively i, S I+1, S I+2And S I+3The first and second storage signal generative circuit 702a and store clock signal CLK_L, CLKB_R, CLKB_L and the CLK_R on the 702b.
But when the direction of scanning of gate driver 402 is backs during to direction, gateable clock signal GCK_L, GCK_R, GCKB_L and GCKB_R among Figure 12 generate (i+3), (i+2), (i+1) and i gate signal g respectively I+3, g I+2, g I+1And g iSignal and store clock signal CLK_L, CLKB_R, CLKB_L and CLK_R can be applied on the first and second storage signal generative circuit 702a and the 702b, generate (i+3), (i+2), (i+1) and i storage signal S respectively I+3, S I+2, S I+1And S i
The pulse width of store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R can be that about 2H and their dutycycle can be about 50%.The every approximately 2H of store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R swing once.As shown in figure 12, each of two respective stored clock signal clk _ R and CLKB_R or CLK_L and CLKB_L has the opposite waveform of phase place.Respective stored clock signal clk _ R and CLKB_R each and and store clock signal CLK_R and CLKB_R corresponding store clock signal CLK_L and CLKB_L between have predetermined time delay.In an exemplary embodiment, can be for example about 1H time delay, but be not limited to this.Store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R have the 4th high level voltage Vh4 and the 4th low level voltage Vl4 (Figure 13 A).For example, high level voltage Vh4 can be that about 15V and low level voltage Vl4 can be about-1V, but is not limited to this.
Signal generating circuit 710b further comprises alternative the 6th transistor Tr 61 and alternative the 7th transistor Tr 71 that each contains control end, input end and output terminal.
The input of alternative the 6th transistor Tr 61 is connected with input end IP21 with control end, and the output terminal of alternative the 6th transistor Tr 61 is connected with the control end of first to the 3rd transistor Tr 1-Tr3, thereby makes alternative the 6th transistor Tr 61 play diode effectively.
The control end of alternative the 7th transistor Tr 71 is connected with control end IP22, and the input end of alternative the 7th transistor Tr 71 is connected with input end IP21, and the output terminal of alternative the 7th transistor Tr 71 is connected with the control end of first to the 3rd transistor Tr 1-Tr3.
Referring now to Figure 13 A signal generating circuit 710b is described in further detail, wherein, the direction of scanning of gate driver 402 is forward directions.
When with i gate signal g iThe voltage Von that opens the door be supplied to signal generating circuit 710b, for example, during the input end IP21 of the i signal generating circuit 710b that is connected with the even number storage line, 61 conductings of alternative the 6th transistor Tr and first to the 3rd also conducting of transistor Tr 1-Tr3.
Therefore, for i gate signal g iThe applying of the voltage Von that opens the door, will have that signal based on the voltage level of the state separately of first to the 3rd clock signal C K1, CK1B and CK2 is sent to output terminal OP respectively and as storage signal V SiOutput.
In the period 1 T1 of the voltage Von that opens the door of gate signal gi, the first clock signal C K1 is on the first low level voltage Vl1, be in respectively on the first and second high level voltage Vh1 and the Vh2 with the second and the 3rd clock signal C K1B and CK2, and have the storage signal V of high level storage signal voltage V+ by the operation of the first, the 3rd and the 5th transistor Tr 1, Tr3 and Tr5 from output terminal OP output Si
But, because at gate signal g iThe period T 2 of the voltage Von that opens the door in, the first clock signal C K1 changes over the first high level voltage Vh1, change over first and second low level voltage Vl1 and the Vl2 respectively with the second and the 3rd clock signal C K1B and CK2, will have the storage signal V of low level storage signal voltage V-by first, second operation with the 4th transistor Tr 1, Tr2 and Tr4 SiBe sent to output terminal OP, thereby make storage signal V SiChange over low level storage signal voltage V-from high level storage signal voltage V+.
After period T 2, gate signal g iChange over and close gate voltage Voff, thereby alternative the 6th transistor Tr 61 of diode action is turn-offed.Consequently, the voltage VN of the node N (Figure 10) that is attached thereto of each output terminal of alternative the 6th transistor and alternative the 7th transistor Tr 61 and Tr71 iHigh level state before keeping causes first to the 3rd transistor Tr 1-Tr3 to keep conducting state, changes over the 4th high level voltage Vh4 once more up to the store clock signal CLK_L that is applied on the control end IP22.Storage signal V SiVoltage level determine according to the voltage level of first to the 3rd clock signal C K1, CK1B and CK2.More particularly, the first clock signal C K1 changes over the first low level voltage Vl1, change over first and second high level voltage Vh1 and the Vh2 respectively with the second and the 3rd clock signal C K1B and CK2, thereby according to the first, the 3rd and the 5th transistor Tr 1, Tr3 and Tr5 operation according to first, second and the 3rd clock signal C K1, CK1B and CK2, V+ is sent to output terminal OP with high level storage signal voltage, causes storage signal V SiChanging over high level storage signal voltage V+ from low level storage signal voltage V-exports from output terminal OP.
After having passed through the schedule time, when the store clock signal CLK_L on being applied to control end IP22 is on the 4th high level voltage Vh4,71 conductings of alternative the 7th transistor Tr, thereby with gate signal g iPass gate voltage Voff be applied on the control end of first to the 3rd transistor Tr 1-Tr3.Therefore, each of first to the 3rd transistor Tr 1-Tr3 is all turn-offed.So, storage signal V SiAccording to the operation of the voltage that is charged to capacitor C2 and the 5th transistor Tr 5, in next frame, keep high level storage signal voltage V+ according to charging voltage.
Then, (i+1) signal generating circuit 710b at (i+1) that be connected with the odd number storage line connects describes the operation of signal generating circuit 710b.
Still with reference to Figure 10 and 13A, when with (i+1) gate signal g I+1The voltage Von that opens the door when being supplied to input end IP21,61 conductings of alternative the 6th transistor Tr and first to the 3rd transistor Tr 1-Tr3 be conducting respectively also.
Therefore, for (i+1) gate signal g I+1The applying of the voltage Von that opens the door, will have that signal based on the voltage level of the state of first to the 3rd clock signal C K1, CK1B and CK2 is sent to output terminal OP respectively and as storage signal V Si+1Output.
At gate signal g I+1The period 1 T1 of the voltage Von that opens the door in, the first clock signal C K1 is on the first high level voltage Vh1, be in respectively on the first and second low level voltage Vl1 and the Vl2 with the second and the 3rd clock signal C K1B and CK2, and by first, second the and the operation of the 4th transistor Tr 1, Tr2 and Tr4 have the storage signal V of low level storage signal voltage V-from output terminal OP output Si+2
But, at gate signal g I+1The period T 2 of the voltage Von that opens the door in, the first clock signal C K1 changes over the first low level voltage Vl1, change over first and second high level voltage Vh1 and the Vh2 respectively with the second and the 3rd clock signal C K1B and CK2, and will have the storage signal V of high level storage signal voltage V+ by first, second operation with the 4th transistor Tr 1, Tr2 and Tr4 Si+1Be sent to output terminal OP.Therefore, storage signal V Si+1Changing over high level storage signal voltage V+ from low level storage signal voltage V-exports from output terminal OP.
After period T 2, gate signal g I+1Change over and close gate voltage Voff, but be applied to before store clock signal CLKB_R on the direct control end IP22 changes over the 4th high level voltage Vh4 the voltage VN of node N I+1Low level state Vl5 before can not changing over, but the operation of alternative the 6th transistor Tr 61 by playing diode action remains on the high level state Vh5, causes first to the 3rd transistor Tr 1-Tr3 to remain on conducting state respectively.So, because the first clock signal C K1 is on the first high level voltage Vh1, with the second and the 3rd clock signal C K1B and CK2 be respectively first and second low level voltage Vl1 and the Vl2, the operation by first, second and the 4th transistor Tr 1, Tr2 and Tr4 is sent to output terminal OP as storage signal V with low level storage signal voltage V- Si+1Consequently, storage signal V Si+1Change over low level storage signal voltage V-from high level storage signal voltage V+ once more.
After having passed through the schedule time, when the store clock signal CLKB_R on being applied to control end IP22 changes over the 4th high level voltage Vh4,71 conductings of alternative the 7th transistor Tr, and will close the gate signal g of gate voltage Voff I+1Be applied to respectively on the control end of first to the 3rd transistor Tr 1-Tr3, turn-off first to the 3rd transistor Tr 1-Tr3.Therefore, storage signal V Si+1According to the operation of charging voltage and the 4th transistor Tr 4 of capacitor Cl, remain on low level storage signal voltage V-and go up up to next frame.
Hereinafter, with reference to Figure 13 B the operation of signal generating circuit 710b is described in further detail, wherein, the direction of scanning of gate driver 402 is that the back is to direction.
Shown in Figure 13 B, the gate signal separately on being applied to input end IP21, the operation that it is the signal generating circuit 710b under the forward direction situation that the operation of signal generating circuit 710b is similar to top direction of scanning described with reference to Figure 13 A, gate driver 402 is identical, therefore, will omit here any of them will be repeated in this description.
According to aforesaid one exemplary embodiment of the present invention, in the time cycle of about 1H of the period 1 T1 of the voltage Von that opens the door, the corresponding level of exporting the 3rd clock signal C K2 is as storage signal, but because the response speed of LCD is compared slowly with time cycle 1H, approximately the variation of the storage signal of 1H can not cause the significant change of pixel electrode line.
And, be applied to store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R on the control end IP22 of signal generating circuit 710b as shown in figure 10 according to the voltage level that closes on the gate voltage Voff decision node N, cause the voltage level that is sent to output terminal OP during the time cycle of about 1H that first to the 3rd clock signal C K1, CK1B and CK2 change, can not change, thereby make the voltage level of storage signal remain to next frame with suitable amplitude leyel.
Therefore, in the storage signal generator 702 of the LCD of one exemplary embodiment, remove normal door line G according to the present invention 1-G 2nOutside transmit the extra gate signal a door line be unnecessary, and do not need and the corresponding discrete direction signal in the direction of scanning of gate driver 402.
The LCD of another one exemplary embodiment according to the present invention is described in further detail to 17B referring now to Figure 14.
Figure 14 is the calcspar of the LCD of another one exemplary embodiment according to the present invention.Figure 15 is the schematic circuit according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 14, and Figure 16 is the plane figure according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 15.Figure 17 A is the signal timing diagram according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 15 that utilizes the row counter-rotating, and Figure 17 B is the signal timing diagram according to the signal generating circuit of the one exemplary embodiment of the present invention among Figure 15 that utilizes the frame counter-rotating.
Except the different piece that describes in further detail below, approximate identical with the LCD of top one exemplary embodiment in greater detail according to the LCD of the one exemplary embodiment of the present invention shown in Figure 14-17B.Therefore, in Figure 14-17B with identical label represent to carry out with above-mentioned one exemplary embodiment in the element of same or analogous operation, and below will omit any of them will be repeated in this description.
As shown in figure 14, LCD comprises the signal controller 603 of liquid crystal panel assembly 300c, gate driver 403, data driver 500, the grayscale voltage generator 800 that is connected with data driver 500, storage signal generator 703 and the top element of control.
As shown in Figure 9, gate driver 403 is bidirectional gate drivers.
Storage signal generator 703 comprises first and second storage signal generative circuit 703a and the 703b.Each comprises each and a plurality of storage electrode line S the first and second storage signal generative circuit 703a and 703b 1-S 2n(Fig. 1) a plurality of signal generating circuit 710c of Lian Jieing.
Approximate with as shown in figure 10 that of each signal generating circuit 710c is identical, for example, as shown in figure 15, each signal generating circuit 710c comprises output terminal OP, each all contains first to the 5th transistor Tr 1-Tr5 and the first and second capacitor C1 and the C2 of control end, input end and output terminal.
But each signal generating circuit 710c further comprises first input end IP31 and the second input end IP32 and control end IP41.
With reference to Figure 15, in i signal generating circuit 710c, first input end IP31 and supply (i+2) gate signal g I+2(i+2) door line G I+2Connect, and the second input end IP32 and supply (i-2) gate signal g I-2(i-2) door line G I-2Connect.
Similarly, in (i+1) signal generating circuit 710c, first input end IP31 and supply (i+3) gate signal g I+3(i+3) door line G I+3Connect, and the second input end IP32 and supply (i-1) gate signal g I-1(i-1) door line G I-1Connect.
As shown in figure 16, the second input end IP32 of each first signal generating circuit 710c of the first and second storage signal generative circuit 703a and 703b receives and is applied to scanning commencing signal STV1 of first on adjacent door driving circuit 403a and the 403b and the 3rd scanning commencing signal STV3 respectively, and will be applied to the first input end IP31 that the scanning commencing signal STV2 of second on adjacent door driving circuit 403a and the 403b and the 4th scanning commencing signal STV4 are supplied to the last signal generating circuit 710c of the first and second storage signal generative circuit 703a and 703b.But, in alternative one exemplary embodiment, for example, can will be supplied to first and second input end IP31 and the IP32 of first and the last signal generating circuit 710c of the first and second storage signal generative circuit 703a and 703b from the discrete signals of external unit (not shown) by the discrete signals line as the glitch line, but be not limited to this.
To be supplied to signal generating circuit 710c respectively from first, second and the 3rd clock signal C K1, CK1B and the CK2 of the storage control signal CONT3 of signal controller 603, and will be supplied to signal generating circuit 710c from the high pressure AVDD and the low pressure AVSS of signal controller 603 or external unit (not shown).
Still with reference to Figure 16, also will be supplied to each signal generating circuit 710c from one of a plurality of gateable clock signal GCK_L, GCK_R, GCKB_L and GCKB_R of gate control signal (Figure 14) CONT1 of signal controller 603 by control end IP41.
Refer back to Figure 15, signal generating circuit 710c comprises that further each all contains the 8th to the tenth transistor Tr 8-Tr10 of control end, input end and output terminal.
The control end of the 8th transistor Tr 8 is connected with first input end IP31, the input end of the 8th transistor Tr 8 is connected with the first direction signal DIR of storage control signal CONT3a, and the output terminal of the 8th transistor Tr 8 is connected with the control end of first to the 3rd transistor Tr 1-Tr3.
The control end of the 9th transistor Tr 9 is connected with the second input end IP32, the input end of the 9th transistor Tr 9 is connected with the second direction signal DIRB of storage control signal CONT3a, and the output terminal of the 9th transistor Tr 9 is connected with the control end of first to the 3rd transistor Tr 1-Tr3.
The control end of the tenth transistor Tr 10 is connected with control end IP41, and the input end of the tenth transistor Tr 10 is connected with pass gate voltage Voff, and the output terminal of the tenth transistor Tr 10 is connected with the control end of first to the 3rd transistor Tr 1-Tr3.
Each first and second storage signal generative circuit 703a that all contain signal generating circuit 710c and the operation of 703b will be described in further detail below.Just for for the purpose of the illustration, the counter-rotating type of described LCD is the row counter-rotating.
To be forward directions at the direction of scanning of gate driver 403 below, thereby first direction signal DIR has high level voltage, and second direction signal DIRB have the situation of low level voltage, describes the operation of signal generating circuit 710c with reference to Figure 17 A.
And, with reference to Figure 15 and 17A signal generating circuit 710c is described, for example, with i storage electrode line S as the odd number storage electrode line iThe operation of the i signal generating circuit that connects.
Applying i gate signal g iThe voltage Von that opens the door after, (i+2) gate signal g I+2The voltage Von that opens the door be applied on the input end IP31, thereby make 8 conductings of the 8th transistor Tr, therefore, the 3rd high level voltage Vh3 of first direction signal DIR is applied to respectively by node N1 on the control end of first to the 3rd transistor Tr 1-Tr3, conducting first to the 3rd transistor Tr 1-Tr3.
Therefore, shown in Figure 17 A, applying (i+2) gate signal g I+2About 2H of the voltage Von that opens the door in, output to output terminal OP as storage signal V based on the respective voltage level of the voltage level of first to the 3rd clock signal C K1, CK1B and CK2 SiAt this moment, because (i-2) gate signal g I-2Keep closing open voltage Voff, thus 9 shutoffs of the 9th transistor Tr, and second direction signal DIRB does not influence the voltage VN1 of node N1.
Therefore, at (i+2) gate signal g I+2The period 1 T1 of the voltage Von that opens the door in, by the operation of first, second and the 4th transistor Tr 1, Tr2 and Tr4, be in storage signal V on the low level storage signal voltage V-from output terminal OP output SiAt (i+2) gate signal g I+2The period T 2 of the voltage Von that opens the door in, by the operation of the first, the 3rd and the 5th transistor Tr 1, Tr3 and Tr5, be in storage signal V on the high level storage signal voltage V+ from output terminal OP output Si
Still with reference to Figure 17 A, at (i+2) gate signal g I+2The period T 2 of the voltage Von that opens the door after, the gateable clock signal GCK_L that is applied on the control end IP41 is approximately keeping the 4th high level voltage Vh4 in the 2H.
Consequently, the tenth transistor Tr 10 conductings and will close gate voltage Voff and be applied on the node N1, and turn-off first to the 3rd transistor Tr 1-Tr3 respectively.
So, because to the operation of the voltage of second capacitor C2 charging and the 5th transistor Tr 5, storage signal V according to charging voltage SiRemaining on high level storage signal voltage V+ goes up up to next frame.
Then, describe in further detail and (i+1) storage electrode line S with reference to Figure 15 and 17A as the even number storage electrode line I+1The operation of the signal generating circuit 710C that connects.
710C is the same with the i signal generating circuit, as (i+3) gate signal g I+3The voltage Von that opens the door when being applied to input end IP31 and going up, 8 conductings of the 8th transistor Tr, and conducting first to the 3rd transistor Tr 1-Tr3 respectively of the first direction signal by having the 3rd high level voltage Vh3.Therefore, based on first, second storage signal V with the corresponding level voltage of the voltage level of the 3rd clock signal C K1, CK1B and CK2 Si+1Output to output terminal OP respectively.
As (i+3) gate signal g I+3State change over when opening the door voltage Von from closing gate voltage Voff, the gateable clock signal GCK_R that is applied on the control end IP41 is approximately keeping the 4th high level voltage Vh4 in the 2H.
Therefore, 10 conductings of the tenth transistor Tr, and by being sent to pass gate voltage Voff shutoff first to the 3rd transistor Tr 1-Tr3 of node N1.Subsequently, storage signal V Si+1According to the voltage of first capacitor C1 charging and the 4th transistor Tr 4 according to the operation of charging voltage, keep low level storage signal voltage V-up to next frame.
In the direction of scanning of gate driver 403 is back under the situation of direction, and first direction signal DIR has the 3rd low level voltage Vl3 and second direction signal DIRB has the 3rd high level voltage Vh3.Therefore, different with the scan forward direction, when the direction of scanning is back during to direction, by being applied to gate signal on the second input end IP32 and second direction signal DIRB conducting first to the 3rd transistor Tr 1-Tr3 respectively.
Except top description, the direction of scanning of the operation of signal generating circuit 710c and gate driver 403 is forward directions, it is identical with the situation of the storage signal of the corresponding level of respective stored electrode wires that output has, and therefore omits being repeated in this description the operation of channel selector 710c here.And, with the direction of scanning of gate driver 403 be that the situation of forward direction is similar, the gate signal that is applied on the first input end IP31 after the output enabling signal Von, is exported in a frame and is closed gate signal Voff in about 2H, thereby the 8th transistor Tr 8 is turn-offed.Therefore, first direction signal DIR does not influence the voltage VN1 of node N1.
Then, with reference to Figure 15 and 17B the operation of signal generating circuit 710c is described in further detail, in this case, the LCD of one exemplary embodiment works under the frame reversing mode according to the present invention.
The operation of signal generating circuit 710c is described in further detail referring now to Figure 17 B.The operation of signal generating circuit 710c with reference to the class of operation of the described signal generating circuit 710c of Figure 17 A seemingly.
In Figure 17, first, second and the 3rd clock signal C K1, CK1B and the every predetermined period of CK2 are (for example, about 1H) alternate, but shown in Figure 17 B, first, second keeps constant voltage with each of the 3rd clock signal C K1, CK1B and CK2 in a frame.But shown in Figure 17 B, each the every successive frames of waveform of first, second and the 3rd clock signal C K1, CK1B and CK2 is anti-phase.
When the direction of scanning of gate driver 403 was forward direction, first direction signal DIR has the 3rd high level voltage Vh3 and second direction signal DIRB has the 3rd low level voltage Vl3.
At first, description is gone up, is had for example data voltage of positive polarity, with i storage electrode line S for being applied to pixel PX iThe operation of the i signal generating circuit 710c that connects.
The first clock signal C K1 keeps the first low level voltage Vl1, and the second and the 3rd clock signal C K1B and CK2 keep the first high level voltage Vh1.
Applying i gate signal g iThe voltage Von that opens the door after, when with (i+2) gate signal g I+2The voltage Von that opens the door when being applied to first input end IP31 and going up, the 8th transistor Tr 8 conductings, and first to the 3rd transistor Tr 1-Tr3 is respectively by first direction signal DIR conducting.
Because the 3rd clock signal C K2 keeps the second high level voltage Vh2, storage signal V SiKeep high level storage signal voltage V+.
As (i+2) gate signal g I+2Change over and close gate voltage Voff, and go up by being applied to control end IP41, when the corresponding clock signal as gateable clock signal GCK_L is for example turn-offed first to the 3rd transistor Tr 1-Tr3, storage signal V SiKeep high level storage signal voltage V+ up to next frame according to the voltage that is charged to the second capacitor C2 and the 5th transistor Tr 5 according to the operation of charging voltage.
Then, when the data voltage with negative polarity being described in further detail being applied to pixel PX and going up, with i storage electrode line S iThe operation of the i signal generating circuit 710c that connects.In this case, the first clock signal C K1 keeps the first high level voltage Vh1, and the second and the 3rd clock signal C K1B and CK2 keep the first low level voltage Vl1.
Applying i gate signal g iThe voltage Von that opens the door after, when with (i+2) gate signal g I+2The voltage Von that opens the door when being applied to first input end IP31 and going up, in response to 8 conductings of the 8th transistor Tr, first to the 3rd transistor Tr 1-Tr3 is conducting respectively also.Therefore, by keeping the 3rd clock signal C K2 of the second low level voltage V12, make storage signal V SiOutput low level storage signal voltage V-.
Subsequently, as (i+2) gate signal g I+2Change over and close gate voltage Voff and when being applied to gateable clock signal GCK_L on the control end IP41 and turn-offing first to the 3rd transistor Tr 1-Tr3 respectively, storage signal V SiAccording to keeping low level storage signal voltage V-up to next frame according to the operation of charging voltage to the voltage of first capacitor C2 charging and the 4th transistor Tr 4.
When the sweep signal of gate driver 403 along the back during to direction, first direction signal DIR has the 5th low level voltage Vl5 and second direction signal DIRB has the first high level voltage Vh5.
Therefore, when the direction of scanning of gate driver 403 is backs during to direction, by being applied to gate signal on the second input end IP32 and second direction signal DIRB conducting first to the 3rd transistor Tr 1-Tr3 respectively.Except top description, the operation of signal generating circuit 710c and the direction of scanning of top gate driver in greater detail 403 are that the situation of forward direction is identical, and therefore any of operation who omits here signal generating circuit 710c is repeated in this description.
As mentioned above, when LCD worked with the frame reversing mode, first, second kept same voltage level with the 3rd clock signal C K1, CK1B and CK2 in an about frame.
So, be applied to gate signal on the respective pixel row change over from the voltage Von that opens the door close gate voltage Voff after, because as shown in figure 15 signal generating circuit 710c the frame counter-rotating occurred according to from the next stage output of the first or second gate driver 403a or 403b, postponed the voltage Von work of opening the door of the gate signal of about 2H with respect to the previous stage of the first or second gate driver 403a or 403b.Therefore, owing to be applied to i door line G iOn the differing between the voltage Von of opening the door of opening the door voltage Von and being applied on the i storage signal generative circuit 710c be about 2H, the voltage Von that opens the door can be not overlapping.Therefore, after the charging operations of i pixel column is finished substantially, be applied to i storage electrode line S iOn storage signal V SiSignal level change, thereby according to storage signal V SiThe change signal level change the charging voltage of i pixel column.
Alternately, when after the change of gate signal is finished, having passed through the schedule time, first, second state with the 3rd clock signal C K1, CK1B and CK2 can change respectively, and can change over the pass gate voltage from the voltage that opens the door in gate signal, or alternately, after changing over the voltage that opens the door, the pass gate voltage exports first, second and the 3rd clock signal C K1, CK1B and CK2 respectively.
According to one exemplary embodiment of the present invention as described herein, because utility voltage is fixed on the predetermined level, be applied on the storage electrode line with the storage signal that predetermined period changes with amplitude, the scope of pixel electrode voltage has been increased, with made the expanded range of pixel voltage, the scope of grayscale voltage does not then have corresponding increase.Therefore, enlarge the effective voltage scope of grayscale voltage, thereby improved resolution effectively.
And, the scope of the pixel voltage that under the situation of scope greater than the storage signal that is applying predetermined value of the pixel voltage that generates under the situation of the data voltage that applies certain scope, generates.Therefore, reduced power consumption effectively.In addition, need not additional to have adopted the LCD that contains bidirectional gate driver and storage signal generator with selecting circuit, thereby dwindled the size of LCD effectively and/or reduced the manufacturing cost of LCD.
In alternative one exemplary embodiment, the LCD of one exemplary embodiment can be reversed and row counter-rotating work according to for example frame according to the present invention, but is not limited to this.
The present invention should not be understood that to be confined to the one exemplary embodiment that this paper provides.Or rather, providing these one exemplary embodiment is for the disclosure being become comprehensively thoroughly, passing on notion of the present invention to those of ordinary skill in the art fully.
Though by the present invention having been made specific descriptions with reference to some one exemplary embodiment of the present invention, but those of ordinary skill in the art should be understood that, can do various changes to it in form and details, and not depart from the spirit and scope of the present invention that appended claims limits.

Claims (44)

1. display device comprises:
Many door lines are used to transmit the gate signal with open the door voltage and pass gate voltage;
Many data lines are used to transmit data voltage;
Many storage electrode lines are used to transmit storage signal;
Be arranged in a plurality of pixels of approximate matrix pattern, wherein, at least one pixel of these a plurality of pixels comprises:
With an on-off element that data line is connected in door line in the many door lines and many data lines;
The liquid crystal capacitor that is connected with utility voltage with on-off element; And
With a holding capacitor that storage electrode line is connected in on-off element and many storage electrode lines;
Gate driver is used for along first direction of scanning or second direction of scanning generates gate signal; And
A plurality of signal generating circuits are used for generating storage signal according at least one control signal and at least one gate signal,
Wherein, be applied to storage signal at least one pixels of this a plurality of pixels and have at the charging data voltage and be charged to the voltage level that changes after liquid crystal capacitor and the holding capacitor, and storage signal becomes from the output order of a plurality of signal generating circuits direction of scanning with gate driver.
2. display device according to claim 1, wherein, when the charging data voltage has positive polarity, the storage signal that is applied on this at least one pixels of this a plurality of pixels changes over high level from low level, and when charging data voltage when having negative polarity, the storage signal that is applied on this at least one pixels of this a plurality of pixels changes over low level from high level.
3. display device according to claim 2, wherein, the every successive frames of storage signal that is applied on the given storage electrode line of these many storage electrode lines is anti-phase.
4. display device according to claim 3, wherein, utility voltage is a fixed voltage.
5. display device according to claim 4, wherein,
These a plurality of pixels comprise:
Supply with first pixel of first gate signal;
Adjacent with first pixel and be supplied to second pixel of second gate signal; And
Adjacent with first pixel and be supplied to the 3rd pixel of the 3rd gate signal;
A plurality of signal generating circuits comprise:
First storage signal is sent to first signal generating circuit of the storage electrode line of first pixel;
Second storage signal is sent to the secondary signal generative circuit of the storage electrode line of second pixel; And
The 3rd storage signal is sent to the 3rd signal generating circuit of the storage electrode line of the 3rd pixel; And
First gate signal or the 3rd gate signal are supplied to the secondary signal generative circuit.
6. display device according to claim 4, wherein,
These a plurality of pixels comprise:
Be supplied to first pixel of first gate signal;
Adjacent with first pixel and be supplied to second pixel of second gate signal; And
Adjacent with first pixel and be supplied to the 3rd pixel of the 3rd gate signal;
A plurality of signal generating circuits comprise:
First storage signal is sent to first signal generating circuit of the storage electrode line of first pixel;
Second storage signal is sent to the secondary signal generative circuit of the storage electrode line of second pixel; And
The 3rd storage signal is sent to the 3rd signal generating circuit of the storage electrode line of the 3rd pixel; And
Second gate signal is supplied to the secondary signal generative circuit.
7. display device according to claim 4, wherein, this at least one control signal comprise first control signal, second control signal and the 3rd control signal and
At least one signal generating circuit of a plurality of signal generating circuits comprises:
Receive at least one gate signal and according to the signal input unit of at least one gate signal output drive control signal;
Receive first control signal and transmit the storage signal applying unit of first control signal as storage signal according to drive control signal from signal input unit;
Receive second control signal and the 3rd control signal and change the control module of the mode of operation of control module according to drive control signal; And
Second control signal or the 3rd control signal according to the mode of operation according to control module applies keep the signal holding unit from the storage signal of storage signal applying unit.
8. display device according to claim 7, wherein, signal input unit further receives each and all has first direction signal and second direction signal based on the signal condition of gate driver direction of scanning.
9. display device according to claim 8, wherein, the phase place of the phase place of first direction signal and second direction signal is in fact opposite.
10. display device according to claim 9, wherein, this at least one gate signal comprises first gate signal and second gate signal, and the mistiming of opening the door between the voltage application time of open the door voltage application time and this second gate signal of this first gate signal is about two horizontal cycles (2H).
11. display device according to claim 10, wherein, this signal input unit is selected one of first gate signal and second gate signal according to first direction signal and second direction signal, and according to selected first gate signal or selected second gate signal output drive control signal.
12. display device according to claim 11, wherein, each is all in fact consistent for the level of the level of this first direction signal and second direction signal.
13. display device according to claim 12, wherein, this signal input unit comprises:
Contain the control end that is connected with the first direction signal, the first transistor of input end that is connected with first gate signal and the output terminal that is connected with drive control signal; And
Contain the control end that is connected with the second direction signal, the transistor seconds of input end that is connected with second gate signal and the output terminal that is connected with drive control signal.
14. display device according to claim 11, wherein, the first direction signal has first level voltage and the second direction signal has second level voltage, and this first direction signal and second direction signal each all whenever in succession predetermined period between first level voltage and second level voltage alternately.
15. display device according to claim 14, wherein, predetermined period be an about horizontal cycle (1H) at interval.
16. display device according to claim 14, wherein, be applied to the phase place of the first direction signal on first signal generating circuit of a plurality of signal generating circuits and to be applied to the phase place of the second direction signal on the secondary signal generative circuit of a plurality of signal generating circuits adjacent with first signal generating circuit in fact opposite.
17. display device according to claim 15, wherein, signal input unit comprises:
Contain the control end that is connected with the first direction signal, the first transistor of input end that is connected with first gate signal and the output terminal that is connected with drive control signal; And
Contain the control end that is connected with the second direction signal, the transistor seconds of input end that is connected with second gate signal and the output terminal that is connected with drive control signal.
18. display device according to claim 9, wherein, this at least one gate signal comprises first gate signal and second gate signal, and the mistiming of opening the door between the voltage application time of open the door the voltage application time and second gate signal of this first gate signal is about four horizontal cycles (4H).
19. display device according to claim 18, wherein, signal input unit is selected one of first direction signal and second direction signal according to first gate signal and second gate signal, and according to selected first direction signal or selected second direction signal output drive control signal.
20. display device according to claim 19, wherein, each is all in fact consistent for the level of the level of first direction signal and second direction signal.
21. display device according to claim 20, wherein, the clock signal that further will have first level voltage and second level voltage different with first level voltage is supplied to signal input unit, and the level of clock signal whenever in succession predetermined period between first level voltage and second level voltage alternately.
22. display device according to claim 21, wherein, this predetermined period be about two horizontal cycles (2H) at interval.
23. display device according to claim 22, wherein, be applied to the phase place of the clock signal on first signal generating circuit of a plurality of signal generating circuits and to be applied to the phase place of the clock signal on the second adjacent signals generative circuit of a plurality of signal generating circuits in fact opposite.
24. display device according to claim 23, wherein, signal input unit is by changing the state of operation signal holding unit based on the drive control signal of first direction signal or second direction signal according to clock signal.
25. display device according to claim 24, wherein, signal input unit comprises:
Contain the input end that is connected with the first direction signal, the first transistor of control end that is connected with first gate signal and the output terminal that is connected with drive control signal;
Contain the input end that is connected with the second direction signal, the transistor seconds of control end that is connected with second gate signal and the output terminal that is connected with drive control signal; And
Contain the input end that is connected with the pass gate voltage, the 3rd transistor of control end that is connected with clock signal and the output terminal that is connected with drive control signal.
26. display device according to claim 25, wherein, be applied to the voltage level of the storage signal on first storage electrode line of many storage electrode lines and to be applied to the voltage level of the storage signal on the second adjacent storage electrode line of many storage electrode lines practically identical.
27. display device according to claim 26, wherein, the voltage level of the voltage level of first control signal, second control signal is in fact consistent and anti-phase about every successive frames in given frame with the voltage level of the 3rd control signal.
28. display device according to claim 7, wherein, the gateable clock signal is supplied to signal input unit with the clock signal with first level voltage and second level voltage different with first level voltage, and clock signal whenever in succession predetermined period between first level voltage and second level voltage alternately.
29. display device according to claim 28, wherein, predetermined period be about two horizontal cycles (2H) at interval.
30. display device according to claim 29, wherein, be applied to the phase place of the clock signal on first signal generating circuit of a plurality of signal generating circuits and to be applied to the phase place of the clock signal on the second adjacent signals generative circuit of a plurality of signal generating circuits in fact opposite.
31. display device according to claim 30, wherein, signal input unit is by changing the state of operation signal holding unit based on the drive clock signal of at least one gate signal according to clock signal.
32. display device according to claim 31, wherein, signal input unit comprises:
Contain each control end that all is connected and the first transistor of input end with the output terminal that is connected with drive control signal with gate signal; And
The transistor seconds that contains the control end that is connected with clock signal, the input end that is connected with gate signal and the output terminal that is connected with drive control signal.
33. display device according to claim 7, wherein, the storage signal applying unit comprises the first transistor that contains the control end that is connected with the output terminal of signal input unit, the input end that is connected with first control signal and the output terminal that is connected with a storage electrode line in many storage electrode lines.
34. display device according to claim 33, wherein, control module comprises:
The transistor seconds that contains control end that is connected with the output terminal of signal input unit and the input end that is connected with second control signal; And
The 3rd transistor that contains control end that is connected with the output terminal of signal input unit and the input end that is connected with the 3rd control signal.
35. display device according to claim 34, wherein, the signal holding unit comprises:
Contain the control end that is connected with the 3rd transistorized output terminal, the 4th transistor of input end that is connected with first driving voltage and the output terminal that is connected with storage electrode line;
Contain the control end that is connected with the output terminal of transistor seconds, the 5th transistor of input end that is connected with second driving voltage and the output terminal that is connected with storage electrode line;
Be connected first capacitor between the 4th transistorized input end and the control end; And
Be connected second capacitor between the 5th transistorized input end and the control end.
36. display device according to claim 7, wherein, the voltage level of the storage signal on the voltage level that is applied to the storage signal on first storage electrode line of many storage electrode lines and the second adjacent storage electrode line that is applied to many storage electrode lines is different.
37. display device according to claim 36, wherein,
Each all has first level voltage and second level voltage first control signal, second control signal and the 3rd control signal,
The level separately of first control signal, second control signal and the 3rd control signal in given frame every subsequent cycles between first level voltage and second level voltage alternately and
The level separately of first control signal, second control signal and the 3rd control signal is anti-phase every a frame.
38. display device according to claim 1 further comprises at least one extra gate line that gate signal is sent to a signal generating circuit in a plurality of signal generating circuits.
39. display device according to claim 1, wherein, be sent to the voltage and be sent at least a portion of the voltage predetermined time cycle of opening the door of second gate signal of adjacent second line of many door lines overlapped in time of opening the door of first gate signal of first line of many door lines.
40. according to the described display device of claim 39, wherein, predetermined period of time be an about horizontal cycle (1H) at interval.
41. the driving method of a LCD, this LCD comprise many door lines, are used to transmit the gate signal with the voltage that opens the door; Many data lines are used to transmit data voltage; Many storage electrode lines are used to transmit storage signal; Door line in a plurality of on-off elements, each on-off element of a plurality of on-off elements and many door lines is connected with a data line in many data lines; A plurality of pixels, each pixel of a plurality of pixels comprise with a plurality of on-off elements in on-off element and many storage electrode lines in a holding capacitor that storage electrode line is connected; Gate driver is used for along first direction of scanning or second direction of scanning generates gate signal; And a plurality of signal generating circuits, being used to generate storage signal, this driving method comprises:
First gate signal is applied on first line of many door lines that are connected with first pixel of a plurality of pixels;
First data voltage is applied on first data line of many data lines that are connected with first pixel;
Second gate signal is applied on second line of many door lines that are connected with second pixel of a plurality of pixels; And
According to second gate signal storage signal is outputed to first pixel,
Wherein, the output order of storage signal becomes with first direction of scanning or second direction of scanning of gate driver.
42. according to the described method of claim 41, wherein, the voltage application time of opening the door of first gate signal and the voltage application time of opening the door of second gate signal about two horizontal cycles (2H) of being separated by.
43. according to the described method of claim 41, wherein, the voltage application time of opening the door of first gate signal and the voltage application time of opening the door of second gate signal about four horizontal cycles (4H) of being separated by.
44. the driving method of a LCD, this LCD comprise many door lines, are used to transmit the gate signal with the voltage that opens the door; Many data lines are used to transmit data voltage; Many storage electrode lines are used to transmit storage signal; Door line in a plurality of on-off elements, each on-off element of a plurality of on-off elements and many door lines is connected with a data line in many data lines; A plurality of pixels, each pixel of a plurality of pixels comprise with a plurality of on-off elements in on-off element and many storage electrode lines in a holding capacitor that storage electrode line is connected; Gate driver is used for along first direction of scanning or second direction of scanning generates gate signal; And a plurality of signal generating circuits, being used to generate storage signal, this driving method comprises:
On a door line in the many door lines that gate signal is applied to a pixel in a plurality of pixels is connected;
Data voltage is applied on the data line in many data lines that are connected with this pixel; And
According to gate signal storage signal is outputed to this pixel,
Wherein, the output order of storage signal becomes with first direction of scanning or second direction of scanning of gate driver.
CNA2007101671501A 2006-10-24 2007-10-24 Display device and driving method thereof Pending CN101169924A (en)

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KR101393638B1 (en) 2014-05-26
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CN102622984B (en) 2015-07-29
CN102622985A (en) 2012-08-01

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Application publication date: 20080430