CN102622984B - Display device and driving method thereof - Google Patents

Display device and driving method thereof Download PDF

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Publication number
CN102622984B
CN102622984B CN201210101486.9A CN201210101486A CN102622984B CN 102622984 B CN102622984 B CN 102622984B CN 201210101486 A CN201210101486 A CN 201210101486A CN 102622984 B CN102622984 B CN 102622984B
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China
Prior art keywords
signal
voltage
gate
storage
transistor
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Expired - Fee Related
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CN201210101486.9A
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CN102622984A (en
Inventor
李明雨
朴商镇
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Publication of CN102622984A publication Critical patent/CN102622984A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

Liquid crystal display comprises: many door lines, for transmitting the gate signal having enabling voltage and close gate voltage; A plurality of data lines, for transmitting data voltage; Many storage electrode lines, for transmitting storage signal; Multiple pixel, wherein, each pixel of multiple pixel comprises the holding capacitor be connected with a storage electrode line in on-off element and many storage electrode lines; Gate driver, for generating gate signal; And multiple signal generating circuit, for generating storage signal according at least one control signal and at least one gate signal.The storage signal applied on each pixel has the voltage level changed after data voltage is charged to liquid crystal capacitor and holding capacitor.

Description

Display device and driving method thereof
The divisional application that this case is the applying date is on October 24th, 2007, application number is 200710167150.1, denomination of invention is the application for a patent for invention of " display device and driving method thereof ".
Cross
This application claims the right of priority of No. 10-2006-0103375th, the korean patent application proposed on October 24th, 2006 and No. 10-2007-0041300th, the korean patent application proposed on April 27th, 2007, hereby quote in full, for reference.
Technical field
The present invention relates to display device and driving method thereof, particularly relate to display device and the driving method thereof of brightness increase and lower power consumption.
Background technology
In general, liquid crystal display (" LCD ") comprises the first display panel containing pixel electrode and contains the second display panel of common electrode and the therebetween liquid crystal layer containing anisotropy dielectric material.Pixel electrode is arranged in approximate matrix pattern and is connected, to receive data voltage successively with the on-off element as such as thin film transistor (TFT) (" TFT ").Common electrode is formed and can receive utility voltage on the whole surface of the second display panel.Liquid crystal capacitor is formed by each pixel electrode, common electrode and liquid crystal layer therebetween.Liquid crystal capacitor and the on-off element be connected with liquid crystal capacitor form pixel cell.
In an lcd, voltage is applied on pixel electrode and common electrode, such as in liquid crystal layer, forms electric field between which.The intensity of electric field determines the transmissivity through the light of liquid crystal layer, and forms required image by the Control of Voltage be applied on pixel electrode and common electrode.When electric field is only applied on liquid crystal layer along a direction (such as polarity), LCD may be deteriorated.In order to prevent being deteriorated, can about such as each frame, row or pixel inversion data voltage relative to the polarity of utility voltage polarity.
But the scope for utilizing row reversion (inverting method of the polarity of such as row reversal data voltage according to pixels) to show the data voltage of image is less than the scope for utilizing a reversion (such as by the inverting method of the polarity of each pixel inversion data voltage) to show the data voltage of image.Therefore, if as in perpendicular alignmnet (" VA ") mode LCD, for driving the starting voltage of the liquid crystal in liquid crystal layer higher, then the low-voltage of the data voltage range that the grayscale voltage shown for image represents becomes equally low with starting voltage.Therefore, Precise Representation brightness is difficult to.
In addition, carry out the polarity of row reversal data voltage according to pixels to reduce the row reversion of power consumption as the small LCD being used in such as mobile phone those, but require high resolution due to small LCD, thus improve power consumption.
Summary of the invention
Display device according to one exemplary embodiment comprises: many door lines, for transmitting the gate signal having enabling voltage and close gate voltage; A plurality of data lines, for transmitting data voltage; Many storage electrode lines, for transmitting storage signal; Be arranged in multiple pixels of approximate matrix pattern, wherein, each pixel of multiple pixel comprises the on-off element be connected with a door line in many door lines and a data line in a plurality of data lines, the liquid crystal capacitor be connected with on-off element and utility voltage and the holding capacitor be connected with a storage electrode line in on-off element and many storage electrode lines; Gate driver, for generating gate signal along the first direction of scanning or the second direction of scanning; And multiple signal generating circuit, for generating storage signal according at least one control signal and at least one gate signal.
The storage signal be applied at least one pixel of multiple pixel has the voltage level changed after charge data voltage is charged to liquid crystal capacitor and holding capacitor, and storage signal becomes from the output order of multiple signal generating circuit with the direction of scanning of gate driver.
When charge data voltage has positive polarity, storage signal can change over high level from low level, and when charge data voltage has negative polarity, storage signal can change over low level from high level.
Be applied on the given storage electrode line of many storage electrode lines storage signal can often successive frames be anti-phase.
Utility voltage can be fixed voltage.
Multiple pixel can comprise first pixel, adjacent with the first pixel and be supplied to the second pixel of the second gate signal and adjacent with the first pixel and be supplied to the 3rd pixel of the 3rd gate signal of supply first gate signal.
Multiple signal generating circuit can comprise the first signal generating circuit the first storage signal being sent to the storage electrode line of the first pixel, the storage electrode line the second storage signal being sent to the second pixel secondary signal generative circuit and the 3rd storage signal is sent to the 3rd signal generating circuit of storage electrode line of the 3rd pixel.
In alternative one exemplary embodiment of the present invention, the first gate signal or the 3rd gate signal are supplied to secondary signal generative circuit, maybe the second gate signal can be supplied to secondary signal generative circuit.
At least one control signal can comprise the first control signal, the second control signal and the 3rd control signal.At least one signal generating circuit of multiple signal generating circuit can comprise at least one gate signal of reception and export the signal input unit of drive control signal according at least one gate signal, receive the first control signal and transmit the storage signal applying unit of the first control signal as storage signal according to the drive control signal from signal input unit, receive the second control signal and the 3rd control signal and change the control module of mode of operation of control module and the second control signal applied according to the mode of operation according to control module and the 3rd control signal according to drive control signal, keep the signal holding unit from the storage signal of storage signal applying unit.
Signal input unit can receive each further and have first direction signal based on the signal condition of gate driver direction of scanning and second direction signal.First direction signal and second direction signal can have in fact contrary phase place.
At least one gate signal can comprise the first gate signal and the second gate signal, and the mistiming between the enabling voltage application time of the enabling voltage application time of the first gate signal and the second gate signal is about two horizontal cycles (" 2H ").
Signal input unit according to first direction signal and one of second direction signal behavior first gate signal and the second gate signal, and can export drive control signal according to selected first gate signal or the second gate signal.
First direction signal and second direction signal each can keep in fact consistent level.
First direction signal and second direction signal can have the first level voltage and second electrical level voltage respectively, and first direction signal and second direction signal can often in succession predetermined period between the first level voltage and second electrical level voltage alternately.Predetermined period can be an about horizontal cycle (" 1H ").
The phase place being applied to the first direction signal on the first signal generating circuit of multiple signal generating circuit can be in fact contrary with the phase place of the second direction signal be applied on the secondary signal generative circuit of multiple signal generating circuits adjacent with the first signal generating circuit.
Signal input unit can comprise containing the control end be connected with first direction signal, the input end be connected with the first gate signal and the first transistor of output terminal that is connected with drive control signal.Signal input unit may further include containing the control end be connected with second direction signal, the input end be connected with the second gate signal and the transistor seconds of output terminal that is connected with drive control signal.
At least one gate signal can comprise the first gate signal and the second gate signal, and the mistiming between the enabling voltage application time of the enabling voltage application time of the first gate signal and the second gate signal is about four horizontal cycles (" 4H ").
Signal input unit can select one of first direction signal and second direction signal according to the first gate signal and the second gate signal, and exports drive control signal according to selected direction signal.
First direction signal and each level that can be consistent of second direction signal.
Further the clock signal with the first level voltage and the second electrical level voltage different from the first level voltage can be supplied to signal input unit, and clock signal can often in succession predetermined period between the first level voltage and second electrical level voltage alternately.Predetermined period can be about two horizontal cycles (" 2H ").
The phase place being applied to the clock signal on the first signal generating circuit of multiple signal generating circuit is in fact contrary with the phase place of the clock signal on the second adjacent signal generating circuit being applied to multiple signal generating circuit.
Signal input unit can by changing the state of operation signal holding unit of the drive control signal based on first direction signal or second direction signal according to clock signal.
In alternative one exemplary embodiment, signal input unit can comprise: containing the input end be connected with first direction signal, the control end be connected with the first gate signal and the first transistor of output terminal that is connected with drive control signal; Containing the input end be connected with second direction signal, the control end be connected with the second gate signal and the transistor seconds of output terminal that is connected with drive control signal; And containing with input end, the control end be connected with clock signal and the third transistor of output terminal be connected with drive control signal of closing gate voltage and being connected.
The voltage level being applied to the storage signal on the first storage electrode line of many storage electrode lines is practically identical with the voltage level of the storage signal on the second adjacent storage electrode line being applied to many storage electrode lines.The voltage level of the voltage level of the first control signal, the voltage level of the second control signal and the 3rd control signal is giving in framing in fact every successive frames of making peace anti-phase.
Can by Gating clock signal with there is the first level voltage and the second electrical level voltage different from the first level voltage be supplied to signal input unit, and clock signal can often in succession predetermined period between the first level voltage and second electrical level voltage alternately.Predetermined period can be about two horizontal cycles (" 2H ").
The phase place being applied to the clock signal on the first signal generating circuit of multiple signal generating circuit is in fact contrary with the phase place of the clock signal on the second adjacent signal generating circuit being applied to multiple signal generating circuit.
In alternative one exemplary embodiment, signal input unit can by changing the state of operation signal holding unit based on the driving clock signal of at least one gate signal according to clock signal.Further, signal input unit can comprise the first transistor of the control end and input end that are connected with gate signal containing each and the output terminal be connected with drive control signal; And containing the control end be connected with clock signal, the input end be connected with gate signal and the transistor seconds of output terminal that is connected with drive control signal.
Storage signal applying unit can comprise containing the control end be connected with the output terminal of signal input unit, the input end be connected with the first control signal and the first transistor of output terminal that is connected with storage electrode line.
Control module can comprise the transistor seconds containing the control end be connected with the output terminal of signal input unit and the input end be connected with the second control signal and the third transistor containing the control end be connected with the output terminal of signal input unit and the input end be connected with the 3rd control signal.
Signal holding unit can comprise containing the control end is connected with the output terminal of third transistor, the input end be connected with the first driving voltage and the 4th transistor of output terminal be connected with storage electrode line and the 5th transistor of output terminal that contains the control end be connected with the output terminal of transistor seconds, the input end be connected with the second driving voltage and be connected with storage electrode line.Signal holding unit may further include the first capacitor between input end and control end being connected to the 4th transistor and the second capacitor between the input end being connected to the 5th transistor and control end.
The voltage level being applied to the storage signal on the first storage electrode line of many storage electrode lines is different with the voltage level of the storage signal on the be applied to many storage electrode lines second adjacent storage electrode line.
First control signal, the second control signal and the 3rd control signal each can have the first level voltage and second electrical level voltage, and the respective level of the first control signal, the second control signal and the 3rd control signal is giving in framing and can often subsequent cycles replace between the first level voltage and second electrical level voltage.Further, the respective level of the first control signal, the second control signal and the 3rd control signal can be anti-phase every a frame.
At least one extra gate line gate signal being sent to a signal generating circuit in multiple signal generating circuit is may further include according to the display device of one exemplary embodiment of the present invention.
The enabling voltage predetermined time cycle of the second gate signal of the enabling voltage being sent to the first gate signal of first line of many door lines and adjacent second line being sent to many door lines at least partially in overlapped in time.
The interval of predetermined period of time can be an about horizontal cycle (" 1H ").
Another one exemplary embodiment of the present invention provides a kind of driving method of liquid crystal display.This liquid crystal display comprises many door lines, for transmitting the gate signal with enabling voltage; A plurality of data lines, for transmitting data voltage; Many storage electrode lines, for transmitting storage signal; Multiple on-off element, each on-off element of multiple on-off element is connected with a data line in a door line in many door lines and a plurality of data lines; Multiple pixel, each pixel of multiple pixel comprises the holding capacitor be connected with a storage electrode line in the on-off element of in multiple on-off element and many storage electrode lines; Gate driver, for generating gate signal along the first direction of scanning or the second direction of scanning; And multiple signal generating circuit, for generating storage signal.
This driving method comprise the first gate signal is applied to the many door lines be connected with the first pixel of multiple pixel first line on, first data voltage is applied on the first data line of a plurality of data lines be connected with the first pixel, second gate signal is applied on second line of the many door lines be connected with the second pixel of multiple pixel, and according to the second gate signal, storage signal is outputted to the first pixel.The output order of storage signal becomes with the first direction of scanning of gate driver or the second direction of scanning.
The application time of the application time of the enabling voltage of the first gate signal and the enabling voltage of the second gate signal is separated by about two horizontal cycles (" 2H "), or in an alternative one exemplary embodiment, about four horizontal cycles (" 4H ") of being separated by.
In another one exemplary embodiment, provide a kind of driving method of liquid crystal display.This liquid crystal display comprises many door lines, for transmitting the gate signal with enabling voltage; A plurality of data lines, for transmitting data voltage; Many storage electrode lines, for transmitting storage signal; Multiple on-off element, each on-off element of multiple on-off element is connected with a data line in a door line in many door lines and a plurality of data lines; Multiple pixel, each pixel of multiple pixel comprises the holding capacitor be connected with a storage electrode line in the on-off element of in multiple on-off element and many storage electrode lines; Gate driver, for generating gate signal along the first direction of scanning or the second direction of scanning; And multiple signal generating circuit, for generating storage signal.
This driving method comprises on a door line in many door lines gate signal being applied to and being connected with the pixel of in multiple pixel, data voltage is applied on a data line in a plurality of data lines be connected with this pixel, and according to gate signal, storage signal is outputted to this pixel.The output order of storage signal becomes with the first direction of scanning of gate driver or the second direction of scanning.
Accompanying drawing explanation
In conjunction with the drawings one exemplary embodiment of the present invention is described in further detail, of the present invention above and other side, feature and advantage will become more obviously, in the accompanying drawings:
Fig. 1 is the calcspar of the liquid crystal display according to the present invention's one exemplary embodiment;
Fig. 2 is the equivalent circuit diagram of a pixel of liquid crystal display according to the present invention's one exemplary embodiment;
Fig. 3 is the schematic circuit of the signal generating circuit according to the present invention's one exemplary embodiment;
Fig. 4 is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Fig. 3;
Fig. 5 is the calcspar of the liquid crystal display according to another one exemplary embodiment of the present invention;
Fig. 6 is the schematic circuit of the signal generating circuit of storage signal generative circuit according to the one exemplary embodiment of the present invention in Fig. 5;
Fig. 7 A and Fig. 7 B is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Fig. 6;
Fig. 8 A and Fig. 8 B is the signal timing diagram of the signal generating circuit according to the present invention's alternative one exemplary embodiment;
Fig. 9 is the calcspar of the liquid crystal display according to another one exemplary embodiment of the present invention;
Figure 10 is the schematic circuit of the signal generating circuit according to the one exemplary embodiment of the present invention in Fig. 9;
Figure 11 is the plane figure of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 10;
Figure 12 is the signal timing diagram illustrating the Gating clock signal be applied to according to an embodiment of the invention on gate driver and the relation being applied to the store clock signal on storage signal generator;
Figure 13 A and Figure 13 B is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 10;
Figure 14 is the calcspar of the liquid crystal display according to another one exemplary embodiment of the present invention;
Figure 15 is the schematic circuit of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 14;
Figure 16 is the plane figure of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 15;
Figure 17 A is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 15 utilizing row reversion; And
Figure 17 B is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 15 utilizing frame to reverse.
The present invention describes in detail
Now, hereinafter with reference to illustrating that the accompanying drawing of one exemplary embodiment of the present invention describes the present invention more fully.But the present invention can implement in many different forms, should not be construed and be confined to embodiment given here.Or rather, provide these embodiments to be to make the disclosure become comprehensively thoroughly, and pass on scope of the present invention to those of ordinary skill in the art fully.Identical label represents identical element from start to finish.
Should be understood that when an element be called as " " another element " on " time, it can directly on other element or can there is insertion element (intervening element) therebetween.In contrast to this, when an element be called as " directly existing " another element " on " time, there is not insertion element.As used herein, term "and/or" comprises and one or morely relevant lists any of item and all combinations.
Although should be understood that term " first ", " second ", " the 3rd " etc. may be used for describing various element, parts, region, layer and/or part in this article, these elements, parts, region, layer and/or part should not limit by these terms.These terms are only for distinguishing an element, parts, region, layer or part and another element, parts, region, layer or part.Therefore, be the present invention's instruction can not be departed from the second element, parts, region, layer or part by the first element discussed below, parts, region, layer or part names.
Term used herein just in order to describe specific embodiment, instead of intends to limit the present invention.As used herein, unless context separately clearly shows, singulative " ", " one " and " being somebody's turn to do " also have a mind to comprise plural form.It is also to be understood that, term " comprise " or " comprising " where used in this disclosure, there are described feature, region, integer, step, operation, element and/or parts in regulation, but does not get rid of existence or additional one or more further feature, region, integer, step, operation, element, parts and/or their cohort.
And, as D score or " end " and " on " or " top " relative terms may be used in this article describing as shown in the figure, the relation of an element and other element.Should be understood that except describing orientation in the drawings, relative terms has a mind to comprise the different orientation of equipment.Such as, if turned by the equipment in a figure, so, the element being described as be at other element D score side become other element " on " side.Therefore, the concrete orientation of view and determining, exemplary term D score can comprise D score and " on " orientation.Similarly, if the equipment in a figure is turned, so, be described as " " other element " below " or the element of " below " become " " other element " above ".Therefore, exemplary term " ... below " or " in ... below " above and below orientation can be comprised.
Unless otherwise defined, with all terms (comprising technology and scientific terminology) in this article have with those of ordinary skill in the art usually understand identical implication.It is also to be understood that, should be interpreted as having the consistent implication of implication with them under background of related as the term being defined in common dictionary those, unless and clear and definite definition so in this article, should idealized or too formally do not explained.
Here the section with reference to the schematic illustration as idealized embodiments of the present invention illustrates description one exemplary embodiment of the present invention.Like this, due to the such as reason such as manufacturing technology and/or tolerance limit, expect to have and be different from illustrative shape.Therefore, embodiments of the invention should not be understood as that the given shape being confined to illustrative region herein, but comprise and such as manufacture the shape caused and depart from.Such as, illustrate or be described as smooth region there is coarse and/or nonlinear feature usually.In addition, illustrative wedge angle may be round.Therefore, the region illustrated in the drawings is schematic, and their shape is not intended to the exact shape of exemplary area, is also not intended to limit the scope of the invention.
Referring now to accompanying drawing, the present invention is described in further detail.
Fig. 1 is the calcspar of the liquid crystal display according to the present invention's one exemplary embodiment, and Fig. 2 is the equivalent circuit diagram of the pixel PX of liquid crystal display according to the present invention's one exemplary embodiment.
As shown in Figure 1, comprise such as liquid crystal panel assembly 300, gate driver 400, data driver 500, the grayscale voltage generator 800 be connected with data driver 500, storage signal generator 700 according to the liquid crystal display (" LCD ") of the present invention's one exemplary embodiment and control the signal controller 600 of upper element, but being not limited to these.
Liquid crystal panel assembly 300 comprises many signal line (G 1-G 2n, G d, D 1-D mand S 1-S 2n) and with many signal line (G 1-G 2n, G d, D 1-D mand S 1-S 2n) connect and be arranged in multiple pixel PX of approximate matrix pattern.
With reference to Fig. 2, liquid crystal panel assembly 300 comprises aspectant lower panel 100 and top panel 200 and the liquid crystal layer between lower panel 100 and top panel 200 3.
With reference to Fig. 1, many signal line (G 1-G 2n, G d, D 1-D mand S 1-S 2n) comprise many door line G 1-G 2nand G d, a plurality of data lines D 1-D mwith many storage electrode line S 1-S 2n.
Many door line G 1-G 2nand G dcomprise many normal door line G of transmission gate signal (being hereafter referred to as " sweep signal ") 1-G 2nwith extra gate line G d.Many storage electrode line S 1-S 2nwith many normal door line G 1-G 2nconnect and transmit storage signal.A plurality of data lines D 1-D mtransmit data voltage.
Many door line G 1-G 2n, G dwith many storage electrode line S 1-S 2nextend also in fact (substantially) along first approximate (substantially) line direction to be parallel to each other, and a plurality of data lines D 1-D mextend along the vertical with first direction second approximate column direction and be in fact parallel to each other.
Referring again to Fig. 2, each pixel PX(such as, with the i-th normal door line G i(i=1,2 ..., 2n), the i-th normal storage signal wire S i(i=1,2 ..., 2n) and jth data line D j(j=1,2 ..., pixel PX m) connected) comprise and signal wire G iand D jconnect on-off element Q and with on-off element Q and storage signal line S ithe liquid crystal capacitor Clc connected and holding capacitor Cst.
In an exemplary embodiment, on-off element Q can be embodied as the three-terminal element (three-terminal element) be such as arranged on lower panel 100, as thin film transistor (TFT) (" TFT "), but is not limited to this.As shown in Figure 2, three-terminal element contains and normal door line G iconnect control end, with data line D jthe input end connected and the output terminal be connected with liquid crystal capacitor Clc and holding capacitor Cst.
The pixel electrode 191 of lower panel 100 and the common electrode 270 of top panel 200 are first end and second end of liquid crystal capacitor Clc respectively.Liquid crystal layer 3 between pixel electrode 191 and common electrode 270 plays dielectric material.Pixel electrode 191 is connected with on-off element Q.Common electrode 270 is positioned on whole top panel 200 and to receive utility voltage Vcom(not shown).Alternately, below plate 100 can form common electrode 270, in this case, at least one of pixel electrode 191 and common electrode 270 can have the shape of approximately linear.
In alternative one exemplary embodiment of the present invention, utility voltage Vcom can comprise direct current (" the DC ") voltage such as with predetermined value, but is not limited to this.
Holding capacitor Cst sub LCD capacitor Clc, by formed be therebetween insulator with storage electrode line S ithe pixel electrode 191 intersected is formed.
For colour display, each pixel PX can represent a kind of primary colors, such as, empty point (apatial division), or alternately, each pixel PX can represent the different primary colors depending on preset time, such as, the time-division.In any case, required color all passes through primary colors, such as, and red, green and blue space or time and show.
Fig. 2 shows the one exemplary embodiment of the present invention utilizing empty point.As shown in the figure, each pixel PX on the region of the top panel 200 corresponding with pixel electrode 191, containing representing one of three primary colors, such as, one of red, green and blue color filter 230.In alternative one exemplary embodiment of the present invention, color filter 230 below the pixel electrode 191 of plate 100 below or can be formed above.
The polarizer (not shown) that light is polarized is attached in liquid crystal panel assembly 300.
Refer back to Fig. 1, grayscale voltage generator 800 can generate all grayscale voltage relevant with the required transmissivity of pixel PX or limited grayscale voltage (hereinafter referred to as " reference gray level voltage ").Some (reference) grayscale voltages have positive polarity relative to utility voltage Vcom, and other (reference) grayscale voltage has negative polarity relative to utility voltage Vcom.
Gate driver 400 comprises the first gate drive circuit 400a and the second gate drive circuit 400a of the opposite side being such as positioned at liquid crystal panel assembly 300 as left side and right side, but is not limited to this.
First gate drive circuit 400a and many door line G 1-G 2nand G dodd number normal door line G 1, G 3..., and G 2n-1with extra gate line G done end connect.Second gate drive circuit 400b and many door line G 1-G 2nand G deven number normal door line G 2, G 4..., and G 2none end connect.Alternately, the second gate drive circuit 400b can with many door line G 1-G 2nand G dodd number normal door line G 1, G 3..., and G 2n-1with extra gate line G done end connect, and the first gate drive circuit 400a can with many door line G 1-G 2nand G deven number normal door line G 2, G 4..., and G 2none end connect.
First gate drive circuit 400a and the second gate drive circuit 400b each utilize enabling voltage (gate-on voltage) Von and close gate voltage (gate-off voltage) Voff generate be applied to many door line G 1-G 2nand G don gate signal.
In an one exemplary embodiment of the present invention, gate driver 400 and many signal line G 1-G 2n, G d, D 1-D mand S 1-S 2nbe integrated into together with on-off element Q in liquid crystal panel assembly 300.In alternative one exemplary embodiment, gate driver 400 can comprise and being arranged in liquid crystal panel assembly 300, or is arranged at least one integrated circuit (" the IC ") chip on flexible print circuit (" the FPC ") film in the thin-film package (" TCP ") that is attached in liquid crystal panel assembly 300.Alternately, gate driver 400 can be arranged on discrete printed circuit board (PCB) (not shown).
Such as, storage signal generator 700 comprises the opposite side and the first storage signal generative circuit 700a adjacent with the second gate drive circuit 400b with the first gate drive circuit 400a and the second storage signal generative circuit 700b that are arranged in liquid crystal panel assembly 300, but is not limited to this.
First storage signal generative circuit 700a and odd number storage electrode line S 1, S 3..., S 2n-1with even number normal door line G 2, G 4..., G 2nconnect, and multiple storage signals with high level voltage and low level voltage are applied to storage electrode line S 1, S 3..., S 2n-1on.
Second storage signal generative circuit 700b and even number storage electrode line S 2, S 4..., S and except the 1st normal door line G 1outside odd number normal door line G 3, G 5..., G 2n-1with extra gate line G dconnect, and multiple storage signals with high level voltage and low level voltage are applied to storage electrode line S 2, S 4..., S 2non.
In an alternative one exemplary embodiment of the present invention, can not by from the extra gate line G be connected with gate driver 400 dsignal provision to storage signal generator 700.Or rather, can by such as from the signal provision of image signal controller 600 or the such separate unit of discrete signals generator (not shown) to storage signal generator 700, but be not limited to this.In this case, as mentioned above, liquid crystal panel assembly 300 can not form extra gate line G d.
In an one exemplary embodiment of the present invention, storage signal generator 700 and many signal line G 1-G 2n, G d, D 1-D mand S 1-S 2nbe integrated into together with on-off element Q in liquid crystal panel assembly 300.In alternative one exemplary embodiment, storage signal generator 700 can comprise and being arranged in liquid crystal panel assembly 300, or is arranged at least one the IC chip on the FPC film in the TCP that is attached in liquid crystal panel assembly 300.Alternately, storage signal generator 700 can be arranged on discrete printed circuit board (PCB) (not shown).
The a plurality of data lines D of data driver 500 and panel assembly 300 1-D mconnect, the data voltage selected in the grayscale voltage supplied from grayscale voltage generator 800 is applied to a plurality of data lines D 1-D mon.But when grayscale voltage generator 800 generates some instead of whole grayscale voltage, data driver 500 can divide reference gray level voltage, to generate data voltage from grayscale voltage.
Signal controller 600 control gate driver 400, data driver 500 and storage signal generator 700.
In an exemplary embodiment, data driver 500, signal controller 600 and grayscale voltage generator 800 can comprise at least one the IC chip being arranged in liquid crystal panel assembly 300 or on FPC film in being arranged on the TCP that is attached in liquid crystal panel assembly 300.Alternately, data driver 500, signal controller 600 and grayscale voltage generator 800 at least one can with many signal line G 1-G 2n, G d, D 1-D mand S 1-S 2nbe integrated into together with on-off element Q in liquid crystal panel assembly 300.In another alternative one exemplary embodiment, each of data driver 500, signal controller 600 and grayscale voltage generator 800 can be integrated in single IC chip, but at least one of data driver 500, signal controller 600 and grayscale voltage generator 800, or data driver 500, signal controller 600 and grayscale voltage generator 800 at least one at least one circuit component can be positioned at the outside of single IC chip.
Still with reference to Fig. 1 and 2, the operation of liquid crystal display is described in further detail now.
Signal controller 600 receives received image signal R, G and B and from the control inputs picture signal R of external graphics controller (not shown), multiple input control signals of G and B.Received image signal R, G and B comprise the monochrome information of pixel PX, and brightness has the gray-scale value of predetermined number, such as, and 1024(=2 10), 256(=2 8) or 64(=2 6) individual gray-scale value, but be not limited to these.
Such as, multiple input control signal comprises vertical synchronizing signal Vsync, horizontal-drive signal Hsync, master clock signal MCLK and data enable signal DE, but is not limited to these.
Signal controller 600 is according to input control signal (not shown) and received image signal R, G and B process received image signal R, G and B, and, according to the operating conditions of liquid crystal panel assembly 300, generate gate control signal CONT1, data controlling signal CONT2 and storage control signal CONT3, gate control signal CONT1 is applied on gate driver 400, data controlling signal CONT2 and data image signal DAT is applied on data driver 500, and storage control signal CONT3 is applied on storage signal generator 700.
The first scanning commencing signal STV1(that gate control signal CONT1 comprises the beginning determining enabling voltage Von is not shown) and the second scanning commencing signal STV2(not shown) and at least one clock signal (not shown) in output cycle of control enabling voltage Von.In an exemplary embodiment, the first scanning commencing signal STV1 is applied on the first gate drive circuit 400a, and the second scanning commencing signal STV2 is applied on the second gate drive circuit 400b.In alternative one exemplary embodiment of the present invention, the first scanning commencing signal STV1 can be applied on the second gate drive circuit 400b, and the second scanning commencing signal STV2 is applied on the first gate drive circuit 400a.
The output enable signal OE(that gate control signal CONT1 may further include the time cycle of restriction enabling voltage Von is not shown).
The horizontal synchronization commencing signal STH(of beginning that the data that data controlling signal CONT2 comprises each row determining pixel PX transmit is not shown), data voltage is applied to a plurality of data lines D 1-D mon Load Signal LOAD(not shown) and data clock signal HCLK(not shown).It is not shown relative to the reverse signal RVS(of the polarity of utility voltage Vcom that data controlling signal CONT2 may further include reversal data voltage).
Respond the data controlling signal CONT2 from signal controller 600, data driver 500 receives the data image signal DAT of each row of pixel PX from signal controller 600, data image signal DAT is converted to the module data voltage selected from grayscale voltage, and module data voltage is applied to a plurality of data lines D 1-D mon.
Gate driver 400 responds the gate control signal CONT1 from signal controller 600, enabling voltage Von is applied to the current line of a line, such as, on the corresponding normal door line of the i-th row, thus the associated switching elements Q that conducting is connected with the respective normal door line of the i-th row.Therefore, analog data voltage is applied to data line D 1-D mon, be then supplied to each pixel PX of the i-th row by actuating switch transistor Q, to be charged to the liquid crystal capacitor Clc in the pixel PX of the i-th row and holding capacitor Cst by analog data voltage.
In an exemplary embodiment, extra gate line G dbe not connected with on-off element Q.
The difference being applied to analog data voltage on each pixel PX and utility voltage Vcom appears as the voltage difference at the liquid crystal capacitor Clc two ends of pixel PX, is called pixel voltage.In liquid crystal capacitor Clc, liquid crystal molecule is with the amplitude orientation of pixel voltage, and the orientation of liquid crystal molecule determines the polarity through the light of liquid crystal layer 3.Polarizer (not shown) converts Light polarizing degree to light transmission, so that given pixel PX has and the analog data voltage be applied on pixel PX, such as, and the brightness that the level of pixel voltage is directly proportional.
After the horizontal cycle (" 1H ") of one-period equaling horizontal-drive signal Hsync and data enable signal DE, data voltage is applied to (i+1) OK by data driver 500, such as, on the pixel PX gone subsequently, and pass gate signal Voff is applied to the i-th row and is applied on (i+1) row of pixel by enabling signal Von by gate driver 400.Consequently, the on-off element Q of the i-th row turns off, and makes the pixel electrode 191 of the i-th row floating.
Storage signal generator 700 is according to storage control signal CONT3 and be applied to (i+1) door line G i+1on the change in voltage of gate signal, change and be applied to the i-th storage electrode line S ion the voltage level of storage signal.Therefore, the voltage of the pixel electrode 191 be connected with one end of holding capacitor Cst is with the storage electrode line S be connected with the other end of holding capacitor Cst ichange in voltage and become.
By repeating process as above to all pixel columns subsequently, LCD will demonstrate the image of single frames.When frame when subsequently starts, the reverse signal RVS(controlling to be applied on data driver 500 is not shown) so that the polarity of the analog data voltage that reverses.In other words, be identical to the polarity of the data voltage of framing, but relative to the reversal of poles of the data voltage of former frame, claim this to be " frame reversion ".
In addition, the polarity being applied to the data voltage on the pixel PX of a line may be similar to identical, and the polarity being applied to front adjacent lines and the data voltage on the pixel PX of rear adjacent lines is reversion (such as, row reversion).
In the one exemplary embodiment of the present invention of conducting frame reversion and/or row reversion, the polarity being applied to all data voltages on the pixel PX of a line is positive and negative alternately with each consecutive line.Further, when the data voltage by positive polarity charges to pixel electrode 191, many storage electrode line S are applied to 1-S 2non storage signal change over high level voltage from low level voltage.On the contrary, when the data voltage by negative polarity charges to pixel electrode 191, storage signal changes over low level voltage from high level voltage.Consequently, if charged to pixel electrode 191 by the positive data voltage of positive polarity, then pixel electrode 191 voltage raise, and if by negative data voltage, pixel electrode 191 is charged, then the voltage drop of pixel electrode 191.Consequently, the scope of the voltage level of pixel electrode 191 increases, thus is greater than the scope of the grayscale voltage as data voltage basis.Consequently, the scope that need not increase grayscale voltage just can increase brightness range.
First storage signal generative circuit 700a and the second storage signal generative circuit 700b comprises and many storage electrode line S 1-S 2nmultiple signal generating circuit 710(Fig. 3 connected).The example of signal generating circuit 710 is described in further detail referring now to Fig. 3 and 4.
Fig. 3 is the schematic circuit of the signal generating circuit according to the present invention's one exemplary embodiment, and Fig. 4 is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Fig. 3.
With reference to Fig. 3, signal generating circuit 710 comprises input end IP and output terminal OP.In the i-th signal generating circuit 710, such as, input end IP and supply (i+1) gate signal g i+1(i+1) door line G of (hereinafter referred to as " input signal ") i+1connect (Fig. 1), and output terminal OP and output the i-th storage signal V slthe i-th storage electrode line S iconnect.Similarly, in (i+1) signal generating circuit 710, such as, input end IP and supply (i+2) gate signal g i+2(not shown) is as (i+2) door line G of input signal i+2connect, and output terminal OP and output (i+1) storage signal V sl+1(i+1) storage electrode line S of (not shown) i+1connect.
By from signal controller 600(Fig. 1) the first clock signal C K1, the second clock signal CK1B of storage control signal CONT3 and the 3rd clock signal C K2 be supplied to signal generating circuit 710, and be supplied to signal generating circuit 710 by from the high pressure AVDD of signal controller 600 or external unit (not shown) and low pressure AVSS.
As shown in Figure 4, the cycle of the first clock signal C K1, second clock signal CK1B and the 3rd clock signal C K2 can be about 2H, and their dutycycle about 50%, but can be not limited to this.First clock signal C K1 and second clock signal CK1B has about 180 0difference and mutually anti-phase.On the contrary, second clock signal CK1B and the 3rd clock signal C K2 has practically identical phase place.In addition, as shown in Figure 4, each each subsequently in frame each phase place of the first clock signal C K1, second clock signal CK1B and the 3rd clock signal C K2 be anti-phase.
First clock signal C K1 and second clock signal CK1B can have the first high level voltage Vh1 of such as approximately 15V, and the first low level voltage Vl1 of such as about 0V.3rd clock signal C K2 can have the second high level voltage Vh2 of such as approximately 5V, and the second low level voltage Vl2 of such as about 0V.High pressure AVDD can be such as about 5V, and can approximate greatly the second high level voltage Vh2 of the 3rd clock signal C K2.Low pressure AVSS can be such as about 0V, and can approximate greatly the second low level voltage Vl2 of the 3rd clock signal C K2.
Signal generating circuit 710 comprises the first to the five transistor Tr1-Tr5 and the first capacitor C1 and the second capacitor C2 that contain control end, input end and output terminal respectively.
The control end of the first transistor Tr1 is connected with input end IP, and the input end of transistor Tr1 is connected with the 3rd clock signal C K2, and the output terminal of transistor Tr1 is connected with output terminal OP.
Transistor seconds Tr2 is connected with input end IP with the control end of third transistor Tr3, and transistor seconds Tr2 is connected with the first clock signal C K1 and second clock signal CK1B respectively with the input end of third transistor Tr3.
4th transistor Tr4 is connected with the output terminal of transistor seconds Tr2 and third transistor Tr3 respectively with the control end of the 5th transistor Tr5, and the 4th transistor Tr4 is connected with low pressure AVSS and high pressure AVDD respectively with the input end of the 5th transistor Tr5.
First capacitor C1 and the second capacitor C2 be connected to the 4th transistor Tr4 and the 5th transistor Tr5 control end and between low pressure AVSS and high pressure AVDD.
In an exemplary embodiment, the first to the five transistor Tr1-Tr5 is formed by amorphous silicon (" a-Si ") or polysilicon (" p-Si ") TFT respectively.
The operation of signal generating circuit 710 is described in further detail now.
Referring again to Fig. 4, in general, enabling voltage Von such as approximately 1H(but be not limited to this) predetermined overlapping time period in be applied to two adjacent door lines each on.Consequently, in about 1H, utilize the data voltage be applied in the pixel of previous row, in all the other 1H, then utilize data voltage to all pixel PX chargings of given row to show image.
Now, the i-th signal generating circuit 710 is further described with reference to Fig. 3 and 4.
When input signal (such as, is applied to (i+1) door line G i+1on gate signal g i+1) when changing over enabling voltage Von, first, second, and third transistor Tr1-Tr3 conducting respectively.3rd clock signal C K2 is sent to output terminal OP by the first transistor Tr1 of conducting.Consequently, the i-th storage signal V sibe on the second low level voltage Vl2 of the 3rd clock signal C K2.First clock signal C K1 is sent to the control end of the 4th transistor Tr4 by the transistor seconds Tr2 of conducting, and second clock signal CK1B is sent to the control end of the 5th transistor Tr5 by the third transistor Tr3 of conducting.
Because the first and second clock signal C K1 and CK1B exist anti-phase relation, the 4th transistor Tr4 and the 5th transistor Tr5 was reverse biased in preset time.Such as, when the 4th transistor Tr4 conducting, the 5th transistor Tr5 turns off, on the contrary, when the 4th transistor Tr4 turns off, and the 5th transistor Tr5 conducting.Further, when the 4th transistor Tr4 conducting and the 5th transistor Tr5 turn off, low pressure AVSS is sent to output terminal OP, and when the 4th transistor Tr4 shutoff and the 5th transistor Tr5 conducting, high pressure AVDD is sent to output terminal OP.
As shown in Figure 4, gate signal g i+1be on enabling voltage Von in the interval of such as about 2H.Further, the period 1 of about 1H represents with period 1 T1, and approximately represents by cycle T 2 subsequently the second round of 1H.
First clock signal C K1 is on the first high level voltage Vh1 in period 1 T1, and second clock signal and the 3rd clock signal C K1B and CK2 are on the first and second low level voltage Vl1 and vl2 respectively, and low pressure AVSS is supplied to the output terminal OP of the second low level voltage Vl2 being passed to the 3rd clock signal C K2 by transistor Tr1.Consequently, storage signal V simaintenance amplitude equals the low level storage signal voltage V-of the amplitude of the second low level voltage Vl2 and low pressure AVSS.During period 1 T1, voltage difference between the first high level voltage Vh1 and low pressure AVSS of the first clock signal C K1 is charged to capacitor C1, and the voltage difference between the first low level voltage Vl1 of second clock signal CK1B and high pressure AVDD is charged to capacitor C2.
During cycle T 2, first clock signal C K1 remains on the first low level voltage Vl1, and second and the 3rd clock signal C K1B and CK2 remain on the first and second high level voltage Vh1 and Vh2 respectively, thus the 5th transistor Tr5 conducting and the 4th transistor Tr4 turns off.
Consequently, the second high level voltage Vh2 of the 3rd clock signal C K2 transmitted by the first transistor Tr1 by conducting is supplied to output terminal OP, and storage signal V sistate change over from low level storage signal voltage V-the high level storage signal voltage V+ that amplitude equals the amplitude of the second high level voltage Vh2.In addition, amplitude equaled the amplitude of high level storage signal voltage V+, be supplied to output terminal OP by the high pressure AVDD of conducting the 5th transistor Tr5 applying.
The voltage difference be similar between the first low level voltage Vl1 and low pressure AVSS of the first clock signal C K1 due to the voltage being charged to capacitor C1 is identical, when the first low level voltage Vl1 and the low pressure AVSS of the first clock signal C K1 become approximate identical time, capacitor C1 discharges.Because the voltage that is charged to capacitor C2 is based on the voltage difference between the first high level voltage Vh1 of second clock signal CK1B and high pressure AVDD, when as mentioned above, when first high level voltage Vh1 and high pressure AVDD is mutually different, the voltage being charged to capacitor C2 is not equal to 0V, wherein, the first high level voltage Vh1 of second clock signal CK1B is about 15V and high pressure AVDD is about 5V.Therefore, the voltage being charged to capacitor C2 is about 10V.
When as shown in the figure, gate signal g i+1the i-th+1 grade after have passed through cycle T 2 from enabling voltage Von change over close gate voltage Voff time, first turns off respectively to third transistor Tr1-Tr3.Consequently, the electrical connection between the first transistor Tr1 with output terminal OP separates, and the control end of the 4th and the 5th transistor Tr4 and Tr5 also separates respectively with the electrical connection between output terminal OP.
Due to uncharged to capacitor C1, the 4th transistor Tr4 remains on off state.But the voltage between the first high level voltage Vh1 of second clock signal CK1B and high pressure AVDD has been charged to capacitor C2.Therefore, when the charging voltage of capacitor C2 is greater than the starting voltage of the 5th transistor Tr5, transistor Tr5 remains on conducting state.Consequently, using high pressure AVDD as storage signal V sibe supplied to output terminal OP.So, storage signal V sikeep high level storage signal voltage V+.
Then, the operation of (i+1) signal generating circuit 710 is described in further detail with reference to Fig. 4.
When having (i+2) gate signal g of enabling voltage Von i+2be applied to (i+1) signal generating circuit 710(not shown) upper time, (i+1) signal generating circuit 710 is started working.
As shown in Figure 4, as (i+2) gate signal g i+2when switching to enabling voltage Von, the state of first, second, and third clock signal C K1, CK1B and CK2 is reversed respectively, and (i+1) gate signal g i+1be on enabling voltage Von.
(i+2) gate signal g i+2the operation of previous enabling voltage cycle T1 approximate with (i+1) gate signal g i+1the operation of a rear enabling voltage cycle T2 identical, cause the first, the 3rd and the 5th transistor Tr1, Tr3 and Tr5 conducting respectively.So the second high level voltage Vh2 of the 3rd clock signal C K2 and high pressure AVDD is applied on output terminal OP.Consequently, storage signal V si+1be on high level storage signal voltage V+.
Similarly, (i+2) gate signal g i+2the operation of enabling voltage cycle T2 approximate with (i+1) gate signal g i+ 1the operation of previous enabling voltage cycle T1 identical, cause first, second and the 4th transistor Tr1, Tr2 and Tr4 conducting respectively.So the second low level voltage Vl2 and low pressure AVSS of the 3rd clock signal C K2 is applied on output terminal OP.Consequently, storage signal V si+1low level storage signal voltage V-is changed over from high level storage signal voltage V+.
As mentioned above, the first transistor Tr1 can apply the 3rd clock signal C K2 as storage signal while input signal keeps enabling voltage Von, and when being separated with the output terminal of the first transistor Tr1 by output terminal OP by pass gate voltage Voff, utilize the first and second capacitor C1 and C2 to make the second to the five transistor Tr2-Tr5 remain on the state of storage signal respectively until next frame.Further, storage signal can be applied in respective stored electrode wires by the first transistor Tr1, and the second to the five transistor Tr2-Tr5 keeps storage signal respectively.
In an exemplary embodiment, the size of the first transistor Tr1 is more much bigger than the size of the second to the five transistor Tr2-Tr5 respectively.As provided in equation 1, pixel electrode voltage Vp responds storage signal V schange in voltage and become.
Vp=V d+/-Δ=V d+/-C st/ (C st+ C lc) * [(V+)-(V-)] (equation 1)
Wherein: V dit is data voltage; Δ is voltage variety; C lcand C stthe electric capacity of representative storage and liquid crystal capacitor respectively; V+ represents storage signal V shigh level storage signal voltage; And V-represents storage signal V slow level storage signal voltage.
By by storage signal V svoltage variety Δ add data voltage V din or from data voltage V din deduct storage signal V svoltage variety Δ, when utilizing the data voltage of positive polarity to charge to pixel, pixel electrode voltage Vp adds voltage variety Δ, and on the contrary, when utilizing the data voltage of negative polarity to charge to pixel, pixel electrode voltage Vp reduces voltage variety Δ.Consequently, the voltage variety Δ of pixel voltage, by making pixel electrode voltage Vp increase or reducing, makes pixel voltage become to be greater than the scope of grayscale voltage, causes the scope of representative brightness also to increase.
Further, as mentioned above, because utility voltage is fixed in predetermined value, compared with the LCD of the prior art replaced between high level and low value with utility voltage, power consumption is significantly reduced.
Therefore, according to one exemplary embodiment of the present invention, utility voltage is fixed in predetermined value, and the storage signal of level period change is applied on storage electrode line, causes the scope of pixel electrode voltage to increase.Therefore, the scope representing the voltage of grayscale voltage increases, thus the picture quality of LCD is improved.
Further, as mentioned above, power consumption is reduced because utility voltage is constant.
Hereinafter, another one exemplary embodiment of the present invention is further described with reference to Fig. 5-8B.
Fig. 5 is the calcspar of the liquid crystal display according to another one exemplary embodiment of the present invention, and Fig. 6 is the schematic circuit of the signal generating circuit of storage signal generative circuit according to the one exemplary embodiment of the present invention in Fig. 5.Fig. 7 A and 7B is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Fig. 6.More particularly, the example that Fig. 7 A is the direction of scanning of gate driver when being forward direction, and the example when direction of scanning that Fig. 7 B is gate driver is backward direction.Fig. 8 A and 8B is the signal timing diagram of the signal generating circuit according to the present invention's alternative one exemplary embodiment.More particularly, figure BA is the example of signal sequence when to illustrate the direction of scanning of gate driver be forward direction, and the example of signal sequence when Fig. 8 B be the direction of scanning that illustrates gate driver is backward direction.
Except the different piece described in further detail below, the LCD of the one exemplary embodiment of the present invention according to such as Fig. 5 to 8B is similar to such as the LCD shown in Fig. 1 to 3 is identical.Therefore, perform the element of same or similar operation with identical labelled notation, and any repeated description of will omit them below.
Liquid crystal panel assembly 300a, gate driver 401, data driver 500, the grayscale voltage generator 800 be connected with data driver 500, storage signal generator 701 and signal controller 601 is comprised according to the liquid crystal display of one exemplary embodiment of the present invention as shown in Figure 5.
But different from one exemplary embodiment of the present invention as shown in Figure 1, gate driver 401 is many normal door line G 1-G 2nthe bidirectional gate driver that becomes with the selection signal (not shown) from external unit (not shown) of direction of scanning.More particularly, according to selecting the state of signal, gate driver 401 is along such as from the 1st normal door line G 1to last normal door line G 2nforward direction, or on the contrary, along such as from last normal door line G 2nto the 1st normal door line G 1backward direction, transmit enabling voltage Von successively.In the bi-directional drive of gate driver 401, liquid crystal display may further include selector switch (not shown), selector switch exports to have and such as selects and the selection signal of the state of change with the user being input to signal controller 601, and, except like that as described above in greater detail, the first and second scanning commencing signal STV1 and STV2(be applied to respectively on the first and second gate drive circuit 401a and 401b are not shown) outside, signal controller 601 can also for gate control signal CONT1a, export additional third and fourth scanning commencing signal STV3 and STV4(respectively not shown).Therefore, when gate driver 410 scans along forward direction, first and second scanning commencing signal STV1 and STV2 can be applied on the first and second gate drive circuit 401a and 401b respectively, and when gate driver 410 is along backward scanning direction, the third and fourth scanning commencing signal STV3 and STV4 can be applied on the first and second gate drive circuit 401a and 401b respectively.
Comprise according to each of the first and second storage signal generative circuit 701a and 701b of the storage signal generator 701 of the liquid crystal display of one exemplary embodiment and storage signal is sent to many storage electrode line S 1-S 2nmultiple signal generating circuit 710a.As shown in Figure 6, each signal generating circuit 710a of multiple signal generating circuit 710a is similar with signal generating circuit 710 as shown in Figure 3, such as, signal generating circuit 710a comprises output terminal OP, the first to the five transistor Tr1-Tr5 and the first capacitor C1 and the second capacitor C2.
But the signal generating circuit 710a of the one exemplary embodiment in Fig. 6 comprises first input end IP11 and the second input end IP12 and first direction control end IP13 and second direction control end IP14 further.In the i-th signal generating circuit 710a, first input end IP11 and supply (i+1) gate signal g i+1(i+1) door line G of (hereinafter referred to as " the first input signal ") i+1connect, and the second input end IP12 and supply (i-1) gate signal g i-1(i-1) door line G of (hereinafter referred to as " the second input signal ") i-1connect.Similarly, in (i+1) signal generating circuit 710a, first input end IP11 and supply (i+2) gate signal g i+2as (i+2) door line G of the first input signal i+2connect, and the second input end IP12 and supply the i-th gate signal g ias i-th line G of the second input signal iconnect.
The same with signal generating circuit 710 as shown in Figure 3, first, second, and third clock signal C K1, CK1B and CK2 of the storage control signal CONT3a from signal controller 601 are supplied to signal generating circuit 710a respectively, and are supplied to signal generating circuit 710a by from the high pressure AVDD of signal controller 601 or external unit (not shown) and low pressure AVSS.Respectively by first direction control end IP13 and second direction control end IP14, further first direction signal DIR or DIRa of the storage control signal CONT3a from signal controller 610 and second direction signal DIRB or DIRBa is supplied to signal generating circuit 710a.
Signal generating circuit 710a comprises each the 6th transistor Tr6 containing control end, input end and output terminal and the 7th transistor Tr7 further.
As shown in Figure 6, the control end of the 6th transistor Tr6 is connected with first direction control end IP13, the input end of the 6th transistor Tr6 is connected with first input end IP11, is connected respectively with the output terminal of the 6th transistor Tr6 with the control end of first to third transistor Tr1-Tr3.
And, the control end of the 7th transistor Tr7 is connected with second direction control end IP14, the input end of the 7th transistor Tr7 is connected with the second input end IP12, is connected respectively with the output terminal of the 7th transistor Tr7 with the control end of first to third transistor Tr1-Tr3.
Except extra gate line G doutside, liquid crystal display comprises the second extra gate line G further da.Second extra gate line G dabe connected with one end of the second gate drive circuit 401b, to transfer gate signal g 1afterwards enabling voltage Von is sent to the first storage signal generative circuit 701a.
In an exemplary embodiment, extra gate line G dawith extra gate line G ddifferent on-off element Q connects.
The example of operation of signal generating circuit is described in further detail with reference to Fig. 7 A and 7B.
As shown in figs. 7 a-b, the first and second direction signal DIR and DIRB be applied to respectively on the first and second direction controlling end IP13 and IP14 keep third high level voltage Vh3 or the 3rd low level voltage Vl3 respectively in a frame, and the first and second direction signal DIR and DIRB have phases opposite respectively.More particularly, when first direction signal DIR has third high level voltage Vh3, second direction signal DIRB has the 3rd low level voltage Vl3, and when first direction signal DIR has the 3rd low level voltage Vl3, second direction signal DIRB has third high level voltage Vh3.Further, the third high level voltage Vh3 of the first and second direction signal DIR and DIRB has the amplitude of conducting the 6th and the 7th transistor Tr6 and Tr7, and the amplitude of third high level voltage Vh3 can be such as about 15V, but is not limited to this.The 3rd low level voltage Vl3 of the first and second direction signal DIR and DIRB has the amplitude of shutoff the 6th and the 7th transistor Tr6 and Tr7, and the amplitude of the 3rd low level voltage Vl3 can be such as about-10V, but is not limited to this.
Therefore, 6th and the 7th transistor Tr6 and Tr7 has reciprocal biased in preset time, thus when the 6th transistor Tr6 is in conducting state, the 7th transistor Tr7 is in off state, and when the 6th transistor Tr6 is in off state, the 7th transistor Tr7 is in conducting state.
In alternative one exemplary embodiment of the present invention, such as, according to selection signal, the control signal of the direction of scanning of control gate driver 40 maybe can be utilized to export the first and second direction signal DIR and DIRB, but be not limited to this.
The situation being now forward directions for the direction of scanning of gate driver 401 describes in further detail the operation of signal generating circuit 710a.
Be in third high level voltage Vh3 on reference to Fig. 6 and 7A, first direction signal DIR and input in first direction control end IP13, and second direction signal DIRB to be on the 3rd low level voltage Vl3 in input second direction control end IP14.
Therefore, the 6th transistor Tr6 conducting and the 7th transistor Tr7 turn off, thus according to the first input signal be applied on first input end IP11, such as, gate signal g i+1operation signal generative circuit 710a.More particularly, when as the i-th signal generating circuit 710a during operation signal generative circuit 710a, by being applied to (i+1) door line G i+1(Fig. 1) the gate signal g on i+1enabling voltage Von operate the i-th signal generating circuit 710a.Therefore, as described in above with reference to Fig. 3 and 4, export the storage signal V with predetermined level by the operation of the first to the five transistor Tr1-Tr5 and the first and second capacitor C1 and C2 si.
Similarly, when the direction of scanning of gate driver 401 is backward directions, as shown in Figure 7 B, first direction signal DIR is on the 3rd low level voltage Vl3, and second direction signal DIRB presents third high level voltage Vh3.
Therefore, the 6th transistor Tr6 turns off and the 7th transistor Tr7 conducting, thus by being applied to the second input signal on the second input end IP12, such as, gate signal g i-1operation signal generative circuit 710a.More particularly, when as the i-th-1 signal generating circuit 710a during operation signal generative circuit 710a, by being applied to (i-1) door line G i-1(Fig. 1) the gate signal g on i-1enabling voltage Von operate the i-th signal generating circuit 710a.Therefore, as described in above with reference to Fig. 3 and 4, export the storage signal V with predetermined level by the operation of the first to the five transistor Tr1-Tr5 and the first and second capacitor C1 and C2 si.
Replace and directly input signal be supplied to signal generating circuit 710(Fig. 3 by input end IP) distinguish conducting first to third transistor Tr1-Tr3, as shown in the figure, when direction of scanning is forward direction, by the 6th transistor T6, gate signal is supplied to signal generating circuit 710a, as the input signal be applied to respectively on the control end of first to third transistor Tr1-Tr3, and when direction of scanning is backward direction, by the 7th transistor T7, gate signal is supplied to signal generating circuit 710a, as the input signal be applied to respectively on the control end of first to third transistor Tr1-Tr3.The first to the five transistor Tr1-Tr5 is identical with those of the signal generating circuit 710 described in further detail above with reference to Fig. 3 respectively with the operation of the first and second capacitor C1 with C2.
The operation of the signal generating circuit 710a according to the alternative one exemplary embodiment of the present invention is described in further detail referring now to Fig. 8 A and 8B.
As shown in figs. 8 a and 8b, first direction signal DIRa and second direction signal DIRBa is applied on the first and second direction controlling end IP13 and IP14 respectively, and has third high level voltage Vh3 and the 3rd low level voltage Vl3 respectively.Further, third high level voltage Vh3 and the 3rd low level voltage Vl3 remains unchanged each in about 1H, and their dutycycle can be about 50%.More particularly, the every approximately 1H of first direction signal DIRa and second direction signal DIRBa replaces between third high level voltage Vh3 and the 3rd low level voltage Vl3.Further, first direction signal DIRa and second direction signal DIRBa has about 180 0difference and mutually anti-phase.
As mentioned above, the third high level voltage Vh3 of first direction signal DIRa and second direction signal DIRBa can be such as about 15V, and their the 3rd low level voltage Vl3 can be such as about-10V.
For every row, respectively by first direction signal DIRa and second direction signal DIRBa alternate supplies to the first direction control end IP13 of signal generating circuit 710a and second direction control end IP14.More particularly, with odd number storage electrode line S 1, S 3..., S 2n-1in the signal generating circuit 710a connected, first direction signal DIRa is supplied to first direction control end IP13, and second direction signal DIRBa is supplied to second direction control end IP14.On the contrary, with even number storage electrode line S 2, S 4..., S 2nin the signal generating circuit 710a connected, second direction signal DIRBa is supplied to first direction control end IP13, and first direction signal DIRa is supplied to second direction control end IP14.
The present direction of scanning for gate driver 401 is the situation of forward direction, and the operation of signal generating circuit 710a is described in further detail with reference to Fig. 6 and 8B.
Such as, at odd number signal generating circuit 710a, in the i-th signal generating circuit 710a, when using (i+1) the gate signal g as the first input signal i+1enabling voltage Von be supplied to first input end IP11, and using (i-1) the gate signal g as the second input signal i-1pass gate voltage Voff when being supplied to the second input end IP12, using first direction signal DIRa as first direction signal provision to first direction control end IP13, and using second direction signal DIRBa as second direction signal provision to second direction control end IP14.
At gate signal g i+1enabling voltage Von period 1 T1 in, first direction signal DIRa is on the 3rd low level voltage Vl3 and second direction signal DIRBa is on third high level voltage Vh3, thus the 6th transistor Tr6 turns off, and the 7th transistor Tr7 conducting.Further, the second input signal closes gate voltage Voff, and therefore, first turns off respectively to third transistor Tr1-Tr3, thus storage signal V siremain on as shown in Figure 8 A, voltage status before as such as low level storage signal voltage V-.
Such as, after about 1H, at gate signal g i+1enabling voltage Von cycle T 2 in, first direction signal DIRa changes over third high level voltage Vh3 from the 3rd low level voltage Vl3, and second direction signal DIRBa changes over the 3rd low level voltage Vl3 from third high level voltage Vh3.
Therefore, the 6th transistor Tr6 is at gate signal g i+1enabling voltage Von cycle T 2 in conducting, and enabling voltage Von is sent to first to the control end of third transistor Tr1-Tr3, conducting first is to third transistor Tr1-Tr3.
As above with reference to described in Fig. 3 and 4, the first clock signal C K1 is on the first low level voltage Vl1 in cycle T 2, and second and the 3rd clock signal C K1B and CK2 be in respectively on the first high level voltage Vh1 and Vh2.Therefore, the second high level voltage Vh2 of the 3rd clock signal C K2 and high pressure AVDD is sent to output terminal OP.Therefore, storage signal V sihigh level storage signal voltage V+ is changed over from low level storage signal voltage V-, and the second capacitor C2 that charges.
When first direction signal DIRa changes over the 3rd low level voltage Vl3 after have passed through cycle T 2, the 6th transistor Tr6 turns off.But transistor Tr5 is remained in conducting state by the voltage being charged to the second capacitor C2, thus still high pressure AVDD is sent to output terminal OP, causes storage signal V sikeep high level storage signal voltage V+.
Then, even number signal generating circuit 710a is described in further detail, such as, the operation of (i+1) signal generating circuit 710a.
Still with reference to Fig. 6 and 8A, in (i+1) signal generating circuit 710a, when using (i+2) the gate signal g as the first input signal i+2enabling voltage Von be supplied to first input end IP11, and using the i-th gate signal g as the second input signal ipass gate voltage Voff when being supplied to the second input end IP12, using second direction signal DIRBa as first direction signal provision to first direction control end IP13, and using first direction signal DIRa as second direction signal provision to second direction control end IP14.
Due at gate signal g i+1enabling voltage Von period 1 T1 in, first direction signal DIRBa is on the 3rd low level voltage Vl3 and second direction signal DIRa is on third high level voltage Vh3, and the 6th transistor Tr6 turns off, and the 7th transistor Tr7 conducting.Second input signal closes gate voltage Voff, and first turns off respectively to third transistor Tr1-Tr3, thus storage signal V siremain on the front voltage status as such as high level storage signal voltage V+.
Such as, after about 1H, at gate signal g i+2enabling voltage Von cycle T 2 in, first direction signal DIRBa changes over third high level voltage Vh3 from the 3rd low level voltage Vl3, and second direction signal DIRa changes over the 3rd low level voltage Vl3 from third high level voltage Vh3.
Therefore, the 6th transistor Tr6 is at gate signal g i+2enabling voltage Von cycle T 2 in conducting, and enabling voltage Von is sent to first to the control end of third transistor Tr1-Tr3, conducting first is to third transistor Tr1-Tr3.
As above with reference to described in Fig. 3 and 4, first clock signal C K1 is on the first high level voltage Vh1, with second and the 3rd clock signal C K1B and CK2 be in respectively on the first low level voltage Vl1 and Vl2, thus the low level voltage Vl2 of the 3rd clock signal C K2 and low pressure AVSS is sent to output terminal OP.Therefore, storage signal V si+1low level storage signal voltage V-is changed over from high level storage signal voltage V+, and the first capacitor C1 that charges.
When first direction signal DIRBa changes over the 3rd low level voltage Vl3 after have passed through cycle T 2, the 6th transistor Tr6 turns off.But the 4th transistor Tr4 is remained in conducting state by the voltage being charged to the first capacitor C1, thus still low pressure AVSS is sent to output terminal OP, and storage signal V si+1remain on low level storage signal voltage V-.
Hereinafter, Fig. 8 B being backward directions with reference to the direction of scanning of gate driver 401 describes in further detail the operation of signal generating circuit 710a.In this case, the waveform of direction signal DIRa and DIRBa is contrary with the situation above with reference to the forward direction described in Fig. 8 A.
With reference to Fig. 6 and 8B, being applied to the cycle 1H of enabling voltage Von of the respective doors signal on the second input end IP12 as the second input signal, such as, be connected in the cycle T subsequently 2 of above-mentioned cycle T 2, transistor Tr7 conducting, the first to third transistor Tr1-Tr3 also conducting respectively.More particularly, according to state of operation the first to the five transistor Tr1-Tr5 and first and second capacitor C1 and C2 of the first to the three clock signal C K1, CK1B and CK2, storage signal is sent to respective stored electrode wires.The operation of the first to the five transistor Tr1-Tr5 and the first and second capacitor C1 and C2 approximate with as mentioned above, the direction of scanning of gate driver is that the situation of forward direction is identical, therefore omits description of them here.
As mentioned above, in an exemplary embodiment of the invention, the first and second direction signal DIRa and DIRBa are applied on the first and second direction controlling end IP13 and IP14 respectively.Further, the every 1H of the first and second direction signal DIRa and DIRBa replaces between third high level voltage Vh3 and the 3rd low level voltage Vl3.Therefore, the operating characteristic of transistor can not change because of the long-time applying of direction signal DIRa and DIRBa and the component degradation caused thus.
Except polycrystal film transistor, the signal be presented in the sequential chart of Fig. 8 A and 8B also can be applied to the liquid crystal display containing amorphous thin film transistor.
In an exemplary embodiment, gate driver 401 is bidirectional gate drivers, and one of the first to the four scanning commencing signal STV1 and STV4 can be applied to the signal generating circuit 710a of supply gate signal according to direction of scanning.
Hereinafter, with reference to Fig. 9-13B, the liquid crystal display according to the alternative one exemplary embodiment of the present invention is described in further detail.
Fig. 9 is the calcspar of the liquid crystal display according to another one exemplary embodiment of the present invention, Figure 10 is the schematic circuit of the signal generating circuit according to the one exemplary embodiment of the present invention in Fig. 9, and Figure 11 is the plane figure of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 10.Figure 12 is the signal timing diagram illustrating the Gating clock signal be applied to according to an embodiment of the invention on gate driver and the relation being applied to the store clock signal on storage signal generator.Figure 13 A and 13B is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 10, wherein, the example of Figure 13 A to be the direction of scanning of gate driver be signal sequence of forward direction, and the direction of scanning that Figure 13 B is gate driver is the example of the signal sequence in backward direction.
Except the different piece described in further detail below, the LCD of the one exemplary embodiment of the present invention according to such as Fig. 9-13B is similar to such as the LCD shown in Fig. 1 to 6 is identical.Therefore, represent the element performing same or similar operation with identical label, and any repeated description of will omit them below.
Liquid crystal panel assembly 300b, gate driver 402, data driver 500, the grayscale voltage generator 800 be connected with data driver 500, storage signal generator 702 and signal controller 602 is comprised with reference to Fig. 9, LCD.
The same with the LCD be described in more detail above with as shown in Figure 5, gate driver 402 is bidirectional gate drivers.
First and second storage signal generative circuit 702a and 702b of storage signal generator 702 can comprise and storage electrode line S respectively 1-S 2nthe multiple signal generating circuit 710b connected, and each signal generating circuit 710b is similar with signal generating circuit 710a as shown in Figure 6.
As shown in Figure 10, signal generating circuit 710b comprises output terminal OP, the first to the five transistor Tr1-Tr5 and the first and second capacitor C1 and C2.
Signal generating circuit 710b comprises input end IP21 and control end OP22 further.In the i-th signal generating circuit 710b, such as, input end IP21 and supply the i-th gate signal g ias i-th line G of the first input signal iconnect, similarly, in (i+1) signal generating circuit 710b, input end IP21 and supply (i+1) gate signal g i+1as (i+1) door line G of the first input signal i+1connect.
First, second, and third clock signal C K1, CK1B and CK2 of the storage control signal CONT3 from signal controller 602 are supplied to signal generating circuit 710b respectively, and are supplied to signal generating circuit 710b by from the high pressure AVDD of signal controller 602 or external unit (not shown) and low pressure AVSS.
By control end IP22 further by multiple store clock signal CLK_L(of the storage control signal CONT3 from signal controller 602 such as, as shown in Figure 10), a store clock signal provision of CLK_R, CLKB_L and CLKB_R is to signal generating circuit 710b.
As shown in figs. 9 and 11, the signal generating circuit 710b of the first storage signal generative circuit 702a is positioned at the left side of liquid crystal panel assembly 300b and generates even number storage signal V s2, V s4..., V s2n, and the store clock signal CLK_L of multiple store clock signal CLK_L, CLK_R, CLKB_L and CLKB_R of being applied in the left side from liquid crystal panel assembly 300b and CLKB_L alternate supplies are to signal generating circuit 710b.The signal generating circuit 710b of the second storage signal generative circuit 702b is positioned at the relative right side of liquid crystal panel assembly 300b and generates odd number storage signal V s1, V s3..., V s2n-1, and the store clock signal CLKB_R of multiple store clock signal CLK_L, CLK_R, CLKB_L and CLKB_R of being applied on the right side from liquid crystal panel assembly 300b and CLK_L alternate supplies are to signal generating circuit 710b.
In alternative one exemplary embodiment of the present invention, the operative relationship of the first and second positions of storage signal generative circuit 702a and 702b on liquid crystal panel assembly 300b, annexation between the first and second storage signal generative circuit 702a and 702b and storage electrode line and the first and second storage signal generative circuit 702a and 702b and multiple store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R can be changed.
And, in alternative one exemplary embodiment, multiple store clock signal CLK_L, CLKB_L, CLK_R can be relevant with the gate control signal CONT1 generating gate signal with CLKB_R, and can generate according to the Gating clock signal be applied on gate drive circuit 402a and 402b.
Show in fig. 12 according to the Gating clock signal of one exemplary embodiment of the present invention and the example of store clock signal.
Figure 12 shows when the direction of scanning of gate driver 402 is forward directions, generates i-th respectively, (i+1), (i+2) and (i+3) gate signal g when Gating clock signal GCK_L, GCK_R, GCKB_L and GCKB_R are applied to i, g i+1, g i+2and g i+3the first and second gate drive circuit 402a and 402b time, multiple store clock signal CLK_L, CLKB_R, CLKB_L and CLK_R are applied to and generate i-th respectively, (i+1), (i+2) and (i+3) storage signal S i, S i+1, S i+2and S i+3the first and second storage signal generative circuit 702a and 702b on store clock signal CLK_L, CLKB_R, CLKB_L and CLK_R.
But when the direction of scanning of gate driver 402 is backward directions, Gating clock signal GCK_L, GCK_R, GCKB_L and GCKB_R in Figure 12 generate (i+3), (i+2), (i+1) and the i-th gate signal g respectively i+3, g i+2, g i+1and g isignal, and store clock signal CLK_L, CLKB_R, CLKB_L and CLK_R can be applied on the first and second storage signal generative circuit 702a and 702b, generate (i+3), (i+2), (i+1) and the i-th storage signal S respectively i+3, S i+2, S i+1and S i.
The pulse width of store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R can be about 2H, and their dutycycle can be about 50%.The every approximately 2H of store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R swings once.As shown in figure 12, each of two respective stored clock signal clk _ R and CLKB_R or CLK_L and CLKB_L has the contrary waveform of phase place.Predetermined time delay is there is between each and store clock signal CLK_L and CLKB_L corresponding with store clock signal CLK_R and CLKB_R of respective stored clock signal clk _ R and CLKB_R.In an exemplary embodiment, time delay can be such as about 1H, but is not limited to this.Store clock signal CLK_L, CLKB_L, CLK_R and CLKB_R have the 4th high level voltage Vh4 and the 4th low level voltage Vl4(Figure 13 A).Such as, high level voltage Vh4 can be about 15V, and low level voltage Vl4 can be about-1V, but is not limited to this.
Signal generating circuit 710b comprises each alternative 6th transistor Tr61 containing control end, input end and output terminal and alternative 7th transistor Tr71 further.
The input of alternative 6th transistor Tr61 is connected with input end IP21 with control end, be connected with the control end of first to third transistor Tr1-Tr3 with the alternative output terminal of the 6th transistor Tr61, thus make alternative 6th transistor Tr61 effectively play diode.
The control end of alternative 7th transistor Tr71 is connected with control end IP22, the input end of alternative 7th transistor Tr71 is connected with input end IP21, is connected with the control end of first to third transistor Tr1-Tr3 with the alternative output terminal of the 7th transistor Tr71.
Referring now to Figure 13 A, signal generating circuit 710b is described in further detail, wherein, the direction of scanning of gate driver 402 is forward directions.
When by the i-th gate signal g ienabling voltage Von be supplied to signal generating circuit 710b, such as, during the input end IP21 of the i-th signal generating circuit 710b be connected with even number storage line, alternative 6th transistor Tr61 conducting, and first to third transistor Tr1-Tr3 also conducting.
Therefore, for the i-th gate signal g ithe applying of enabling voltage Von, the signal of the voltage level of the respective state had based on the first to the three clock signal C K1, CK1B and CK2 is sent to output terminal OP and as storage signal V siexport.
At gate signal g ienabling voltage Von period 1 T1 in, first clock signal C K1 is on the first low level voltage Vl1, with second and the 3rd clock signal C K1B and CK2 be in respectively on the first and second high level voltage Vh1 and Vh2, and exported the storage signal V with high level storage signal voltage V+ from output terminal OP by the operation of the first, the 3rd and the 5th transistor Tr1, Tr3 and Tr5 si.
But, due at gate signal g ienabling voltage Von cycle T 2 in, first clock signal C K1 changes over the first high level voltage Vh1, with second and the 3rd clock signal C K1B and CK2 change over the first and second low level voltage Vl1 and Vl2 respectively, will there is the storage signal V of low level storage signal voltage V-by the operation of first, second and the 4th transistor Tr1, Tr2 and Tr4 sibe sent to output terminal OP, thus make storage signal V silow level storage signal voltage V-is changed over from high level storage signal voltage V+.
After cycle T 2, gate signal g ichange over and close gate voltage Voff, thus the alternative 6th transistor Tr61 of diode action is turned off.Consequently, node N(Figure 10 of being attached thereto of each output terminal of alternative 6th transistor and alternative 7th transistor Tr61 and Tr71) voltage VN ihigh level state before keeping, causes first to third transistor Tr1-Tr3 to keep conducting state, until the store clock signal CLK_L be applied on control end IP22 changes over the 4th high level voltage Vh4 again.Storage signal V sivoltage level determine according to the voltage level of the first to the three clock signal C K1, CK1B and CK2.More particularly, first clock signal C K1 changes over the first low level voltage Vl1, with second and the 3rd clock signal C K1B and CK2 change over the first and second high level voltage Vh1 and Vh2 respectively, thus according to the first, the 3rd and the 5th transistor Tr1, Tr3 and Tr5 according to the operation of first, second, and third clock signal C K1, CK1B and CK2, high level storage signal voltage V+ is sent to output terminal OP, causes storage signal V sichange over high level storage signal voltage V+ from low level storage signal voltage V-to export from output terminal OP.
After have passed through the schedule time, when being applied to the store clock signal CLK_L on control end IP22 and being on the 4th high level voltage Vh4, alternative 7th transistor Tr71 conducting, thus by gate signal g ipass gate voltage Voff be applied on the control end of first to third transistor Tr1-Tr3.Therefore, first to third transistor Tr1-Tr3 each turn off.So, storage signal V siaccording to being charged to the voltage of capacitor C2 and the 5th transistor Tr5 according to the operation of charging voltage, in next frame, keep high level storage signal voltage V+.
Then, for (i+1) signal generating circuit 710b that (i+1) that be connected with odd number storage line connects, the operation of signal generating circuit 710b is described.
Still with reference to Figure 10 and 13A, when by (i+1) gate signal g i+1enabling voltage Von when being supplied to input end IP21, alternative 6th transistor Tr61 conducting, and first to third transistor Tr1-Tr3 also conducting.
Therefore, for (i+1) gate signal g i+1the applying of enabling voltage Von, the signal of the voltage level of the state had based on the first to the three clock signal C K1, CK1B and CK2 is sent to output terminal OP and as storage signal V si+1export.
At gate signal g i+1enabling voltage Von period 1 T1 in, first clock signal C K1 is on the first high level voltage Vh1, with second and the 3rd clock signal C K1B and CK2 be in respectively on the first and second low level voltage Vl1 and Vl2, and exported the storage signal V with low level storage signal voltage V-from output terminal OP by the operation of first, second the 4th transistor Tr1, Tr2 and Tr4 si+2.
But, at gate signal g i+1enabling voltage Von cycle T 2 in, first clock signal C K1 changes over the first low level voltage Vl1, with second and the 3rd clock signal C K1B and CK2 change over the first and second high level voltage Vh1 and Vh2 respectively, and will there is the storage signal V of high level storage signal voltage V+ by the operation of first, second and the 4th transistor Tr1, Tr2 and Tr4 si+1be sent to output terminal OP.Therefore, storage signal V si+1change over high level storage signal voltage V+ from low level storage signal voltage V-to export from output terminal OP.
After cycle T 2, gate signal g i+1change over and close gate voltage Voff, but be applied to before the store clock signal CLKB_R on direct control end IP22 changes over the 4th high level voltage Vh4, the voltage VN of node N i+1front low level state Vl5 can not be changed over, but remained on high level state Vh5 by the operation of the alternative 6th transistor Tr61 playing diode action, cause first to remain on conducting state to third transistor Tr1-Tr3.So, because the first clock signal C K1 is on the first high level voltage Vh1, with second and the 3rd clock signal C K1B and CK2 be the first and second low level voltage Vl1 and Vl2 respectively, by the operation of first, second and the 4th transistor Tr1, Tr2 and Tr4, low level storage signal voltage V-is sent to output terminal IP as storage signal V si+1.Consequently, storage signal V si+1again change over low level storage signal voltage V-from high level storage signal voltage V+.
After have passed through the schedule time, when being applied to the store clock signal CLKB_R on control end IP22 and changing over the 4th high level voltage Vh4, alternative 7th transistor Tr71 conducting, and will the gate signal g of gate voltage Voff be closed i+1be applied on the control end of first to third transistor Tr1-Tr3, turn off first to third transistor Tr1-Tr3.Therefore, storage signal V si+1according to the charging voltage of capacitor C1 and the operation of the 4th transistor Tr4, remain on low level storage signal voltage V-until next frame.
Hereinafter, the operation of signal generating circuit 710b is described in further detail with reference to Figure 13 B, wherein, the direction of scanning of gate driver 402 is backward directions.
As shown in Figure 13 B, except being applied to the respective gate signal on input end IP21, the operation of signal generating circuit 710b be similar to above with reference to described in Figure 13 A, the direction of scanning of gate driver 402 is that the operation of signal generating circuit 710b in forward direction situation is identical, therefore, any repeated description of will omit them here.
According to one exemplary embodiment of the present invention as above, within the time cycle of about 1H of the period 1 T1 of enabling voltage Von, export the corresponding level of the 3rd clock signal C K2 as storage signal, but because the response speed of liquid crystal display is slow compared with time cycle 1H, the change of the storage signal of about 1H can not cause the significant change of pixel electrode line.
And, store clock signal CLK_L, CLKB_L, CLK_R and the CLKB_R be applied on the control end IP22 of signal generating circuit 710b as shown in Figure 10 determines the voltage level on node N according to pass gate voltage Voff, can not change during the time cycle of the about 1H causing the voltage level that is sent to output terminal OP to change at the first to the three clock signal C K1, CK1B and CK2, thus make the voltage level of the storage signal with suitable amplitude leyel remain to next frame.
Therefore, in the storage signal generator 702 of the LCD according to one exemplary embodiment of the present invention, except normal door line G 1-G 2noutside transmit extra gate signal door line be unnecessary, and do not need the discrete direction signal corresponding with the direction of scanning of gate driver 402.
Referring now to Figure 14 to 17B, the LCD according to another one exemplary embodiment of the present invention is described in further detail.
Figure 14 is the calcspar of the liquid crystal display according to another one exemplary embodiment of the present invention.Figure 15 is the schematic circuit of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 14, and Figure 16 is the plane figure of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 15.Figure 17 A is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 15 utilizing row reversion, and Figure 17 B is the signal timing diagram of the signal generating circuit according to the one exemplary embodiment of the present invention in Figure 15 utilizing frame to reverse.
Except the different piece described in further detail below, the LCD of the one exemplary embodiment of the present invention according to such as Figure 14-17B is similar to the LCD of one exemplary embodiment is identical in greater detail above.Therefore, in Figure 14-17B, represent the element performed with same or analogous operation in above-mentioned one exemplary embodiment with identical label, and any repeated description of will omit them below.
As shown in figure 14, LCD comprises liquid crystal panel assembly 300c, gate driver 403, data driver 500, the grayscale voltage generator 800 be connected with data driver 500, storage signal generator 703 and controls the signal controller 603 of upper element.
As shown in Figure 9, gate driver 403 is bidirectional gate drivers.
Storage signal generator 703 comprises the first and second storage signal generative circuit 703a and 703b.First and second storage signal generative circuit 703a and 703b each comprise each and multiple storage electrode line S 1-S 2n(Fig. 1) the multiple signal generating circuit 710c connected.
Each signal generating circuit 710c is similar to identical with as shown in Figure 10 that, such as, as shown in figure 15, each signal generating circuit 710c comprises output terminal OP, each is containing the first to the five transistor Tr1-Tr5 of control end, input end and output terminal and the first and second capacitor C1 and C2.
But each signal generating circuit 710c comprises first input end IP31 and the second input end IP32 and control end IP41 further.
With reference to Figure 15, in the i-th signal generating circuit 710c, first input end IP31 and supply (i+2) gate signal g i+2(i+2) door line G i+2connect, and the second input end IP32 and supply (i-2) gate signal g i-2(i-2) door line G i-2connect.
Similarly, in (i+1) signal generating circuit 710c, first input end IP31 and supply (i+3) gate signal g i+3(i+3) door line G i+3connect, and the second input end IP32 and supply (i-1) gate signal g i-1(i-1) door line G i-1connect.
As shown in figure 16, the second input end IP32 of each first signal generating circuit 710c of the first and second storage signal generative circuit 703a and 703b receives the first scanning commencing signal STV1 and the 3rd scanning commencing signal STV3 be applied to respectively on adjacent door driving circuit 403a and 403b, and the second scanning commencing signal STV2 and the 4th scanning commencing signal STV4 be applied on adjacent door driving circuit 403a and 403b is supplied to the first input end IP31 of the last signal generating circuit 710c of the first and second storage signal generative circuit 703a and 703b.But, in alternative one exemplary embodiment, such as, by the discrete signals line as glitch line, the discrete signals from external unit (not shown) can be supplied to first of the first and second storage signal generative circuit 703a and 703b and first and second input end IP31 and IP32 of last signal generating circuit 710c, but be not limited to this.
First, second, and third clock signal C K1, CK1B and CK2 of the storage control signal CONT3 from signal controller 603 are supplied to signal generating circuit 710c respectively, and are supplied to signal generating circuit 710c by from the high pressure AVDD of signal controller 603 or external unit (not shown) and low pressure AVSS.
Still with reference to Figure 16, also by control end IP41, multiple Gating clock signal one of GCK_L, GCK_R, GCKB_L and the GCKB_R of gate control signal (Figure 14) CONT1 from signal controller 603 are supplied to each signal generating circuit 710c.
Refer back to Figure 15, signal generating circuit 710c comprises each the eight to the ten transistor Tr8-Tr10 containing control end, input end and output terminal further.
The control end of the 8th transistor Tr8 is connected with first input end IP31, the input end of the 8th transistor Tr8 is connected with the first direction signal DIR of storage control signal CONT3a, and the output terminal of the 8th transistor Tr8 is connected with the control end of first to third transistor Tr1-Tr3.
The control end of the 9th transistor Tr9 is connected with the second input end IP32, the input end of the 9th transistor Tr9 is connected with the second direction signal DIRB of storage control signal CONT3a, and the output terminal of the 9th transistor Tr9 is connected with the control end of first to third transistor Tr1-Tr3.
The control end of the tenth transistor Tr10 is connected with control end IP41, and the input end of the tenth transistor Tr10 is connected with pass gate voltage Voff, and the output terminal of the tenth transistor Tr10 is connected with the control end of first to third transistor Tr1-Tr3.
The operation that each contains first and second storage signal generative circuit 703a and 703b of signal generating circuit 710c will be described in further detail below.Just for the purpose of illustrating, the inversion-type of described LCD is row reversion.
Be forward direction by the direction of scanning for gate driver 403 below, thus first direction signal DIR has high level voltage, and second direction signal DIRB has the situation of low level voltage, describe the operation of signal generating circuit 710c with reference to Figure 17 A.
Further, with reference to Figure 15 and 17A, signal generating circuit 710c is described, such as, with the i-th storage electrode line S as odd number storage electrode line ithe operation of the i-th signal generating circuit connected.
Be applied with the i-th gate signal g ienabling voltage Von after, (i+2) gate signal g i+2enabling voltage Von be applied on input end IP31, thus make the 8th transistor Tr8 conducting, therefore, the third high level voltage Vh3 of first direction signal DIR is applied to by node N1 on the control end of first to third transistor Tr1-Tr3, and conducting first is to third transistor Tr1-Tr3.
Therefore, as shown in Figure 17 A, (i+2) gate signal g is being applied with i+2enabling voltage Von about 2H in, the respective voltage level based on the voltage level of the first to the three clock signal C K1, CK1B and CK2 outputs to output terminal OP as storage signal V si.Now, due to (i-2) gate signal g i-2keep closing open voltage Voff, so the 9th transistor Tr9 turns off, and second direction signal DIRB does not affect the voltage VN1 of node N1.
Therefore, at (i+2) gate signal g i+2enabling voltage Von period 1 T1 in, by the operation of first, second and the 4th transistor Tr1, Tr2 and Tr4, the storage signal V from output terminal OP output on low level storage signal voltage V- si.At (i+2) gate signal g i+2enabling voltage Von cycle T 2 in, by the operation of the first, the 3rd and the 5th transistor Tr1, Tr3 and Tr5, the storage signal V from output terminal OP output on high level storage signal voltage V+ si.
Still with reference to Figure 17 A, at (i+2) gate signal g i+2enabling voltage Von cycle T 2 after, the Gating clock signal GCK_L be applied on control end IP41 keeps the 4th high level voltage Vh4 in about 2H.
Consequently, the tenth transistor Tr10 conducting and pass gate voltage Voff is applied on node N1, and turn off first to third transistor Tr1-Tr3.
So, due to second capacitor C2 charge voltage and the 5th transistor Tr5 according to the operation of charging voltage, storage signal V siremain on high level storage signal voltage V+ until next frame.
Then, describe in further detail and (i+1) storage electrode line S as even number storage electrode line with reference to Figure 15 and 17A i+1the operation of the signal generating circuit 710C connected.
The same with the i-th signal generating circuit 710C, as (i+3) gate signal g i+3enabling voltage Von when being applied on input end IP31, the 8th transistor Tr8 conducting, and by the first direction signal conduction first with third high level voltage Vh3 to third transistor Tr1-Tr3.Therefore, based on the storage signal V of the corresponding level voltage of the voltage level of first, second, and third clock signal C K1, CK1B and CK2 si+1output to output terminal OP.
As (i+3) gate signal g i+ 3state when changing over enabling voltage Von from pass gate voltage Voff, the Gating clock signal GCK_R be applied on control end IP41 keeps the 4th high level voltage Vh4 in about 2H.
Therefore, the tenth transistor Tr10 conducting, and turn off first to third transistor Tr1-Tr3 by the pass gate voltage Voff being sent to node N1.Subsequently, storage signal V si+1according to the voltage charged to the first capacitor C1 and the 4th transistor Tr4 according to the operation of charging voltage, keep low level storage signal voltage V-until next frame.
When after the direction of scanning of gate driver 403 is to direction, first direction signal DIR has the 3rd low level voltage Vl3 and second direction signal DIRB has third high level voltage Vh3.Therefore, different from scan forward direction, when direction of scanning is backward direction, by being applied to gate signal on the second input end IP32 and second direction signal DIRB conducting first to third transistor Tr1-Tr3.
In addition to the above, the operation of signal generating circuit 710c and the direction of scanning of gate driver 403 are forward directions, export the situation with the storage signal of the level corresponding with respective stored electrode wires identical, therefore omit the repeated description of the operation to channel selector 710c here.And, that the situation of forward direction is similar with the direction of scanning of gate driver 403, after the gate signal be applied on first input end IP31 exports enabling signal Von in about 2H, export in a frame and close gate signal Voff, thus the 8th transistor Tr8 is turned off.Therefore, first direction signal DIR does not affect the voltage VN1 of node N1.
Then, the operation of signal generating circuit 710c is described in further detail with reference to Figure 15 and 17B, and in this case, the LCD according to one exemplary embodiment of the present invention works under frame reversing mode.
The operation of signal generating circuit 710c is described in further detail referring now to Figure 17 B.The operation of signal generating circuit 710c and the class of operation of the signal generating circuit 710c described in reference Figure 17 A are seemingly.
In fig. 17, the every predetermined period of first, second, and third clock signal C K1, CK1B and CK2 (such as, about 1H) alternately change, but as seen in this fig. 17b, each of first, second, and third clock signal C K1, CK1B and CK2 keeps constant voltage in a frame.But as seen in this fig. 17b, each the every successive frames of waveform of first, second, and third clock signal C K1, CK1B and CK2 is anti-phase.
When the direction of scanning of gate driver 403 is forward directions, first direction signal DIR has third high level voltage Vh3, and second direction signal DIRB has the 3rd low level voltage Vl3.
First, describe for being applied on pixel PX, there is the data voltage of such as positive polarity, with the i-th storage electrode line S ithe operation of the i-th signal generating circuit 710c connected.
First clock signal C K1 keeps the first low level voltage Vl1, and second and the 3rd clock signal C K1B and CK2 keep the first high level voltage Vh1.
Be applied with the i-th gate signal g ienabling voltage Von after, when by (i+2) gate signal g i+2enabling voltage Von when being applied on first input end IP31, the 8th transistor Tr8 conducting, and first to third transistor Tr1-Tr3 by first direction signal DIR conducting.
Because the 3rd clock signal C K2 keeps the second high level voltage Vh2, storage signal V sikeep high level storage signal voltage V+.
As (i+2) gate signal g i+2change over and close gate voltage Voff, and when turning off first to third transistor Tr1-Tr3 by the corresponding clock signal be applied on control end IP41, as such as Gating clock signal GCK_L, storage signal V sivoltage and the 5th transistor Tr5 according to being charged to the second capacitor C2 keep high level storage signal voltage V+ until next frame according to the operation of charging voltage.
Then, the data voltage with negative polarity is described in further detail when being applied on pixel PX, with the i-th storage electrode line S ithe operation of the i-th signal generating circuit 710c connected.In this case, the first clock signal C K1 keeps the first high level voltage Vh1, and second and the 3rd clock signal C K1B and CK2 keep the first low level voltage Vl1.
Be applied with the i-th gate signal g ienabling voltage Von after, when by (i+2) gate signal g i+2enabling voltage Von when being applied on first input end IP31, in response to the 8th transistor Tr8 conducting, the first to third transistor Tr1-Tr3 also conducting respectively.Therefore, by keeping the 3rd clock signal C K2 of the second low level voltage Vl2, storage signal V is made sioutput low level storage signal voltage V-.
Subsequently, as (i+2) gate signal g i+2change over and close gate voltage Voff, and when turning off first to third transistor Tr1-Tr3 by the Gating clock signal GCK_L be applied on control end IP41, storage signal V sikeep low level storage signal voltage V-until next frame according to the voltage charged to the first capacitor C2 and the 4th transistor Tr4 according to the operation of charging voltage.
When the sweep signal of gate driver 403 is along backward direction, first direction signal DIR has the 5th low level voltage Vl5, and second direction signal DIRB has the first high level voltage Vh5.
Therefore, when the direction of scanning of gate driver 403 is backward directions, by being applied to gate signal on the second input end IP32 and second direction signal DIRB conducting first to third transistor Tr1-Tr3.In addition to the above, the operation of signal generating circuit 710c with above in greater detail the direction of scanning of gate driver 403 be that the situation of forward direction is identical, therefore omit any repeated description of the operation to signal generating circuit 710c here.
As mentioned above, when LCD works with frame reversing mode, first, second, and third clock signal C K1, CK1B and CK2 keep same voltage level in an about frame.
So, be applied to after the gate signal in corresponding pixel lines to change over from enabling voltage Von and close gate voltage Voff, due to signal generating circuit 710c as shown in figure 15 export according to the next stage from the first or second gate driver 403a or 403b, relative to first or the previous stage of the second gate driver 403a or the 403b enabling voltage Von that is delayed the gate signal of about 2H work, there is frame reversion.Therefore, owing to being applied to i-th line G ion enabling voltage Von and the enabling voltage Von being applied on the i-th storage signal generative circuit 710c between difference be about 2H, enabling voltage Von can not be overlapping.Therefore, after the charging operations of the i-th pixel column completes substantially, be applied to the i-th storage electrode line S ion storage signal V sisignal level change, thus according to storage signal V sichange signal level change the charging voltage of the i-th pixel column.
Alternately, when have passed through the schedule time after completing since the change of gate signal, the state of first, second, and third clock signal C K1, CK1B and CK2 can change, and pass gate voltage can be changed in gate signal from enabling voltage, or alternately, after pass gate voltage changes over enabling voltage, export first, second, and third clock signal C K1, CK1B and CK2.
According to one exemplary embodiment as of the invention described herein, because utility voltage is fixed on predetermined level, be applied on storage electrode line with amplitude with the storage signal that predetermined period changes, the scope of pixel electrode voltage is increased, with make the expanded range of pixel voltage, the scope of grayscale voltage does not then have corresponding increase.Therefore, expand the effective voltage scope of grayscale voltage, thus effectively improve resolution.
And the scope of the pixel voltage generated when applying the data voltage of certain scope is greater than the scope of the pixel voltage generated when applying the storage signal of predetermined value.Therefore, power consumption is significantly reduced.In addition, have employed liquid crystal display containing bidirectional gate driver and storage signal generator without the need to additional selection circuit, thus effectively reduce the size of liquid crystal display and/or reduce the manufacturing cost of liquid crystal display.
In alternative one exemplary embodiment, the liquid crystal display according to one exemplary embodiment of the present invention according to such as frame reversion and row reversion work, but can be not limited to this.
The present invention should not be understood to the one exemplary embodiment being confined to provide herein.Or rather, these one exemplary embodiment are provided to be to make the disclosure become comprehensively thoroughly, passing on concept of the present invention to those of ordinary skill in the art fully.
Although made specific descriptions to the present invention by referring to some one exemplary embodiment of the present invention, but those of ordinary skill in the art should be understood that, various change can be done to it in form and details, and not depart from the spirit and scope of the present invention of appended claims restriction.

Claims (20)

1. a display device, comprising:
Many door lines, for transmitting the gate signal having enabling voltage and close gate voltage;
A plurality of data lines, for transmitting data voltage;
Many storage electrode lines, for transmitting storage signal;
Be arranged in multiple pixels of approximate matrix pattern, wherein, the first pixel of the plurality of pixel comprises:
The on-off element be connected with a data line in first line of transmission first gate signal in many door lines and a plurality of data lines;
The liquid crystal capacitor be connected with on-off element and utility voltage; And
The holding capacitor be connected with a storage electrode line in on-off element and many storage electrode lines;
Gate driver, for generating gate signal along the first direction of scanning or the second direction of scanning; And
Multiple signal generating circuit, for generating storage signal,
Wherein, the storage signal be applied in the first pixel has the voltage level changed after charge data voltage is charged to liquid crystal capacitor and holding capacitor,
Storage signal becomes from the output order of multiple signal generating circuit with the direction of scanning of gate driver,
The first signal generating circuit that the storage electrode line to the first pixel in the plurality of signal generating circuit applies storage signal comprises the signal input unit exporting drive control signal, the storage signal applying unit exporting storage signal, control module and keeps the signal holding unit of storage signal
This signal input unit comprises the first transistor and transistor seconds, the first transistor comprises the input end receiving first direction signal and the control end receiving the second gate signal, transistor seconds comprises the input end receiving second direction signal and the control end receiving the 3rd gate signal, this signal input unit comprises the input end having and be connected with pass gate voltage further, the control end be connected with clock signal and the 7th transistor of output terminal be connected with drive control signal, the first transistor, transistor seconds, the output terminal of the 7th transistor is connected the output terminal forming this signal input unit,
This storage signal applying unit comprises third transistor, and it comprises the input end of reception first control signal, comprises the control end be connected with the output terminal of signal input unit, and comprises the output terminal be connected with storage electrode line, and
This control module comprises two the 4th transistors, described two the 4th transistors comprise the control end be connected with the output terminal of signal input unit, one of described two the 4th transistors comprise the input end be connected with the second control signal, and another of described two the 4th transistors comprises the input end be connected with the 3rd control signal
Wherein, this signal holding unit comprises:
Containing the control end be connected with the output terminal of one of described two the 4th transistors, the input end be connected with the first driving voltage and the 5th transistor of output terminal that is connected with storage electrode line;
Containing the control end be connected with another output terminal of described two the 4th transistors, the input end be connected with the second driving voltage and the 6th transistor of output terminal that is connected with storage electrode line;
Be connected to the first capacitor between the input end of the 5th transistor and control end; And
Be connected to the second capacitor between the input end of the 6th transistor and control end,
Wherein, the storage signal be applied in the first pixel changes over high level when charge data voltage has positive polarity from low level, and changes over low level when charge data voltage has negative polarity from high level,
Wherein, utility voltage is fixed voltage.
2. display device according to claim 1, wherein, each frame of this storage signal is anti-phase.
3. display device according to claim 1, wherein,
Starting after-applied second gate signal applying the first gate signal to first line,
The 3rd gate signal was applied before beginning applies the first gate signal to first line,
Wherein, mistiming between the enabling voltage application time of the first gate signal and the enabling voltage application time of the second gate signal is about two horizontal cycles (2H), and the mistiming between the enabling voltage application time of the first gate signal and the enabling voltage application time of the 3rd gate signal is about two horizontal cycles (2H).
4. display device according to claim 1, wherein, the second control signal that this signal holding unit applies according to the mode of operation according to control module or the 3rd control signal and operate.
5. display device according to claim 1, wherein, first direction signal and second direction signal have the signal condition of the direction of scanning based on gate driver separately.
6. display device according to claim 5, wherein, the phase place of first direction signal is in fact contrary with the phase place of second direction signal.
7. display device according to claim 1, wherein, the level of first direction signal and each constant of level of second direction signal.
8. display device according to claim 1, wherein, this signal input unit selects one of first direction signal and second direction signal according to the second gate signal and the 3rd gate signal, and exports drive control signal according to selected first direction signal or selected second direction signal.
9. display device according to claim 8, wherein, the level of first direction signal and each constant of level of second direction signal.
10. display device according to claim 9, wherein, this signal input unit is supplied the clock signal of the second electrical level voltage having the first level voltage and be different from the first level voltage, and each predetermined period in succession of the level of this clock signal replaces between the first level voltage and second electrical level voltage.
11. display devices according to claim 10, wherein, the interval of this predetermined period is about two horizontal cycles (2H).
12. display devices according to claim 11, wherein, the phase place being applied to the clock signal on the first signal generating circuit of multiple signal generating circuit is in fact contrary with the phase place being applied to the clock signal on the secondary signal generative circuit adjacent with the first signal generating circuit.
13. display devices according to claim 12, wherein, this signal input unit is by changing the state of operation signal holding unit of the drive control signal based on first direction signal or second direction signal according to clock signal.
14. display devices according to claim 13, wherein, the voltage level being applied to the storage signal on the first storage electrode line of many storage electrode lines is practically identical with the voltage level being applied to the storage signal on the second storage electrode line adjacent with the first storage electrode line.
15. display devices according to claim 14, wherein, the voltage level of the voltage level of the first control signal, the voltage level of the second control signal and the 3rd control signal is giving constant in framing, and each successive frames is anti-phase.
16. display devices according to claim 1, wherein, the voltage level being applied to the storage signal on the first storage electrode line of many storage electrode lines is different with the voltage level of the storage signal be applied on the second storage electrode line adjacent from the first storage electrode line.
17. display devices according to claim 16, wherein,
First control signal, the second control signal and the 3rd control signal each there is the first level voltage and second electrical level voltage,
The respective level of the first control signal, the second control signal and the 3rd control signal giving in framing every subsequent cycles between the first level voltage and second electrical level voltage alternately, and
The respective level of the first control signal, the second control signal and the 3rd control signal is anti-phase every a frame.
18. display devices according to claim 1, comprise at least one extra gate line gate signal being sent to a signal generating circuit in multiple signal generating circuit further.
19. display devices according to claim 1, wherein, adjacent gate signal predetermined time cycle at least partially in overlapped in time.
20. display devices according to claim 19, wherein, the interval of this predetermined period of time is an about horizontal cycle (1H).
CN201210101486.9A 2006-10-24 2007-10-24 Display device and driving method thereof Expired - Fee Related CN102622984B (en)

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