CN100444236C - Liquid crystal display driving method and its driving circuit - Google Patents

Abstract

The invention is a LCD driving method, comprising the steps of: supplying a first voltage to the nth scanning line (n>=1,and n is an integer) of a driven TFT LCD; supplying a second voltage opposite to the first voltage in phase to the nth scanning line of the TFT LCD and simultaneously supplying the first voltage to the (n+1)th scanning line; supplying the second voltage to the (n+1)th scanning line of the TFT LCD; supplying a third voltage to the nth scanning line of the TFT LCD, where the third voltage is lower than the first voltage and used to switch off the grids of TFTs connected with the nth scanning line; and supplying the third voltage to the (n+1)th scanning line of the TFT LCD.

Description

Liquid crystal display driving method and its driving circuit

【Technical field】

The invention relates to a liquid crystal display driving method and its driving circuit, in particular to a thin film transistor liquid crystal display gate driving method and its driving circuit.

【Background technique】

At present, the requirements for the optical performance of liquid crystal displays (Liquid Crystal Display, LCD) are getting higher and higher, including high brightness, high contrast, high aperture ratio (ApertureRatio) and wide viewing angle, etc. The size of the aperture ratio is an important factor affecting the brightness and design of the LCD panel, so the design of the current LCD panel mostly adopts the method of storing the storage capacitor on the gate (Cs On Gate).

Please refer to FIG. 1 , which is a schematic diagram of an equivalent circuit of a conventional liquid crystal display panel. The liquid crystal display panel 10 includes a gate driver 1, a source driver 2, scanning lines G1...Gn (n≥1, n is an integer) parallel to each other and connected to the gate driver 1, parallel to each other and connected to the source driver 2 connected data lines D1...Dm (m≥1, m is an integer) and the thin film transistor 3. The scanning lines G1...Gn and the data lines D1...Dm are insulated and intersect; the thin film transistor 3 is located at the intersection of the scanning lines G1...Gn and the data lines D1...Dm, and its gate 31 is connected to the scanning line G1 ... Gn connection, its source 32 is connected to the data line D1...Dm, its drain 33 is connected to the storage capacitor Cs 4 and the pixel electrode 6, the pixel electrode 6 and the common electrode 7 form a liquid crystal capacitor C1c 8, the The other end of the storage capacitor Cs4 is connected to the next scan line.

Please refer to FIG. 2 together, which is a timing diagram of driving waveforms of the gate driver 1 in FIG. 1 . Gate driver 1 provides two different scanning voltages, namely V5 and V6. The voltage value of V5 is a high voltage for turning on the gate 31 of the thin film transistor 3 , and V6 is a low voltage for turning off the gate 31 of the thin film transistor 3 . When the gate 31 connected to the scan line G1 is closed, the voltage is lowered from V5 to V6, and at the same time, the gate driver 1 provides a voltage V5 to open the gate 31 connected to the scan line G2. Similarly, the gate 31 connected to the scan line G2 is opened in turn. ..Gn connected gate 31. Taking the resolution of SVGA (1024×768) and the picture update frequency of 60 Hz as an example to illustrate, the range indicated by the arrow in the figure is the period of one frame (Frame) picture, which is about 16.67 ms. G1-Gn represent 768 outputs of the driver 1 respectively, and the start-up time period of the gate 31 is also 16.67ms. Between 16.67ms, a total of 768 output lines of G1-Gn need to be turned on and then turned off in sequence, so the time allocated to turn on each line is only 16.67ms/768=21.7μs. Within 21.7 μs, the source gate driver 2 charges the corresponding pixel electrode 6 to the required voltage. The driving mode of the gate driver 1 is two-stage driving, that is, its output voltage has only two values, which are the open voltage and the close voltage of the thin film transistor gate respectively.

However, since the storage capacitor is located at the gate, the other end of the storage capacitor is connected to the next scan line instead of the common voltage source, so after a certain scan line is turned off, that is, when the next scan line is turned on, the next scan line The line voltage change will cause a feedthrough voltage (FeedThrough) to the nth pixel electrode through the storage capacitor Cs4, so the voltage change provided by the gate driver 1 to the gate 31 will cause a feedthrough voltage. The feed-through voltage will cause a feed-through effect, that is, the original output voltage range of the source driver 2, due to the influence of the feed-through voltage, the voltage range of the pixel electrode 6 is inconsistent with the original expectation, which will cause flickering and reduce the picture quality.

【Content of invention】

In order to overcome the defect in the prior art that the voltage range of the pixel electrode is inconsistent with the original expectation due to the influence of the feed-through voltage, which will cause flickering of the picture and reduce the picture quality, it is necessary to provide a method to prevent the influence of the feed-through voltage from causing the pixel electrode. A liquid crystal display driving method and a liquid crystal display driving circuit that cause picture flicker and reduce picture quality due to voltage range inconsistent with original expectation.

A method for driving a liquid crystal display, used for driving a thin film transistor liquid crystal display, the thin film transistor liquid crystal display includes a plurality of scanning lines parallel to each other and a plurality of thin film transistors, the scanning lines are connected to the gates of the thin film transistors, and the thin film transistors A storage capacitor is formed between the next scan line of the scan line corresponding to the drain electrode and the gate electrode, and the method includes the following steps:

Step 1: providing a first voltage to the nth (n≥1, n is an integer) scanning line of the driven thin film transistor liquid crystal display, which is used to open the gate of the thin film transistor connected to the nth scanning line;

Step 2: providing a second voltage to the nth scan line of the driven thin film transistor liquid crystal display, and at the same time providing the first voltage to the n+1th scan line, the second voltage is smaller than the first voltage and has an opposite phase with it, using To compensate the feed-through voltage generated by the storage capacitor of the driven liquid crystal display;

Step 3: providing a second voltage to the n+1th scan line of the driven TFT-LCD scan line;

Step 4: providing a third voltage to the nth scanning line of the driven thin film transistor liquid crystal display; the third voltage is lower than the first voltage and used to close the gate of the thin film transistor connected to the nth scanning line;

Step 5: providing a third voltage to the n+1th scanning line of the driven TFT-LCD scanning lines.

A liquid crystal display driving circuit, which includes a plurality of serial driving units, each of which includes eight thin film transistors.

The gate of the first thin film transistor is connected to the first voltage source, its source is connected to the source of the third thin film transistor and connected to a third voltage source, and its drain is connected to the source of the second thin film transistor and the sixth thin film transistor. the gate connection of the transistor;

The gate of the second thin film transistor is connected to the gate of the third thin film transistor as a first input terminal, its source is connected to the drain of the first thin film transistor, and its drain is connected to the drains of the fourth and sixth thin film transistors and ground;

The gate of the third thin film transistor is connected to the gate of the second thin film transistor, its source is connected to the source of the first thin film transistor, its drain is connected to the source of the fourth thin film transistor, and the fifth and seventh thin film transistors grid connection;

The gate of the fourth thin film transistor is connected to the gate of the first thin film transistor, its source is connected to the drain of the third thin film transistor, and its drain is connected to the drain of the second thin film transistor;

The gate of the fifth thin film transistor is connected to the drain of the third thin film transistor, its source is connected to the source of the seventh thin film transistor and connected to a second voltage source, and its drain is connected to the source of the sixth thin film transistor And as the first output terminal;

The gate of the sixth thin film transistor is connected to the drain of the first thin film transistor, its source is connected to the drain of the fifth thin film transistor, and its drain is connected to the drains of the second and fourth thin film transistors and grounded;

The gate of the seventh thin film transistor is connected to the drain of the third thin film transistor and the gate of the fifth thin film transistor, its source is connected to the source of the fifth thin film transistor and to the second voltage source, and its drain is connected to the second voltage source. The sources of the eight thin film transistors are connected and used as the second output terminals;

The gate of the eighth thin film transistor serves as a second input terminal, its source is connected to the drain of the seventh thin film transistor and serves as a second output terminal, and its drain is connected to the fourth voltage source;

When the gate of the sixth thin film transistor is turned on, the voltage output by the first output terminal is 0 volts; when the gates of the fifth and seventh thin film transistors are turned on, the voltage output by the first and second output terminals is the second voltage source voltage; when the gate of the eighth thin film transistor is turned on, the voltage output by the second output terminal is the voltage of the fourth voltage source;

The first input terminal of the first drive unit receives the initial voltage signal, the second input terminal is used to receive the output voltage of the second drive unit connected thereto, the first output terminal provides voltage to the second drive unit, and the second output terminal Provide scanning voltage to the driven liquid crystal display; the first input terminal of the last drive unit receives the output voltage of the previous drive unit connected to it; the first input terminal of other drive units is used to receive the previous drive unit connected to it The output voltage of the unit, the second input terminal is used to receive the output voltage of the subsequent circuit connected to it, the first output terminal provides voltage to the first input terminal of the subsequent circuit connected to it, and the second output terminal provides scanning voltage respectively to the driven LCD.

The driving method of the present invention utilizes the third-order driving voltage to reduce the influence of the feedthrough effect, so that the flickering of the picture can be reduced and the picture quality can be improved.

【Description of drawings】

FIG. 1 is a schematic diagram of an equivalent circuit of a liquid crystal display panel in the prior art.

FIG. 2 is a schematic diagram of timing sequence of gate driver driving waveforms.

FIG. 3 is a structural block diagram of the gate drive circuit of the present invention.

FIG. 4 is a schematic diagram of a specific circuit structure of the driving unit in FIG. 3 .

FIG. 5 is a schematic diagram of the driving waveform timing of the liquid crystal display driving method of the present invention.

Fig. 6 is a schematic diagram showing the effect comparison between the driving method of the present invention and the driving method of the prior art.

【Detailed ways】

Please refer to FIG. 3 , which is a structural block diagram of the gate driving circuit of the present invention. The gate drive circuit 11 is used to drive a thin film transistor liquid crystal display (not shown), the thin film transistor liquid crystal display includes a plurality of parallel scan lines and a plurality of thin film transistors, the scan lines are connected to the gate of the thin film transistor, A storage capacitor is formed between the drain of the thin film transistor and the next scan line of the scan line corresponding to the gate. The gate driving circuit 11 includes driving units C1, C2...Cn (n≥1, n is an integer), and the driving units C1, C2...Cn respectively include two input terminals I1, I2, and two output terminals O1 and O2 are respectively connected to a low voltage V2, the first voltage source PH1 and the second voltage source PH2. The first voltage source PH1 and the second voltage source PH2 are pulse voltages with the same voltage and different time sequences. The input terminal I1 of the driving unit C1 is used to receive the initial voltage signal, the input terminal I2 is used to receive the output voltage of the driving unit C2, the output terminal O1 provides voltage to the input terminal I1 of the driving unit C2, and the output terminal O2 provides voltage to the scanning line G1. The input terminal I1 of the drive unit C2...Cn-1 is used to receive the output voltage signal of the previous circuit, the input terminal I2 is used to receive the output voltage of the next drive unit, and the output terminal O1 provides voltage to the next drive unit The input terminal I1 and the output terminal O2 respectively provide voltages to the scan lines G2 . . . Gn. When the input terminal I1 of the driving unit C1 receives a voltage, the n output terminals O2 provide scanning voltages to the scanning lines G2 . . . Gn in time division.

Please refer to FIG. 4 together, which is a schematic diagram of a specific circuit structure of the driving unit C1 in FIG. 3 . The specific circuit structure of the driving units C2, C3...Cn is the same as that of the driving unit C1. The driving unit C1 includes a first thin film transistor P1, a second thin film transistor P2, a third thin film transistor P3, a fourth thin film transistor P4, a fifth thin film transistor P5, a sixth thin film transistor P6, a seventh thin film transistor P7 and an eighth thin film transistor. Transistor P8. The gate of the first TFT P1 is connected to the first voltage source PH1, its source is connected to the source of the third TFT P3 and connected to the third voltage source V2, the third voltage source V2 is a low voltage, the The drain of the first TFT P1 is connected to the source of the second TFT P2 and the gate of the sixth TFT P6. The gate of the second thin film transistor P2 is connected to the gate of the third thin film transistor P3 as the first input terminal I1, its source is connected to the drain of the first thin film transistor P1 and the gate of the sixth thin film transistor P6, and its drain The electrode is connected to the drains of the fourth thin film transistor P4 and the sixth thin film transistor P6 and grounded. The gate of the third thin film transistor P3 is connected to the gate of the second thin film transistor P2 as the first input terminal I1, its source is connected to the source of the first thin film transistor P1, and its drain is connected to the source of the fourth thin film transistor P4 electrode, the gates of the fifth thin film transistor P5 and the seventh thin film transistor P7. The gate of the fourth TFT P4 is connected to the gate of the first TFT P1, the source thereof is connected to the drain of the third TFT P3, and the drain thereof is connected to the drain of the second TFT P2. The gate of the fifth thin film transistor P5 is connected to the drain of the third thin film transistor P3, its source is connected to the source of the seventh thin film transistor P7 and connected to the second voltage source PH2, and its drain is connected to the sixth thin film transistor P6 The source of is connected and serves as the first output terminal O1. The gate of the sixth thin film transistor P6 is connected to the drain of the first thin film transistor P1, its source is connected to the drain of the fifth thin film transistor P5 as the first output terminal O1, and its drain is connected to the second thin film transistor P2, The drain of the fourth thin film transistor P4 is connected to ground. The gate of the seventh thin film transistor P7 is connected to the drain of the third thin film transistor P3 and the gate of the fifth thin film transistor P5, and its source is connected to the source of the fifth thin film transistor P5 and to the second voltage source PH2. The drain is connected to the source of the eighth thin film transistor P8 and serves as the second output terminal O2. The gate of the eighth thin film transistor P8 serves as the second input terminal I2, its source is connected to the drain of the seventh thin film transistor P7 and serves as the second output terminal O2, its drain is connected to the fourth voltage source Vcom, and the fourth The voltage source Vcom is a common voltage source. When the gate of the sixth thin film transistor P6 is turned on, the output voltage of the first output terminal O1 is 0 volts; when the gates of the fifth thin film transistor P5 and the seventh thin film transistor P7 are turned on, the first output terminal O1, the second output The output voltage of the terminal O2 is the voltage of the second voltage source PH1; when the gate of the eighth thin film transistor P8 is turned on, the output voltage of the second output terminal O2 is the voltage of the fourth voltage source Vcom.

The driving method and the gate driving circuit of the present invention use the third-order driving voltage to reduce the influence of the feedthrough effect, so that the flickering of the picture can be reduced and the picture quality can be improved. The gate driving circuit of the present invention can be designed on the glass substrate of the liquid crystal display, so the use of the gate driving IC can be reduced and the cost can be reduced.

Please refer to FIG. 5 , which is a schematic diagram of the timing sequence of driving waveforms of the liquid crystal display driving method of the present invention, which is the driving waveform provided to the gate driver 11 in FIG. 3 . The gate driver 11 provides three different scanning voltages, namely V0, V1 and V2. The voltage value of V1 is 10 volts, which is used to open the gate of the thin film transistor; the voltage value of V0 is 0 volts, which is used to close the gate of the thin film transistor; the voltage value of V2 is -2 volts, which is used to compensate the feedthrough generated by the storage capacitor Voltage. First provide voltage V1 to scan line Gi (1≤i≤n, n is an integer), then provide voltage V2 to scan line Gi, and finally provide voltage V0 to scan line Gi; provide voltage V2 to scan line Gi at any time +1 provides voltage V1, then provides voltage V2 to scan line Gi+1, provides voltage V0 to scan line Gi, and then provides voltage V0 to scan line Gi+1. The voltage V2 of the scanning line Gi can compensate the feedthrough effect of the pixels driven by the scanning line Gi by the feedthrough voltage generated when the voltage V1 is provided to the scanning line Gi+1 to turn it on.

Please refer to FIG. 6 , which is a schematic diagram illustrating the effect comparison between the driving method of the present invention and the driving method of the prior art. Curve A represents the ideal pixel electrode voltage, curve B represents the pixel electrode voltage obtained by using the third-order driving method of the present invention, and curve C represents the pixel electrode voltage obtained by using the second-order driving method in the prior art. It can be seen from the figure that curve B is closer to curve A than curve C, so its transmittance or color coordinates are closer to the ideal value, so the flickering degree of the screen is lower.

Claims (5)

1. liquid crystal display driving method, be used for the drive thin film transistors LCD, this Thin Film Transistor-LCD comprises a plurality of sweep traces that are parallel to each other and a plurality of thin film transistor (TFT), this sweep trace is connected with the grid of this thin film transistor (TFT), form memory capacitance between next bar sweep trace of the drain electrode of this thin film transistor (TFT) and its grid corresponding scanning beam, this method comprises the steps:

Step 1: provide first voltage to the Thin Film Transistor-LCD n that is driven (n 〉=1, n is an integer) bar sweep trace, it is used to open the grid of the thin film transistor (TFT) that is connected with this n bar sweep trace;

Step 2: provide second voltage to the Thin Film Transistor-LCD n bar sweep trace that is driven, simultaneously provide first voltage to n+1 bar sweep trace, this second voltage is less than first voltage and anti-phase with it, is used to compensate the feed-trough voltage that the LCD memory capacitance that driven is produced;

Step 3: the n+1 bar sweep trace to the Thin Film Transistor-LCD sweep trace that is driven provides second voltage;

Step 4: provide tertiary voltage to the Thin Film Transistor-LCD n bar sweep trace that is driven; This tertiary voltage is less than first voltage and be used to close the grid of the thin film transistor (TFT) that is connected with n bar sweep trace;

Step 5: the n+1 bar sweep trace to the Thin Film Transistor-LCD sweep trace that is driven provides tertiary voltage.

2. liquid crystal display driving method as claimed in claim 1 is characterized in that: the magnitude of voltage of this first voltage is 10 volts, and the magnitude of voltage of second voltage is-2 volts, and this tertiary voltage magnitude of voltage is 0 volt.

3. liquid crystal display drive circuit, it comprises the driver element of a plurality of series connection, this each driver element comprises eight thin film transistor (TFT)s;

The transistorized grid of the first film is connected with first voltage source, and its source electrode is connected with the source electrode of the 3rd thin film transistor (TFT) and is connected with a tertiary voltage source, and its drain electrode is connected with the source electrode of second thin film transistor (TFT) and the grid of the 6th thin film transistor (TFT);

The grid of second thin film transistor (TFT) is connected as first input end with the grid of the 3rd thin film transistor (TFT), and source electrode is connected with the first film transistor drain, and drain electrode is connected and ground connection with the drain electrode of the 6th thin film transistor (TFT) with the 4th;

The grid of the 3rd thin film transistor (TFT) is connected with the grid of second thin film transistor (TFT), and its source electrode is connected with the transistorized source electrode of the first film, and its drain electrode is connected with the grid of the 7th thin film transistor (TFT) with the source electrode, the 5th of the 4th thin film transistor (TFT);

The grid of the 4th thin film transistor (TFT) is connected with the transistorized grid of the first film, and its source electrode is connected with the drain electrode of the 3rd thin film transistor (TFT), and its drain electrode is connected with the drain electrode of second thin film transistor (TFT);

The grid of the 5th thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT), and its source electrode is connected with the source electrode of the 7th thin film transistor (TFT) and is connected with one second voltage source, and its drain electrode is connected with the source electrode of the 6th thin film transistor (TFT) and as first output terminal;

The grid of the 6th thin film transistor (TFT) is connected with the first film transistor drain, and its source electrode is connected with the drain electrode of the 5th thin film transistor (TFT), and its drain electrode is connected and ground connection with the drain electrode of the 4th thin film transistor (TFT) with second;

The grid of the 7th thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT), the grid of the 5th thin-film electro crystalline substance, its source electrode is connected with the source electrode of the 5th thin film transistor (TFT) and with second voltage source, and its drain electrode is connected with the source electrode of the 8th thin film transistor (TFT) and as second output terminal;

The grid of the 8th thin film transistor (TFT) is as second input end, and its source electrode is connected with the drain electrode of the 7th thin film transistor (TFT) and as second output terminal, its drain electrode is connected with the 4th voltage source;

When the grid of the 6th thin film transistor (TFT) is opened, then the voltage of first output terminal output is 0 volt; When the grid of the 5th, the 7th thin film transistor (TFT) is opened, the voltage of first, second output terminal output is the voltage of second voltage source; When the grid of the 8th thin film transistor (TFT) is opened, the voltage of second output terminal output is the voltage of the 4th voltage source;

The first input end of first driver element receives the starting potential signal, second input end is used to receive the output voltage of second driver element that is attached thereto, first output terminal provides voltage to second driver element, and second output terminal provides scanning voltage to the LCD that is driven; The first input end of last driver element receives the output voltage of the last driver element that is attached thereto; The first input end of other driver element is used to receive the output voltage of the last driver element that is attached thereto, second input end is used to receive a back circuit output voltage that is attached thereto, first output terminal provides the first input end of voltage to a back circuit that is attached thereto, and second output terminal provides scanning voltage to the LCD that is driven respectively.

4. liquid crystal display drive circuit as claimed in claim 3 is characterized in that: this first voltage source is the different pulse voltage of the identical sequential of voltage with second voltage source, and this tertiary voltage source is a low-voltage source, and the 4th voltage source is a public voltage source.

5. liquid crystal display drive circuit as claimed in claim 3 is characterized in that: the magnitude of voltage of this first voltage is 10 volts, and the magnitude of voltage of second voltage is-2 volts, and this tertiary voltage magnitude of voltage is 0 volt.

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