CN100444236C - Liquid crystal display driving method and driving circuit - Google Patents
Liquid crystal display driving method and driving circuit Download PDFInfo
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- CN100444236C CN100444236C CNB2005101021025A CN200510102102A CN100444236C CN 100444236 C CN100444236 C CN 100444236C CN B2005101021025 A CNB2005101021025 A CN B2005101021025A CN 200510102102 A CN200510102102 A CN 200510102102A CN 100444236 C CN100444236 C CN 100444236C
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Abstract
The invention is a LCD driving method, comprising the steps of: supplying a first voltage to the nth scanning line (n>=1,and n is an integer) of a driven TFT LCD; supplying a second voltage opposite to the first voltage in phase to the nth scanning line of the TFT LCD and simultaneously supplying the first voltage to the (n+1)th scanning line; supplying the second voltage to the (n+1)th scanning line of the TFT LCD; supplying a third voltage to the nth scanning line of the TFT LCD, where the third voltage is lower than the first voltage and used to switch off the grids of TFTs connected with the nth scanning line; and supplying the third voltage to the (n+1)th scanning line of the TFT LCD.
Description
[technical field]
The invention relates to a kind of liquid crystal display driving method and driving circuit thereof, particularly about a kind of Thin Film Transistor-LCD grid drive method and driving circuit thereof.
[background technology]
At present, (Liquid Crystal Display, LCD) requirement of optical property is more and more higher, comprises high brightness, high-contrast, high aperture (ApertureRatio) and wide viewing angle or the like to LCD.The size of aperture opening ratio is the key factor that influences display panels brightness and design, so the design of display panels now adopts memory capacitance to be positioned at the mode of grid (Cs On Gate) mostly.
Please refer to Fig. 1, is a kind of schematic equivalent circuit of display panels of prior art.Sweep trace G1...Gn (n 〉=1 that this display panels 10 comprises gate drivers 1, source electrode driver 2, is parallel to each other and is connected with gate drivers 1, n is an integer), the data line D1...Dm (m 〉=1, m is an integer) and the thin film transistor (TFT) 3 that are parallel to each other and are connected with source electrode driver 2.Sweep trace G1...Gn and data line D1...Dm insulation are intersected; Thin film transistor (TFT) 3 is positioned at the intersection of this sweep trace G1...Gn and data line D1...Dm, its grid 31 is connected with sweep trace G1...Gn, its source electrode 32 is connected with data line D1...Dm, its drain electrode 33 is connected with pixel electrode 6 with memory capacitance Cs 4, this pixel electrode 6 forms liquid crystal capacitance C1c 8 with public electrode 7, and the other end of this memory capacitance Cs 4 is connected with next bar sweep trace.
, be gate drivers 1 drive waveforms sequential synoptic diagram among Fig. 1 please together with reference to figure 2.Gate drivers 1 provides two kinds of different scanning voltages, is respectively V5 and V6.The V5 magnitude of voltage is the grid 31 that high voltage is used to open thin film transistor (TFT) 3, and V6 is the grid 31 that low-voltage is used to close thin film transistor (TFT) 3.When the grid 31 that is connected with sweep trace G1 is closed, voltage is dropped to voltage V6 from V5, simultaneously gate drivers 1 grid 31 that provides voltage V5 to open to be connected with sweep trace G2 is in like manner opened the grid 31 that is connected with sweep trace G2...Gn successively.With the resolution of SVGA (1024 * 768), the frame updating frequency of 60Hz is that example illustrates, and scope is the cycle of a frame (Frame) picture shown in arrow among the figure, is about 16.67ms.G1～Gn represents 768 outputs of driver 1 respectively, and cycle start-up time of grid 31 also is 16.67ms.Between 16.67ms, need respectively to allow G1-Gn totally 768 output lines open again in regular turn and close, so be assigned to the time that every line opens 16.67ms/768=21.7 μ s is only arranged.In 21.7 μ s times, source gate driver 2 is charged to required voltage with corresponding pixel electrode 6 again.The type of drive of gate drivers 1 is that second order drives, and promptly its output voltage only has two kinds of numerical value, is respectively the film crystal tube grid and opens voltage and close voltage.
But, the framework that is positioned at grid owing to memory capacitance is that to receive on next bar sweep trace be not to receive public voltage source to the storage capacitors other end, therefore after a certain sweep trace closed, be that next bar sweep trace is when opening, the change in voltage of next bar sweep trace can cause feed-trough voltage (FeedThrough) by 4 pairs of n one pixel electrodes of memory capacitance Cs, so the change in voltage that gate drivers 1 offers grid 31 can cause feed-trough voltage.Feed-trough voltage can cause the feedthrough effect, and promptly the output voltage range of source electrode driver 2 originally because the influence of feed-trough voltage causes the voltage range of pixel electrode 6 inconsistent with original expection, thereby can cause film flicker reduction picture quality.
[summary of the invention]
Cause the voltage range of pixel electrode inconsistent owing to the influence of feed-trough voltage in order to overcome prior art with original expection, thereby can cause that film flicker reduces the defective of picture quality, be necessary to provide a kind of voltage range that prevents the influence of feed-trough voltage and cause pixel electrode inconsistent and cause film flicker, reduce the liquid crystal display driving method and the liquid crystal display drive circuit of picture quality with original expection.
A kind of liquid crystal display driving method, be used for the drive thin film transistors LCD, this Thin Film Transistor-LCD comprises a plurality of sweep traces that are parallel to each other and a plurality of thin film transistor (TFT), this sweep trace is connected with the grid of this thin film transistor (TFT), form memory capacitance between next bar sweep trace of the drain electrode of this thin film transistor (TFT) and its grid corresponding scanning beam, this method comprises the steps:
Step 1: provide first voltage to the Thin Film Transistor-LCD n that is driven (n 〉=1, n is an integer) bar sweep trace, it is used to open the grid of the thin film transistor (TFT) that is connected with this n bar sweep trace;
Step 2: provide second voltage to the Thin Film Transistor-LCD n bar sweep trace that is driven, simultaneously provide first voltage to n+1 bar sweep trace, this second voltage is less than first voltage and anti-phase with it, is used to compensate the feed-trough voltage that the LCD memory capacitance that driven is produced;
Step 3: the n+1 bar sweep trace to the Thin Film Transistor-LCD sweep trace that is driven provides second voltage;
Step 4: provide tertiary voltage to the Thin Film Transistor-LCD n bar sweep trace that is driven; This tertiary voltage is less than first voltage and be used to close the grid of the thin film transistor (TFT) that is connected with n bar sweep trace;
Step 5: the n+1 bar sweep trace to the Thin Film Transistor-LCD sweep trace that is driven provides tertiary voltage.
A kind of liquid crystal display drive circuit, it comprises the driver element of a plurality of series connection, this each driver element comprises eight thin film transistor (TFT)s.
The transistorized grid of the first film is connected with first voltage source, and its source electrode is connected with the source electrode of the 3rd thin film transistor (TFT) and is connected with a tertiary voltage source, and its drain electrode is connected with the source electrode of second thin film transistor (TFT) and the grid of the 6th thin film transistor (TFT);
The grid of second thin film transistor (TFT) is connected as first input end with the grid of the 3rd thin film transistor (TFT), and its source electrode is connected with the first film transistor drain, and its drain electrode is connected and ground connection with the drain electrode of the 6th thin film transistor (TFT) with the 4th;
The grid of the 3rd thin film transistor (TFT) is connected with the grid of second thin film transistor (TFT), and its source electrode is connected with the transistorized source electrode of the first film, and its drain electrode is connected with the grid of the 7th thin film transistor (TFT) with the source electrode, the 5th of the 4th thin film transistor (TFT);
The grid of the 4th thin film transistor (TFT) is connected with the transistorized grid of the first film, and its source electrode is connected with the drain electrode of the 3rd thin film transistor (TFT), and its drain electrode is connected with the drain electrode of second thin film transistor (TFT);
The grid of the 5th thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT), and its source electrode is connected with the source electrode of the 7th thin film transistor (TFT) and is connected with one second voltage source, and its drain electrode is connected with the source electrode of the 6th thin film transistor (TFT) and as first output terminal;
The grid of the 6th thin film transistor (TFT) is connected with the first film transistor drain, and its source electrode is connected with the drain electrode of the 5th thin film transistor (TFT), and its drain electrode is connected and ground connection with the drain electrode of the 4th thin film transistor (TFT) with second;
The grid of the 7th thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT), the grid of the 5th thin-film electro crystalline substance, its source electrode is connected with the source electrode of the 5th thin film transistor (TFT) and with second voltage source, and its drain electrode is connected with the source electrode of the 8th thin film transistor (TFT) and as second output terminal;
The grid of the 8th thin film transistor (TFT) is as second input end, and its source electrode is connected with the drain electrode of the 7th thin film transistor (TFT) and as second output terminal, its drain electrode is connected with the 4th voltage source;
When the grid of the 6th thin film transistor (TFT) is opened, then the voltage of first output terminal output is 0 volt; When the grid of the 5th, the 7th thin film transistor (TFT) is opened, the voltage of first, second output terminal output is the voltage of second voltage source; When the grid of the 8th thin film transistor (TFT) is opened, the voltage of second output terminal output is the voltage of the 4th voltage source;
The first input end of first driver element receives the starting potential signal, second input end is used to receive the output voltage of second driver element that is attached thereto, first output terminal provides voltage to second driver element, and second output terminal provides scanning voltage to the LCD that is driven; The first input end of last driver element receives the output voltage of the last driver element that is attached thereto; The first input end of other driver element is used to receive the output voltage of the last driver element that is attached thereto, second input end is used to receive a back circuit output voltage that is attached thereto, first output terminal provides the first input end of voltage to a back circuit that is attached thereto, and second output terminal provides scanning voltage to the LCD that is driven respectively.
Driving method of the present invention is to utilize three rank driving voltages to reduce the influence of feedthrough effect, thereby so can reduce film flicker and improve picture quality.
[description of drawings]
Fig. 1 is a kind of schematic equivalent circuit of display panels of prior art.
Fig. 2 is a gate driver drive waveform sequential synoptic diagram.
Fig. 3 is a grid electrode drive circuit structure block diagram of the present invention.
Fig. 4 is the particular circuit configurations synoptic diagram of driver element among Fig. 3.
Fig. 5 is the drive waveforms sequential synoptic diagram of liquid crystal display driving method of the present invention.
Fig. 6 is that the effect of driving method of the present invention and prior art driving method compares synoptic diagram.
[embodiment]
Please refer to Fig. 3, is grid electrode drive circuit structure block diagram of the present invention.This gate driver circuit 11 is used for drive thin film transistors LCD (figure does not show), this Thin Film Transistor-LCD comprises a plurality of sweep traces that are parallel to each other and a plurality of thin film transistor (TFT), this sweep trace is connected with the grid of this thin film transistor (TFT), forms memory capacitance between next bar sweep trace of the drain electrode of this thin film transistor (TFT) and its grid corresponding scanning beam.This gate driver circuit 11 comprises driver element C1, C2...Cn (n 〉=1, n is an integer), this driver element C1, C2...Cn comprise two input end I1, I2 respectively, and two output terminal O1, O2 also are connected with the second voltage source PH2 with a low-voltage V2, the first voltage source PH1 respectively.This first voltage source PH1 is the different pulse voltage of the identical sequential of voltage with the second voltage source PH2.The input end I1 of driver element C1 is used to receive the starting potential signal, and input end I2 is used to receive the output voltage of driver element C2, and output terminal O1 provides the input end I1 of voltage to driver element C2, and output terminal O2 provides voltage to sweep trace G1.The input end I 1 of driver element C2...Cn-1 is used to receive the output voltage signal of last circuit, input end I2 is used to receive the output voltage of back one driver element, output terminal O1 provides the input end I1 of voltage to back one driver element, and output terminal O2 provides voltage to sweep trace G2...Gn respectively.When the input end I1 of driver element C1 received voltage, n output terminal O2 timesharing provided scanning voltage to sweep trace G2...Gn.
, be the particular circuit configurations synoptic diagram of driver element C1 among Fig. 3 please together with reference to figure 4.The particular circuit configurations of driver element C2, C3...Cn is identical with driver element C1.This driver element C1 comprises the first film transistor P1, the second thin film transistor (TFT) P2, the 3rd thin film transistor (TFT) P3, the 4th thin film transistor (TFT) P4, the 5th thin film transistor (TFT) P5, the 6th thin film transistor (TFT) P6, the 7th thin film transistor (TFT) P7 and the 8th thin film transistor (TFT) P8.The grid of this first film transistor P1 is connected with the first voltage source PH1, its source electrode is connected with the source electrode of the 3rd thin film transistor (TFT) P3 and is connected with tertiary voltage source V2, this tertiary voltage source V2 is a low-voltage, and the drain electrode of this first film transistor P1 is connected with the grid of the source electrode of the second thin film transistor (TFT) P2 and the 6th thin film transistor (TFT) P6.The grid of the second thin film transistor (TFT) P2 is connected as first input end I1 with the grid of the 3rd thin film transistor (TFT) P3, its source electrode is connected with the drain electrode of the first film transistor P1 and the grid of the 6th thin film transistor (TFT) P6, and its drain electrode is connected with the drain electrode of the 4th thin film transistor (TFT) P4, the 6th thin film transistor (TFT) P6 and ground connection.The grid of the 3rd thin film transistor (TFT) P3 is connected as first input end I1 with the grid of the second thin film transistor (TFT) P2, its source electrode is connected with the source electrode of the first film transistor P1, and its drain electrode is connected with the grid of source electrode, the 5th thin film transistor (TFT) P5 and the 7th thin film transistor (TFT) P7 of the 4th thin film transistor (TFT) P4.The grid of the 4th thin film transistor (TFT) P4 is connected with the grid of the first film transistor P1, and its source electrode is connected with the drain electrode of the 3rd thin film transistor (TFT) P3, and its drain electrode is connected with the drain electrode of the second thin film transistor (TFT) P2.The grid of the 5th thin film transistor (TFT) P5 is connected with the drain electrode of the 3rd thin film transistor (TFT) P3, its source electrode is connected with the source electrode of the 7th thin film transistor (TFT) P7 and is connected with the second voltage source PH2, and its drain electrode is connected with the source electrode of the 6th thin film transistor (TFT) P6 and as the first output terminal O1.The grid of the 6th thin film transistor (TFT) P6 is connected with the drain electrode of the first film transistor P1, its source electrode is connected with the drain electrode of the 5th thin film transistor (TFT) P5 and as the first output terminal O1, its drain electrode is connected with the drain electrode of the second thin film transistor (TFT) P2, the 4th thin film transistor (TFT) P4 and ground connection.The grid of the 7th thin film transistor (TFT) P7 is connected with the drain electrode of the 3rd thin film transistor (TFT) P3, the grid of the 5th thin film transistor (TFT) P5, its source electrode is connected with the source electrode of the 5th thin film transistor (TFT) P5 and with the second voltage source PH2, and its drain electrode is connected with the source electrode of the 8th thin film transistor (TFT) P8 and as the second output terminal O2.The grid of the 8th thin film transistor (TFT) P8 is as the second input end I2, and its source electrode is connected with the drain electrode of the 7th thin film transistor (TFT) P7 and as the second output terminal O2, its drain electrode is connected with the 4th voltage source V com, and the 4th voltage source V com is a public voltage source.When the grid of the 6th thin film transistor (TFT) P6 is opened, then the voltage of first output terminal O1 output is 0 volt; When the grid of the 5th thin film transistor (TFT) P5, the 7th thin film transistor (TFT) P7 is opened, the voltage of the first output terminal O1, second output terminal O2 output is the voltage of the second voltage source PH1; When the grid of the 8th thin film transistor (TFT) P8 is opened, the voltage of second output terminal O2 output is the voltage of the 4th voltage source V com.
Driving method of the present invention and gate driver circuit are to utilize three rank driving voltages to reduce the influence of feedthrough effect, thereby so can reduce film flicker and improve picture quality.Gate driver circuit of the present invention can design on the glass substrate of LCD, thereby the use that therefore can reduce gate driving IC can reduce cost.
Please refer to Fig. 5, is the drive waveforms sequential synoptic diagram of liquid crystal display driving method of the present invention, and it is the drive waveforms that offers gate drivers 11 among Fig. 3.Gate drivers 11 provides three kinds of different scanning voltages, is respectively V0, V1 and V2.The V1 magnitude of voltage is 10 volts, is used to open the grid of thin film transistor (TFT); The V0 magnitude of voltage is 0 volt, is used to close the grid of thin film transistor (TFT); The V2 magnitude of voltage is-2 volts, is used to compensate the feed-trough voltage that memory capacitance produces.Voltage V1 is provided at first for sweep trace Gi (1≤i≤n, n are integer), voltage V2 is provided for then sweep trace Gi, voltage V0 is provided at last sweep trace Gi; Provide voltage V2 constantly to provide voltage V1 for sweep trace Gi, voltage V2 is provided for then sweep trace Gi+1, provide voltage V0 to sweep trace Gi+1 after voltage V0 being provided for sweep trace Gi to sweep trace Gi+1.The voltage V2 of sweep trace Gi can compensate because when providing voltage V 1 to sweep trace Gi+1 it to be opened, the feed-trough voltage of generation is to the feedthrough effect of sweep trace pixel that Gi drives generation.
Please refer to Fig. 6, is that the effect of driving method of the present invention and prior art driving method compares synoptic diagram.Curve A is represented desirable pixel electrode voltage, and curve B represents that the pixel electrode voltage that adopts the present invention's three rank driving methods to obtain, curve C represent to adopt the voltage of the pixel electrode that prior art second order driving method obtains.As can be seen from Figure, curve B more approaches curve A than curve C, so its penetrance or chromaticity coordinates be more near ideal value, thereby the film flicker degree is lower.
Claims (5)
1. liquid crystal display driving method, be used for the drive thin film transistors LCD, this Thin Film Transistor-LCD comprises a plurality of sweep traces that are parallel to each other and a plurality of thin film transistor (TFT), this sweep trace is connected with the grid of this thin film transistor (TFT), form memory capacitance between next bar sweep trace of the drain electrode of this thin film transistor (TFT) and its grid corresponding scanning beam, this method comprises the steps:
Step 1: provide first voltage to the Thin Film Transistor-LCD n that is driven (n 〉=1, n is an integer) bar sweep trace, it is used to open the grid of the thin film transistor (TFT) that is connected with this n bar sweep trace;
Step 2: provide second voltage to the Thin Film Transistor-LCD n bar sweep trace that is driven, simultaneously provide first voltage to n+1 bar sweep trace, this second voltage is less than first voltage and anti-phase with it, is used to compensate the feed-trough voltage that the LCD memory capacitance that driven is produced;
Step 3: the n+1 bar sweep trace to the Thin Film Transistor-LCD sweep trace that is driven provides second voltage;
Step 4: provide tertiary voltage to the Thin Film Transistor-LCD n bar sweep trace that is driven; This tertiary voltage is less than first voltage and be used to close the grid of the thin film transistor (TFT) that is connected with n bar sweep trace;
Step 5: the n+1 bar sweep trace to the Thin Film Transistor-LCD sweep trace that is driven provides tertiary voltage.
2. liquid crystal display driving method as claimed in claim 1 is characterized in that: the magnitude of voltage of this first voltage is 10 volts, and the magnitude of voltage of second voltage is-2 volts, and this tertiary voltage magnitude of voltage is 0 volt.
3. liquid crystal display drive circuit, it comprises the driver element of a plurality of series connection, this each driver element comprises eight thin film transistor (TFT)s;
The transistorized grid of the first film is connected with first voltage source, and its source electrode is connected with the source electrode of the 3rd thin film transistor (TFT) and is connected with a tertiary voltage source, and its drain electrode is connected with the source electrode of second thin film transistor (TFT) and the grid of the 6th thin film transistor (TFT);
The grid of second thin film transistor (TFT) is connected as first input end with the grid of the 3rd thin film transistor (TFT), and source electrode is connected with the first film transistor drain, and drain electrode is connected and ground connection with the drain electrode of the 6th thin film transistor (TFT) with the 4th;
The grid of the 3rd thin film transistor (TFT) is connected with the grid of second thin film transistor (TFT), and its source electrode is connected with the transistorized source electrode of the first film, and its drain electrode is connected with the grid of the 7th thin film transistor (TFT) with the source electrode, the 5th of the 4th thin film transistor (TFT);
The grid of the 4th thin film transistor (TFT) is connected with the transistorized grid of the first film, and its source electrode is connected with the drain electrode of the 3rd thin film transistor (TFT), and its drain electrode is connected with the drain electrode of second thin film transistor (TFT);
The grid of the 5th thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT), and its source electrode is connected with the source electrode of the 7th thin film transistor (TFT) and is connected with one second voltage source, and its drain electrode is connected with the source electrode of the 6th thin film transistor (TFT) and as first output terminal;
The grid of the 6th thin film transistor (TFT) is connected with the first film transistor drain, and its source electrode is connected with the drain electrode of the 5th thin film transistor (TFT), and its drain electrode is connected and ground connection with the drain electrode of the 4th thin film transistor (TFT) with second;
The grid of the 7th thin film transistor (TFT) is connected with the drain electrode of the 3rd thin film transistor (TFT), the grid of the 5th thin-film electro crystalline substance, its source electrode is connected with the source electrode of the 5th thin film transistor (TFT) and with second voltage source, and its drain electrode is connected with the source electrode of the 8th thin film transistor (TFT) and as second output terminal;
The grid of the 8th thin film transistor (TFT) is as second input end, and its source electrode is connected with the drain electrode of the 7th thin film transistor (TFT) and as second output terminal, its drain electrode is connected with the 4th voltage source;
When the grid of the 6th thin film transistor (TFT) is opened, then the voltage of first output terminal output is 0 volt; When the grid of the 5th, the 7th thin film transistor (TFT) is opened, the voltage of first, second output terminal output is the voltage of second voltage source; When the grid of the 8th thin film transistor (TFT) is opened, the voltage of second output terminal output is the voltage of the 4th voltage source;
The first input end of first driver element receives the starting potential signal, second input end is used to receive the output voltage of second driver element that is attached thereto, first output terminal provides voltage to second driver element, and second output terminal provides scanning voltage to the LCD that is driven; The first input end of last driver element receives the output voltage of the last driver element that is attached thereto; The first input end of other driver element is used to receive the output voltage of the last driver element that is attached thereto, second input end is used to receive a back circuit output voltage that is attached thereto, first output terminal provides the first input end of voltage to a back circuit that is attached thereto, and second output terminal provides scanning voltage to the LCD that is driven respectively.
4. liquid crystal display drive circuit as claimed in claim 3 is characterized in that: this first voltage source is the different pulse voltage of the identical sequential of voltage with second voltage source, and this tertiary voltage source is a low-voltage source, and the 4th voltage source is a public voltage source.
5. liquid crystal display drive circuit as claimed in claim 3 is characterized in that: the magnitude of voltage of this first voltage is 10 volts, and the magnitude of voltage of second voltage is-2 volts, and this tertiary voltage magnitude of voltage is 0 volt.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101021025A CN100444236C (en) | 2005-12-03 | 2005-12-03 | Liquid crystal display driving method and driving circuit |
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| CNB2005101021025A CN100444236C (en) | 2005-12-03 | 2005-12-03 | Liquid crystal display driving method and driving circuit |
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| CN100444236C true CN100444236C (en) | 2008-12-17 |
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Cited By (1)
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| CN103745706A (en) * | 2013-12-31 | 2014-04-23 | 深圳市华星光电技术有限公司 | Three order-driven type array substrate line driving circuit |
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| CN101520583B (en) * | 2009-04-27 | 2012-03-21 | 友达光电股份有限公司 | Pixel structure, driving method thereof and driving method of display |
| CN101556785B (en) * | 2009-05-12 | 2011-02-09 | 友达光电股份有限公司 | Shared voltage compensating circuit and compensating method for liquid crystal display device |
| CN101587700B (en) * | 2009-06-26 | 2011-11-09 | 友达光电股份有限公司 | Liquid crystal display and method for driving same |
| CN102053433B (en) * | 2009-10-28 | 2013-03-20 | 无锡夏普电子元器件有限公司 | Liquid crystal display screen and driving method thereof |
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| CN102737590B (en) * | 2011-04-06 | 2015-09-16 | 青岛海信电器股份有限公司 | scan electrode driving method, system and liquid crystal display |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129034A (en) * | 1994-06-03 | 1996-08-14 | 精工爱普生株式会社 | Method of driving liquid crystal display device, liquid crystal display device, electronic machine, and drive circuit |
| JP2001003375A (en) * | 1999-06-18 | 2001-01-09 | Daikichi Suematsu | Surface design structure of sticking block and surface design structure of tightly connected sticking block |
| WO2004040539A1 (en) * | 2002-10-31 | 2004-05-13 | Koninklijke Philips Electronics N.V. | Line scanning in a display |
| JP2004258498A (en) * | 2003-02-27 | 2004-09-16 | Victor Co Of Japan Ltd | Liquid crystal display device |
| JP2004309843A (en) * | 2003-04-08 | 2004-11-04 | Seiko Epson Corp | Electrooptic device, method for driving electrooptic device, and electronic equipment |
| CN1653512A (en) * | 2002-04-18 | 2005-08-10 | Jps集团控股有限公司 | Low power LCD with gray shade driving scheme |
-
2005
- 2005-12-03 CN CNB2005101021025A patent/CN100444236C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129034A (en) * | 1994-06-03 | 1996-08-14 | 精工爱普生株式会社 | Method of driving liquid crystal display device, liquid crystal display device, electronic machine, and drive circuit |
| JP2001003375A (en) * | 1999-06-18 | 2001-01-09 | Daikichi Suematsu | Surface design structure of sticking block and surface design structure of tightly connected sticking block |
| CN1653512A (en) * | 2002-04-18 | 2005-08-10 | Jps集团控股有限公司 | Low power LCD with gray shade driving scheme |
| WO2004040539A1 (en) * | 2002-10-31 | 2004-05-13 | Koninklijke Philips Electronics N.V. | Line scanning in a display |
| JP2004258498A (en) * | 2003-02-27 | 2004-09-16 | Victor Co Of Japan Ltd | Liquid crystal display device |
| JP2004309843A (en) * | 2003-04-08 | 2004-11-04 | Seiko Epson Corp | Electrooptic device, method for driving electrooptic device, and electronic equipment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103745706A (en) * | 2013-12-31 | 2014-04-23 | 深圳市华星光电技术有限公司 | Three order-driven type array substrate line driving circuit |
| CN103745706B (en) * | 2013-12-31 | 2016-01-06 | 深圳市华星光电技术有限公司 | The array base palte horizontal drive circuit that three rank drive |
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| CN1979623A (en) | 2007-06-13 |
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