JP2004309843A - Electrooptic device, method for driving electrooptic device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrooptic device which realizes a bright display of even high definition with low power consumption, a method for driving an electrooptic device, and electronic equipment. <P>SOLUTION: The potential of a gate line to which a correcting capacitive element of each pixel is connected is varied after a data signal is written to correct a pixel potential of each pixel by a feedthrough voltage ΔV. Consequently, potential differences between respective scan lines Y1 to Ym and respective pixel electrodes become relatively small to suppress declination. One frame is divided into three subfields SF1, SF2, and SF3 having periods corresponding to respective bits of 3-bit gradation data. In cycles T of the subfield SF1 having the shortest period in one frame, an L or H data signal is written seven times to respective pixels to make a display with 2<SP>3</SP>gradations. Consequently, a holding period wherein pixel voltages written to the respective pixels in one frame are held up to next writing becomes short and drops of the pixel voltages in the holding period become small. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

ノーマリホワイトモードの場合、階調データ（０００）は一つの画素２５に階調度０の表示（白表示）をするためのデータであり、階調データ（１１１）は一つの画素２５に階調度７の表示（黒表示）をするためのデータである。また、階調データ（００１）〜（１１０）はそれぞれ、一つの画素２５に中間の階調度１〜６の表示をするためのデータである。
【００５３】
信号線駆動回路３４は、走査線Ｙ１〜Ｙｍが順に選択される各選択期間に、選択された走査線に接続された各画素にデータ信号として、下記の表１及び図５に示すようにＬ（電圧０）又はＨ（電圧Ｖ１）のいずれか一方を順に出力するようになっている。これにより、Ｌ又はＨのいずれか一方が、上記７回の各選択期間において、選択された走査線に接続された各画素２５の液晶容量３１と補正容量素子３２に、オン（導通状態）になったＴＦＴ２６を介して書き込まれる。そして、Ｌ（電圧０）又はＨ（電圧Ｖ１）のデータ信号が書き込まれた後にＴＦＴ２６がオフ（非導通状態）になると、各画素２５の液晶容量３１と補正容量素子３２に電圧０又は電圧Ｖ１の電荷が保持されるようになっている。
下記の表２は、上述した８種類の階調度に応じた階調データと、１フレームにおけるサブフィールドＳＦ１（１回目の選択期間）、ＳＦ２（２回目と３回目の各選択期間）及びＳＦ３（４回目〜７回目の各選択期間）で一つの画素２５に印加されるデータ信号との関係を示してある。
【００５４】
【表２】

例えば、図５（ａ）の階調データ（０００）で各画素２５に階調度０の表示をする場合、表２に示すように、サブフィールドＳＦ１（１回目の選択期間）、ＳＦ２（２回目と３回目の各選択期間）及びＳＦ３（４回目〜７回目の各選択期間）の７回の全ての選択期間でＬのデータ信号のみが各画素２５に書き込まれる。また、図５（ｂ）の階調データ（００１）で各画素２５に階調度１の表示をする場合、表２に示すように、１回目の選択期間にのみＨのデータ信号が書き込まれ、２回目〜７回目までの各選択期間にはＬのデータ信号が書き込まれる。以下同様に、図５（ｃ）〜（ｈ）の階調データ（０１０）〜（１１１）で各画素２５に階調度２〜７の表示をする場合、表２に示すように、７回の各選択期間でＬ又はＨのデータ信号が書き込まれるようになっている。
【００５５】
＜サブフィールド駆動による階調制御の動作説明＞
ここでは、一例として、ある１フレームで全ての画素２５に、図５（ｂ）の階調データ（００１）に基づき、階調度１の表示をする場合について説明する。
【００５６】
走査線駆動回路３３は、１フレームの最初に１番目の開始信号ＤＹが入力されると、図６（ａ）、（ｂ）及び（ｃ）に示す走査信号Ｇ１１〜Ｇｍ１を順に出力し、走査線Ｙ１〜Ｙｍを順に選択する（１回目の選択期間）。これにより、走査線Ｙ１〜Ｙｍのうち選択された一つの走査線に接続された各画素２５のＴＦＴ２６がオンになる。
【００５７】
この１回目の選択期間（サブフィールドＳＦ１の間）において、信号線駆動回路３４は、選択された一つの走査線に接続された各画素２５に表２に示すようにＨ（電圧Ｖ１）のデータ信号を順に出力する。これにより、その走査線に接続された各画素２５の液晶容量３１と補正容量素子３２に、データ信号として電圧Ｖ１がＴＦＴ２６を介してそれぞれ書き込まれる。
【００５８】
１回目の選択期間が終了して各ＴＦＴ２６がオフになると、各画素２５に書き込まれたデータ信号（電圧Ｖ１）が、次の選択期間（２回目の選択期間）になるまでの保持期間（上記周期Ｔ−選択期間ｈ）の間保持される。
【００５９】
１番目の開始信号ＤＹの入力時から周期Ｔが経過して２番目の開始信号ＤＹが入力されると、走査線駆動回路３３は、走査信号Ｇ１２〜Ｇｍ２を順に出力し、走査線Ｙ１〜Ｙｍを順に選択する。この２回目の選択期間、即ち図６に示すサブフィールドＳＦ２における最初の周期Ｔでは、信号線駆動回路３４は、選択される走査線Ｙ１〜Ｙｍの一つに接続された各画素２５にＬ（電圧０）のデータ信号を順に出力する。これにより、各画素２５の画素電極２９にデータ信号として電圧０がＴＦＴ２６を介してそれぞれ書き込まれる。２回目の選択期間が終了してＴＦＴ２６がオフになると、各画素２５の画素電極２９に書き込まれたデータ信号（電圧０）が、次の選択期間（３回目の選択期間）になるまでの前記保持期間の間保持される。
【００６０】
２番目の開始信号ＤＹの入力時から周期Ｔが経過して３番目の開始信号ＤＹが入力されると、走査線駆動回路３３は、走査信号Ｇ１３〜Ｇｍ３を順に出力し、走査線Ｙ１〜Ｙｍを順に選択する。この３回目の選択期間、即ち図６に示すサブフィールドＳＦ２における最初の周期Ｔでは、信号線駆動回路３４は、選択される走査線の一つに接続された各画素２５にＬ（電圧０）のデータ信号を順に出力する。これにより、各画素に電圧０がそれぞれ書き込まれる。３回目の選択期間が終了してＴＦＴ２６がオフになると、各画素２５に書き込まれた電荷（電圧０）が、次の選択期間（４回目の選択期間）になるまでの前記保持期間の間保持される。
【００６１】
この後、上記と同様に４番目〜７番目の開始信号ＤＹが周期Ｔの間隔で入力される毎に、走査線駆動回路３３は、走査信号Ｇ１４〜Ｇｍ４・・・走査信号Ｇ１７〜Ｇｍ７を順に出力し、４回目〜７回目の選択期間になる。これら４回目〜７回目の選択期間、即ちサブフィールドＳＦ３における１回目〜４回目の各周期Ｔではそれぞれ、選択される走査線の一つに接続された各画素にＬ（電圧０）のデータ信号がそれぞれ書き込まれる。
【００６２】
こうして、上記７回目の選択期間において、最後に選択される走査線Ｙｍに接続された各画素にＬのデータ信号を書き込むことにより、１画面を構成する全ての画素に階調度１の表示をさせて１画面を構成する動作（１フレーム周期）が終了する。
＜フィードスルー電圧の補正制御＞
また、本例の液晶表示装置では、各画素２５のＴＦＴ２６がオフする瞬間に画素電極２９の画素電極電位（以下、画素電位という。）が低下する上記フィードスルー電圧を補正する「フィードスルー電圧の補正制御」を行うようになっている。この補正制御を行うために、走査線Ｙ１〜Ｙｍのいずれか一つに接続されている各画素２５の補正容量素子３２は、図４に示すように、ゲート線（配線）４０を介して、ｍ行の走査線Ｙ１〜Ｙｍのうち１つ前に選択される前段（１行前）の走査線に接続されている。例えば、走査線Ｙｋ＋１と信号線Ｘ１〜Ｘｎの各交差部にある各画素２５の補正容量素子３２は、ゲート線４０を介して、１つ前に選択される前段の走査線である走査線Ｙｋに接続されている。
【００６３】
そして、制御回路３５は、上記「サブフィールド駆動による階調制御」により各画素２５にデータ信号を書き込んだ後、選択された走査線Ｙ１〜Ｙｍの一つに印加する各走査信号Ｇ１〜Ｇｍの電圧を変化させて、各画素の画素電位をフィードスルー電圧分だけ補正するようになっている。そのために、制御回路３５は、図７（ａ），（ｂ）に示すように、選択する一つの走査線、例えば走査線Ｙｋ或いはＹｋ＋１に印加する走査信号Ｇｋ，Ｇｋ＋１の電圧を、データ信号の書き込み後に、選択時の電圧Ｖ０から、基準値（例えば０Ｖ）より電圧Ｖ２だけ低い電圧値まで低下させる。そして、その低い電圧値を一定時間維持し、その後基準値に戻すように、制御回路３５は走査線駆動回路３３を制御するようになっている。その一定時間は、選択期間ｈと期間τの合計時間である。
【００６４】
このように構成された制御回路３５が、各画素２５の補正容量素子３２が接続されているゲート線４０の電位をＬ（電圧０）又はＨ（電圧Ｖ１）のデータ信号の各書き込み後に変化させて、各画素の画素電位をフィードスルー電圧ΔＶ分だけ補正する画素電圧補正手段に制御回路３５に相当する。
【００６５】
なお、第１行目の走査線Ｙ１にＴＦＴ２６のゲートがそれぞれ接続される各画素２５の補正容量素子３２については、第１行目の走査線Ｙ１に対する前段の走査線がないので、ダミーの走査線Ｙ０（図示省略）を設ける。走査線Ｙ１と信号線Ｘ１〜Ｘｎの各交差部にある各画素２５の補正容量素子３２を、ゲート線４０を介してダミーの走査線Ｙ０に接続する。そして、その走査線Ｙ０に他の走査線Ｙ１〜Ｙｍと同様の電圧波形の走査信号を印加する。或いは、ゲート線４０の電位をデータ信号の各書き込み後に変化させるための電圧波形、即ち基準値（例えば０Ｖ）より電圧Ｖ２だけ低い電圧値まで低下させ、その低い電圧値を一定時間維持し、その後基準値に戻すような電圧波形のみを印加するようにしてもよい。
【００６６】
このようなフィードスルー電圧の補正制御を行うことにより、選択された一つの走査線、例えば走査線Ｙｋ＋１に接続された各画素２５の画素電位は、プラスフィールド及びマイナスフィールドにおいてそれぞれ図７（ｃ）に示すように変化する。
【００６７】
プラスフィールドでは、例えば走査線Ｙｋ＋１の画素電位は、上記７回の選択期間に電圧Ｖ１（Ｈ）のデータ信号が書き込まれると＋Ｖ１になる。その書き込みが終了してＴＦＴ２６がオフする瞬間に（ｔ１時点）、その画素電位は電圧Ｖ１（＋Ｖ１）からフィードスルー電圧ΔＶｄだけ低下する。この後、ｔ１時点から期間τが経過すると（ｔ２時点）、走査線Ｙｋ＋１に接続された各画素の補正容量素子３２がゲート線４０を介して接続されている走査線Ｙｋに印加される走査信号Ｇｋの電位が前記低い電圧値から電圧Ｖ２だけ上昇して基準値に戻る。これにより、走査線Ｙｋ＋１に接続された各画素２５の画素電位が、電圧Ｖ１からフィードスルー電圧ΔＶｄだけ低下した電位からΔＶｕ１だけ上昇する（ｔ２時点）。この時点から選択期間ｈが経過すると（ｔ３時点）、走査線Ｙｋ＋１に印加される走査信号Ｇｋ＋１の電圧が電圧Ｖ２だけ上昇する。これにより、走査線Ｙｋ＋１に接続された各画素２５の画素電位が、さらにΔＶｕ２だけ上昇する。
【００６８】
一方、マイナスフィールドでは、例えば走査線Ｙｋ＋１の画素電位は、７回の選択期間にＨのデータ信号が書き込まれると−Ｖ１になり、その書き込みが終了してＴＦＴ２６がオフする瞬間に−Ｖ１からフィードスルー電圧ΔＶｄだけ低下する。この後、その低下した画素電位は、走査信号Ｇｋの電位が前記低い電圧値から電圧Ｖ２だけ上昇して基準値に戻ることによりΔＶｕ１だけ上昇し、さらに、走査信号Ｇｋ＋１の電圧が電圧Ｖ２だけ上昇する。これにより、その画素電位がさらにΔＶｕ２だけ上昇する。
【００６９】
このように各画素の画素電位を変化させるようになっているが，上記各電圧の変化量ΔＶｄ，ΔＶｕ１及びΔＶｕ２は、それぞれ下記の２式，３式及び４式で表される。
【００７０】
ΔＶｄ＝｛Ｃｔｆｔ／（Ｃｔｆｔ＋Ｃｈ＋Ｃｌｃ）｝×（Ｖ１＋Ｖ２）・・２式
ΔＶｕ１＝｛Ｃｈ／（Ｃｔｆｔ＋Ｃｈ＋Ｃｌｃ）｝×Ｖ２・・・３式
ΔＶｕ２＝｛Ｃｔｆｔ／（Ｃｔｆｔ＋Ｃｈ＋Ｃｌｃ）｝×Ｖ２・・・４式
ここで、Ｃｈは補正容量素子３２の容量である。この補正容量素子３２の容量は、上記液晶容量のリークを低減する保持容量であるとともに、フィードスルー電圧ΔＶｄを補正するための補正容量でもある。したがって、以下の説明で補正容量素子３２の容量Ｃｈを補正容量と呼ぶ。また、上記各２式〜４式ではそれぞれ単純化のために、Ｃｔｆｔはゲート電圧、ドレイン電圧に依存しないと仮定している。
【００７１】
フィードスルー電圧ΔＶｄを０にするには、
ΔＶｄ−ΔＶｕ１−ΔＶｕ２＝０を満足するように、即ち
Ｃｔｆｔ×Ｖ１−Ｃｈ×Ｖ２＝０ 或いは Ｖ１／Ｖ２＝Ｃｈ／Ｃｔｆｔを満足するように、電圧Ｖ２と補正容量Ｃｈとを設定する必要がある。
【００７２】
例えば、Ｖ１＝１１〜１５Ｖ、Ｃｔｆｔ＝１ｆＦ程度とすると、電圧Ｖ２をＶ２＝１．１〜１．５Ｖに設定するとともに、補正容量ＣｈをＣｈ＝１０ｆＦ程度に設定することにより、フィードスルー電圧ΔＶｄを０にすることができる。
【００７３】
なお、図６に示すように１フレームに７回の垂直走査を行なうが、各垂直走査の終了時から次の垂直走査開始時までの垂直帰線期間については図示を省略してある。また、走査線Ｙ１〜Ｙｍを順に選択する各選択期間に、選択された走査線に接続された各画素に順にデータ信号を書き込む水平走査期間の終了時から次の水平走査開始時までにも、必要に応じて水平帰線期間が設けられる。
【００７４】
また、図７に示す上記期間τは、フィードスルー電圧の補正がゲート線４０のなまりや電流供給能力不足で不十分になるのを避けるために設けてあるが、特にτの長さを特定の値にする必要はない。期間τを選択期間ｈと同じ長さにしてもよい。この場合、データ信号の各書き込み終了時から選択期間ｈと同じ長さの期間τ（τ＝ｈ）が経過したタイミングで走査信号の電圧を電圧Ｖ２だけ上昇すればよく、回路構成が簡単になる。また、期間τ＝０でも問題がなければ、τ＝０とすることにより回路構成が更に簡単になる。
【００７５】
以上のように構成された第１実施形態によれば、以下の作用効果を奏する。
（イ）サブフィールド駆動により、各画素２５に２^３階調（８階調）の階調表示、即ち階調度０〜階調度７の階調表示を行うことができる。
【００７６】
（ロ）そのサブフィールド駆動では、１フレームを３ビットの階調データの各ビットに応じた長さの期間を有する３つのサブフィールドＳＦ１、ＳＦ２及びＳＦ３に分割する。３つのサブフィールドＳＦ１、ＳＦ２及びＳＦ３は、１：２：４の比率の期間（時間長）に設定される。そして、１フレームに、３つのサブフィールドのうち期間が最短のサブフィールドＳＦ１の周期Ｔで、図５に示す階調データに基づき各画素２５にＬ（電圧０）又はＨ（電圧Ｖ１）のデータ信号を、上記表２に示すように書き込み２３階調の表示を行う。
【００７７】
このような階調制御では、フレーム周波数を６０Ｈｚとすると、フレーム周期が１／６０秒（ｓｅｃ）である１フレームに、各画素２５へのデータ信号の書き込みを周期Ｔ毎に７回（２３−１回）行うことになる。これにより、１フレームにおいて各画素２５に書き込んだデータ信号の電圧（画素電圧）を次の書き込み時まで保持する保持期間が通常の駆動方式よりも１／７だけ短くなり、その保持期間中における画素電圧の電圧低下量を小さくすることができる。例えば、上述したように、画素ピッチが２００ｐｐｉ、１０００ｐｐｉになり、液晶容量Ｃｌｃが１／４、１／１００となり、保持期間中の電圧低下量が４倍、１００倍となるような場合に、２^ＮのＮを適宜大きな値に設定することで、その電圧低下量を抑えることが可能になる。そのため、スイッチング素子のリーク電流を小さくして画素電圧の電圧低下量を小さくするために、各画素２５に設けられる補正容量素子３２（保持容量）の保持容量（上記１式のＣｓｔ）を大きくする必要がない。これにより、コントラスト低下、開口率低下などの問題が発生するのを抑制しつつ、画素ピッチの小さい高精細な表示でかつ明るい表示が得られる。
【００７８】
（ハ）上述したフィードスルー電圧の補正制御を行うことにより、各画素２５のＴＦＴ２６がオフする瞬間に画素電位が低下するフィードスルー電圧を補正することができる。これにより、各走査線Ｙ１〜Ｙｍと各画素電極２９の電位差が相対的に小さくなるため、ディスクリネーションが抑えられ、コントラストや開口率が向上し、明るい表示が得られる。こうして、ディスクリネーションが抑えられるとともに、上記（ロ）で説明したように保持期間中における画素電圧の電圧低下量を小さくすることができるので、高精細でも、低消費電力でかつ明るい表示を実現することができる。
【００７９】
（ニ）フィードスルー電圧の補正制御では、制御回路３５は、図７（ａ），（ｂ）に示すように、選択する一つの走査線、例えば走査線Ｙｋ或いはＹｋ＋１に印加する走査信号Ｇｋ，Ｇｋ＋１の電圧を、Ｌ又はＨのデータ信号の各書き込み後に、選択時の電圧Ｖ０から、基準値（例えば０Ｖ）より電圧Ｖ２だけ低下させる。そして、その低い電圧値を一定時間維持し、その後基準値に戻すように、制御回路３５は走査線駆動回路３３を制御するようになっている。そのため、各走査線Ｙ１〜Ｙｍに、各画素２５の画素電位をフィードスルー電圧分だけ補正する電圧波形の信号を供給するように構成すればよく、フィードスルー電圧を補正するために特別に配線を設ける必要がなく、電気的構成の変更が僅かですむ。
【００８０】
（ホ）各画素２５に設けるスイッチング素子としてＮチャンネルのＴＦＴ２６を用いている。この場合、前記画素電圧補正手段としての制御回路３５は、図７（ｃ）に示すように、各画素２５の画素電位をフィードスルー電圧ΔＶｄだけプラス側に補正するようにしている。これにより、各スイッチング素子としてＮチャンネルのＴＦＴ２６を用いる場合に、各画素２５の画素電位をフィードスルー電圧分だけ補正することができる。
【００８１】
［第２実施形態］
次に、本発明の第２実施形態に係る液晶表示装置を図８〜図１０に基づいて説明する。なお、この実施形態の説明において、上記第１実施形態と同様の部材及び信号には、同じ符号を使って重複した説明を省略する。
【００８２】
この第２実施形態は、上記サブフィールド駆動による階調制御を行う点では上記第１実施形態と同じであるが、上記フィードスルー電圧の補正制御を行うのに、各走査線Ｙ１〜Ｙｍにそれぞれ対応する複数の補正容量配線４_１１〜４_１ｍ（図９及び図１０参照）を個別に接続してある点で第１実施形態とは異なる。
【００８３】
図８では補正容量配線４_１１〜４_１ｍのうち、補正容量配線４_１ｋと４_１ｋ＋１のみを示している。これらの補正容量配線４_１１〜４_１ｍのうち選択される一つの走査線に対応する補正容量配線には、制御回路３５により制御される補正容量配線用の駆動回路（図示省略）から図９（ａ）〜（ｃ）及び図１０（ａ），（ｂ）に示す電圧信号Ｓが出力されるようになっている。このように構成された制御回路３５と補正容量配線用の駆動回路（図示省略）が、上記画素電圧補正手段に相当する。
【００８４】
その電圧信号Ｓは、各走査線Ｙ１〜Ｙｍが順に選択される前或いはその選択時とほぼ同時に、基準値（例えば０Ｖ）より電圧Ｖ２だけ低い電圧値まで低下し、その低い電圧値が一定時間（期間τ１＋期間τ２）維持され、その後基準値に戻るように変化する。期間τ２は、各選択期間の終了時から、基準値に戻るまでの期間である。
【００８５】
本実施形態のフィードスルー電圧の補正制御により、選択された一つの走査線、例えば走査線Ｙｋ＋１に接続された各画素２５の画素電位は、プラスフィールド及びマイナスフィールドにおいてそれぞれ図１０（ｃ）に示すように変化する。
【００８６】
プラスフィールドでは、例えば走査線Ｙｋ＋１の画素電位は、上記７回の選択期間におけるデータ信号の書き込みが終了してＴＦＴ２６がオフする瞬間に＋Ｖ１からフィードスルー電圧ΔＶｄだけ低下する。この後、期間τ２が経過すると、走査線Ｙｋ＋１に接続された各画素の補正容量素子３２´に補正容量配線４１ｋ＋１を介して供給されるの電位が前記低い電圧値から電圧Ｖ２だけ上昇して基準値に戻る。これにより、走査線Ｙｋ＋１に接続された各画素２５の画素電位が、＋Ｖ１からフィードスルー電圧ΔＶｄだけ低下した電位からΔＶｕだけ上昇する。
【００８７】
マイナスフィールドにおいても同様に、データ信号の書き込み終了後、期間τ２が経過すると、走査線Ｙｋ＋１に接続された各画素２５の画素電位が、−Ｖ１からフィードスルー電圧ΔＶｄだけ低下した電位からΔＶｕだけ上昇する。
【００８８】
このように各画素の画素電位を変化させるようになっているが、上記各電圧の変化量ΔＶｄ及びΔＶｕは、それぞれ下記の５式及び６式で表される。
ΔＶｄ＝｛Ｃｔｆｔ／（Ｃｔｆｔ＋Ｃｈ＋Ｃｌｃ）｝×Ｖ１・・５式
ΔＶｕ＝｛Ｃｈ／（Ｃｔｆｔ＋Ｃｈ＋Ｃｌｃ）｝×Ｖ２・・・６式
ここで、Ｃｈは補正容量素子３２´の補正容量である。また、上記各５式及び６式ではそれぞれ単純化のために、Ｃｔｆｔはゲート電圧、ドレイン電圧に依存しないと仮定している。
【００８９】
フィードスルー電圧ΔＶｄを０にするには、
ΔＶｄ−ΔＶｕ＝０を満足するように、即ち
Ｃｔｆｔ×Ｖ１−Ｃｈ×Ｖ２＝０ 或いは
Ｖ１／Ｖ２＝Ｃｈ／Ｃｔｆｔを満足するように、電圧Ｖ２と補正容量Ｃｈとを設定する必要がある。
【００９０】
例えば、Ｖ１＝１１〜１５Ｖ、Ｃｔｆｔ＝１ｆＦ程度とすると、電圧Ｖ２をＶ２＝１．１〜１．５Ｖに設定するとともに、補正容量ＣｈをＣｈ＝１０ｆＦ程度に設定することにより、フィードスルー電圧ΔＶｄを０にすることができる。したがって、補正容量Ｃｈを小さくすることができる。
【００９１】
このように構成された第２実施形態によれば、以下の作用効果を奏する。
（ヘ）フィードスルー電圧の補正制御を行うのに、各走査線Ｙ１〜Ｙｍにそれぞれ対応する複数の補正容量配線４_１１〜４_１ｍ（図９及び図１０参照）を個別に接続してある。これにより、各画素２５の画素電位をフィードスルー電圧分だけ個別に補正することができる。
【００９２】
［第３実施形態］
次に、本発明の第３実施形態に係る液晶表示装置を図１１に基づいて説明する。
【００９３】
この第３実施形態では、上記フィードスルー電圧の補正制御をゲート線（配線）４０を使って行う点で上記第１実施形態と同じであるが、上記サブフィールド駆動による階調制御を行わない点で上記第１実施形態とは異なる。
【００９４】
この第３実施形態では、制御回路３５は、各画素２５の画素電極２９に階調に応じた電圧のデータ信号を書き込むアナログ階調制御を行う。また、制御回路３５は、各画素２５の画素電極２９へのデータ信号の書き込みを１２０Ｈｚ以上のフレーム周波数、例えば通常の６０Ｈｚの８倍である４８０Ｈｚのフレーム周波数で行うように、走査線駆動回路３３及び信号線駆動回路３４を制御するようになっている。
【００９５】
このように構成された第３実施形態によれば、以下の作用効果を奏する。
（ト）各画素２５の画素電極２９へのデータ信号の書き込みを４８０ＨＺのフレーム周波数で行うので、フレーム周期が短くなる。即ち、フレーム周期を通常のフレーム周期（１／６０ｓｅｃ）の１／８（１／４８０ｓｅｃ）にすることができる。こうしてフレーム周期が短くなるので、各画素２５の画素電極２９に書き込んだデータ信号（画素電圧）を次の書き込み時まで保持する保持期間が短くなり、その保持期間中における画素電圧の電圧低下量を小さくすることができる。そのため、その電圧低下量を小さくするために、各画素２５に設けられる補正容量素子３２の保持容量を大きくする必要がなく、フリッカ、焼き付き、コントラスト低下、開口率低下などの問題が発生するのを抑制しつつ、画素ピッチの小さい高精細な表示が得られる。したがって、高精細でも、低消費電力でかつ明るい表示を実現することができる。
【００９６】
［第４実施形態］
次に、本発明の第４実施形態に係る液晶表示装置を図１２に基づいて説明する。
【００９７】
この第４実施形態では、上記フィードスルー電圧の補正制御を、各走査線Ｙ１〜Ｙｍにそれぞれ対応する複数の補正容量配線４_１１〜４_１ｍ（図９及び図１０参照）を使って行う点で上記第２実施形態と同じであるが、上記サブフィールド駆動による階調制御を行わない点で第２実施形態とは異なる。
【００９８】
この第４実施形態では、制御回路３５は、各画素２５に階調に応じた電圧のデータ信号を書き込むアナログ階調制御を行う。また、制御回路３５は、各画素２５へのデータ信号の書き込みを１２０ＨＺ以上のフレーム周波数、例えば通常の６０Ｈｚの８倍である４８０Ｈｚのフレーム周波数で行うように、走査線駆動回路３３及び信号線駆動回路３４を制御するようになっている。したがって、上記第３実施形態と同様に上記作用効果（ト）を奏する。
【００９９】
［電子機器］
次に、上記各実施形態で説明した液晶表示装置の液晶表示パネル２１を用いた電子機器について説明する。液晶表示パネル２１は、図１３に示すようなモバイル型のパーソナルコンピュータに適用できる。図１３に示すパーソナルコンピュータ７０は、キーボード７１を備えた本体部７２と、液晶表示パネル２１を用いた表示ユニット７３とを備えている。この表示ユニット７３に用いた液晶表示パネル２１では、高精細でも、低消費電力でかつ明るい表示を実現することができる。
【０１００】
［変形例］
なお、この発明は以下のように変更して具体化することもできる。
・上記第１実施形態において、上述したサブフィールド駆動による階調制御に代えて、サブフィールド駆動による階調制御を次のように行う構成にも本発明は適用可能である。制御回路３５は、１フレームを同じ長さの期間（周期Ｔ）を有する２^Ｎ−１個のサブフィールドに分割し、サブフィールド毎に、上記階調データに基づき各画素に２値の電圧のいずれか一方を書き込み２^Ｎ階調の表示を行うように、走査線駆動回路３３及び信号線駆動回路３４を制御する。下記の表３は、一例として２^３階調の表示を行う場合における８種類の階調データと、２^３−１（＝７）個のサブフィールドＳＦ１〜ＳＦ７毎に行う１回目〜７回目の各選択期間で一つの画素２５に印加されるデータ信号との関係を示してある。
【０１０１】
【表３】

例えば、階調データ（０００）で各画素２５に階調度０の表示をする場合、表３に示すように、サブフィールドＳＦ１（１回目の選択期間）〜ＳＦ７（７回目の選択期間）の各選択期間でＬのデータ信号のみが各画素２５に書き込まれる。また、階調データ（００１）で各画素２５に階調度１の表示をする場合、表３に示すように、サブフィールドＳＦ１でのみＨのデータ信号が書き込まれ、サブフィールドＳＦ２〜ＳＦ７の各選択期間にはＬのデータ信号が書き込まれる。以下同様に、階調データ（０１０）〜（１１１）で各画素２５に階調度２〜７の表示をする場合、表３に示すように、Ｌ又はＨのデータ信号が書き込まれるようになっている。このようなサブフィールド駆動による階調制御によって、上記第１実施形態と同様に上記作用効果（ロ）を奏することができる。
【０１０２】
・上記第１実施形態では、２^３階調（２^ＮのＮ＝３で、８階調）の階調表示、即ち階調度０〜階調度７の階調表示を行う構成であるが、Ｎを４の値に適宜に設定して２^Ｎ階調の表示、即ち階調度０〜階調度２^Ｎ−１の階調表示を行う構成にも本発明は適用される。
【０１０３】
・上記第１実施形態では、フレーム周波数を６０Ｈｚとしているが、フレーム周波数をその２倍（１２０Ｈｚ）以上とする液晶表示装置において、上記サブフィールド駆動による階調制御を行う構成にも本発明は適用可能である。この場合、各画素２５に書き込んだデータ信号の電圧（画素電圧）を次の書き込み時まで保持する保持期間が上記第１実施形態よりも更に短くなるので、さらに高精細で明るい表示を実現することができる。
【０１０４】
・上記第３及び第４実施形態では、フレーム周波数を４８０Ｈｚとしたが、これに限るものではなく、１２０Ｈｚでもよい。
・上記第１実施形態では、１フレーム毎に共通電極３０の電位を反転させるようにしているが、１水平走査期間毎にその電位を反転させるように構成する場合にも本発明は適用可能である。
【０１０５】
・上記第１実施形態では、液晶を反転駆動するのに、共通電極３０の電位を低い電位と高い電位との間で１フレーム毎に反転させるようにしているが、他の方法で液晶を反転駆動する場合にも本発明は適用可能である。
【０１０６】
・上記第１実施形態では、走査線Ｙ１〜Ｙｍを駆動するための左右２つの走査線駆動回路（Ｙドライバー）３３，３３を設けてあるが、走査線駆動回路３３を一つ設けた構成にも本発明は適用可能である。
【０１０７】
・上記各実施形態では、走査線駆動回路３３、信号線駆動回路３４及び制御回路３５は、例えば図１において素子基板２２上に内蔵されているように記載されているが、これに限るものではない。例えば、ＣＯＧでＩＣを図１の回路３３〜３５に実装してもよいし、内蔵を行わずにＴＡＢ等でＩＣを接続してもよい。また、制御回路３５は外部回路基板上に設けてもよい。
【０１０８】
・上記各実施形態では、ＴＮ（Ｔｗｉｓｔｅｄ Ｎｅｍａｔｉｃ）型の液晶２４を用いている。しかし、液晶２４として１８０°以上のねじれ配向を有するＳＴＮ（Ｓｕｐｅｒ Ｔｗｉｓｔｅｄ Ｎｅｍａｔｉｃ）型、ＢＴＮ（Ｂｉ−ｓｔａｂｌｅ Ｔｗｉｓｔｅｄ Ｎｅｍａｔｉｃ）型、強誘電型等のメモリ性を有する双安定型、高分子分散型、ゲストホスト型等を含めて、周知なものを広く用いることができる。
【０１０９】
・上記各実施形態において、液晶２４として非メモリ形（単安定型）のものを用いるのが好ましい。メモリ形の液晶はリーク電流の影響を保持に関して受けないが、非メモリ形の液晶であるとリーク電流の影響を受けるので、液晶２４として非メモリ形のものを用いる場合に特に有効となる。
【０１１０】
・上記各実施形態で用いたＴＦＴ２６は、ａ−Ｓｉ（アモルファスシリコン：非晶質シリコン）形の薄膜トランジスタ、ｐ−Ｓｉ（ポリシリコン）形の薄膜トランジスタ、或いは、単結晶シリコン、ＳｉＧｅを用いたひずみシリコン、他の半導体材料を用いたものであってもよい。
【０１１１】
・上記各実施形態では、各画素のスイッチング素子として３端子スイッチング素子であるＴＦＴを用いているが、これに代えてＴＦＤ（Ｔｈｉｎ Ｆｉｌｍ Ｄｉｏｄｅ）のような２端子スイッチング素子を用いたアクティブマトリクス型液晶表示パネルにも本発明は適用可能である。なお、２端子スイッチング素子を用いる場合には、素子基板上にある各画素の画素電極と液晶を介して対向電極を対向基板側に設け、この対向電極を走査線ごと分割する。そして、素子基板上にある信号線と対向基板上にある対向電極（走査線）とが空間的に交差する個所に対応してＴＦＤのような２端子スイッチング素子を素子基板側に配置する。
【０１１２】
・上記各実施形態では、電気光学装置を液晶表示装置として説明したが、本発明はこれに限るものではなく、液晶以外の電気光学物質を用いた電気光学装置及び該電気光学装置を備えた電子機器に対しても適用可能である。例えば、本発明を有機ＥＬ素子などの発光素子を用いる電気光学装置に適用する場合、各画素に書き込む「データ信号」とは、各画素の発光素子を駆動する駆動用トランジスタのゲートに印加される電圧をいう。
【０１１３】
・液晶表示装置の液晶表示パネル２１は、図１３に示すようなパーソナルコンピュータに限らず、携帯電話、デジタルカメラ等の各種の電子機器に適用できる。
【０１１４】
・上記各実施形態において、走査線駆動回路３３は、走査線Ｙ１〜Ｙｍを順次に選択する垂直走査を、垂直走査開始時にＨｉ（Ｈレベル）の走査方向切換え信号が入力されたときには上から順に行うとともに、Ｌｏｗ（Ｌレベル）の走査方向切換え信号が入力されたときには下から順に行うようになっている。こうした構成は、本発明をプロジェクター用Ｌ／Ｖ（ライトバルブ）に適用して、スクリーンに投写する場合に有効になる。
【図面の簡単な説明】
【図１】第１実施形態に係る液晶表示装置の液晶表示パネルを示す平面図。
【図２】図１の液晶表示パネルの断面を一部破断して示す断面図。
【図３】液晶表示装置の駆動回路の電気的構成を示す概略構成図。
【図４】液晶表示パネルの電気的等価回路の一部を示す回路図。
【図５】（ａ）〜（ｈ）は階調データと画素に印加されるデータ信号の関係を示す波形図。
【図６】（ａ）〜（ｃ）は走査信号の波形図。
【図７】（ａ），（ｂ）は図６と同様の波形の一部を拡大して示す波形図で、（ｃ）は画素電圧の波形図。
【図８】第２実施形態における駆動回路の一部の等価回路を示す回路図。
【図９】（ａ）〜（ｃ）は走査信号と補正容量配線の信号を示す波形図。
【図１０】（ａ），（ｂ）は図９と同様の波形の一部を拡大して示す波形図で、（ｃ）は画素電圧の波形図。
【図１１】（ａ）〜（ｃ）は第３実施形態における走査信号の一部を拡大して示す波形図。
【図１２】（ａ）〜（ｃ）は第４実施形態における走査信号の一部を拡大して示す波形図。
【図１３】液晶表示装置を用いたパーソナルコンピュータを示す斜視図。
【図１４】従来例についての説明図。
【符号の説明】
τ，τ２…期間、Ｖ０，Ｖ１，Ｖ２…電圧、Ｔ…周期、Ｙ０，Ｙ１〜Ｙｍ…走査線、Ｃｌｃ，３１…液晶容量、ＳＦ１〜ＳＦ７…サブフィールド、Ｘ１〜Ｘｎ，３６，３７…信号線、２４…電気光学物質としての液晶、２５…画素、２６…スイッチング素子としての薄膜トランジスタ（ＴＦＴ）、２９…画素電極、３０…対向電極としての共通電極、３２…容量素子としての補正容量素子、４０…ゲート線（配線）、４１１〜４１ｍ…補正容量配線。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus.
[0002]
[Prior art]
2. Description of the Related Art As a conventional electro-optical device, there is known an active matrix type liquid crystal display device in which a thin film transistor (hereinafter, referred to as a “TFT”) is provided in each pixel so as to correct a feed-through voltage. (For example, see Patent Document 1). This “feedthrough voltage” refers to a voltage at which the pixel electrode potential of each pixel decreases at the moment when the TFT of each pixel is turned off. Such feed-through characteristics are caused by the parasitic capacitance Cgs between the gate and the source of the TFT. That is, in each pixel, the electric charges charged in the liquid crystal capacitance Clc and the storage capacitances Cs and Cgs when the TFT is turned on are redistributed to the respective capacitances at the moment when the TFT is turned off. The potential decreases by feed-through voltage ΔV (see feed-through voltage ΔV1 in FIG. 14).
[0003]
In the related art of Patent Document 1, in order to correct a feedthrough voltage, a first potential Vdd of a high voltage and a second potential VEE1 serving as a reference voltage at a low voltage are used as selection signals for each scanning line. And a lower third potential VEE2. That is, the selection signal waveform supplied to each scanning line rises from the second potential VEE1, holds the first potential Vdd for one horizontal scanning period, then drops to the third potential VEE2, and reduces this potential by two horizontal potentials. After the scanning period is maintained, the potential returns to the second potential, and this potential is maintained until writing of the next frame.
[0004]
[Patent Document 1]
JP-A-6-273720
[0005]
[Problems to be solved by the invention]
By the way, in the related art of Patent Document 1, by correcting the feedthrough voltage, each pixel is provided with a plus field for applying a positive signal to each pixel and a minus field for applying a negative signal to each pixel. The difference in polarity of the applied voltage is reduced, and flicker and image sticking are suppressed. In addition, since the potential difference between the signal line and the pixel electrode is relatively reduced by correcting the feedthrough voltage, disclination is suppressed, and the contrast and the aperture ratio are improved. The term “declination” as used herein refers to a defect such as a display defect due to the arrangement of liquid crystal molecules being disturbed by the influence of an adjacent pixel potential. As the defect, for example, light loss occurs in a normally white mode, and light leakage occurs in a normally black mode. Such a declination is also suppressed by correcting the feedthrough voltage.
[0006]
Such an effect is confirmed in a large pixel of 13 inches XGA class (pixel having a pixel pitch of 254 μm) used in a notebook computer or a monitor, for example. However, it becomes a high-definition (200 ppi (pixel pitch 125 μm or more)) liquid crystal display device or a projector L / V (light valve) of about 1000 ppi (pixel pitch 25 μm) required in recent markets. Therefore, a new problem has arisen that the liquid crystal capacitance itself becomes small, and it becomes difficult to hold the pixel voltage until the next writing. This is because although the amount of leakage current of the TFT is constant, the leakage current becomes relatively large because the pixel becomes small and the liquid crystal capacitance becomes small, and the voltage drop ΔV3 during the holding period (see FIG. 14) becomes large. Arises. FIG. 14 shows that the pixel voltage written to one pixel in the plus field and the minus field decreases by the feed-through voltage ΔV1, and further, during the holding period from the end of the selection period to the start of the selection period of the next frame. It shows a state of dropping. In FIG. 14, curves A and B show the voltage drop during the holding period in the case of the above 13 inch XGA class notebook personal computer, etc., and curves C and D show the holding in the case of the above high definition liquid crystal display device. Each shows a voltage drop during the period. Here, “ppi” is a unit of definition and indicates the number of pixels per inch.
[0007]
As described above, in the prior art of Patent Document 1, when used in the above-described high-definition liquid crystal display device or L / V for projector, the liquid crystal capacitance itself becomes small, and as shown in FIG. There was a problem that it became difficult to hold. This is because the leak current of the TFT is constant, but the pixel becomes smaller and the voltage drop ΔV (ΔV3 in FIG. 14) during the holding period becomes larger.
[0008]
This is represented by the following equation.
ΔV = Ileak · T1 / (Clc + Cst + Ctft) (1)
Here, Ileak is a leakage current of the TFT, T1 is a holding period, Clc is a liquid crystal capacity, Cst is a holding capacity, and Ctft is a parasitic capacity between a gate and a source of the TFT.
[0009]
Here, as an example, an 11 inch XGA liquid crystal display device using a polysilicon TFT will be described. In this liquid crystal display device, Clc = 330 fF (fetom farad), Cst = 100 fF, Ctft = 1 fF, and the liquid crystal capacitance Clc is sufficiently large and the above problem does not occur. However, when the pixel pitch becomes 200 ppi or 1000 ppi, the liquid crystal capacitance Clc becomes 1/4 or 1/100, and the voltage drop ΔV during the holding period becomes 4 times or 100 times. This causes problems such as flicker, burn-in, reduced contrast, and reduced aperture ratio. If an attempt is made to increase the storage capacitance Cst to solve this problem, the aperture ratio becomes extremely small, and only a dark display can be obtained. This problem is particularly noticeable in the case of L / V for projectors.
[0010]
Further, even in the high-definition liquid crystal display device and the L / V for projector, low power consumption and bright display are required, and it is not allowed to increase the storage capacitance Cst in order to realize those requirements. In addition, the present inventors have studied reducing the leak current Ileak of the TFT. However, since the TFT is made of polysilicon and has many defects, there is a limit to the reduction of the leak current. Furthermore, since the defect varies for each TFT, the variation in leak current is large, resulting in a rough display.
[0011]
Therefore, the present invention has been made in view of such a conventional problem, and an object thereof is to provide an electro-optical device, a driving method for an electro-optical device, and a display device that can realize a bright display with high definition even with low power consumption. It is to provide an electronic device.
[0012]
[Means for Solving the Problems]
The electro-optical device according to the aspect of the invention includes a plurality of switching elements arranged in a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines. An electro-optical device configured to write a signal to a pixel electrode of each pixel, comprising: a correction capacitor provided corresponding to the switching element; and a wiring to which the correction capacitor is connected. Writing a signal to a pixel electrode of a pixel is performed at a frame frequency of 120 Hz or more, and changing the potential of the wiring after writing the signal to the pixel electrode changes the pixel electrode potential of each pixel by a feedthrough voltage. The gist is that only the correction is made.
[0013]
According to this, the potential of the wiring to which the correction capacitance element of each pixel is connected is changed after the signal is written to the pixel electrode of each pixel, so that the pixel electrode potential of each pixel is corrected by the feedthrough voltage. be able to. Accordingly, the potential difference between the scanning line and the pixel electrode becomes relatively small, so that disclination is suppressed, the contrast and the aperture ratio are improved, and a bright display is obtained. In addition, since the writing of the signal to the pixel electrode of each pixel is performed at a frame frequency of 120 Hz or more, the frame period is shortened. For example, if the frame frequency is set to 480 Hz, which is eight times the normal 60 Hz, the frame period can be reduced to 1/8 (1/480 sec) of the normal frame period (1/60 sec). Since the frame period is shortened in this manner, the holding period (T1 in the above equation) for holding the voltage (pixel voltage) of the signal written to the pixel electrode of each pixel until the next writing is shortened. The amount of voltage drop (ΔV in the above equation) can be reduced. Therefore, it is not necessary to increase the storage capacitance (Cst in the above formula 1) of the capacitor provided in each pixel in order to reduce the leakage current of the switching element and reduce the amount of voltage drop of the pixel voltage. As a result, a high-definition display with a small pixel pitch and a bright display can be obtained while suppressing the occurrence of problems such as a decrease in contrast and a decrease in aperture ratio. In this manner, disclination can be suppressed and the amount of decrease in the pixel voltage during the holding period can be reduced, so that a bright display with low power consumption and high definition can be realized.
[0014]
The electro-optical device according to the aspect of the invention includes a plurality of switching elements arranged in a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines. An electro-optical device configured to write a signal to each pixel, comprising: a correction capacitance element connected in parallel to a pixel electrode of each pixel; and a wiring connected to the correction capacitance element of each pixel. The frame is divided into N subfields having a period corresponding to each bit of the N-bit grayscale data, and the frame is divided into one frame at a cycle of the shortest subfield of the N subfields. One of binary voltages is written to each of the pixels based on the tone data. ^N By performing gradation display and changing the potential of the wiring after writing one of the binary voltages, the pixel electrode potential of each pixel is corrected by a feed-through voltage. That is the gist.
[0015]
According to this, the potential of the wiring to which the correction capacitance element of each pixel is connected is changed after writing one of the binary voltages, so that the pixel electrode potential of each pixel is corrected by the feedthrough voltage. be able to. Accordingly, the potential difference between the scanning line and the pixel electrode becomes relatively small, so that disclination is suppressed, the contrast and the aperture ratio are improved, and a bright display is obtained. Also, one frame is divided into N subfields having a period corresponding to each bit of the N-bit grayscale data, and one frame has a period of the shortest subfield among the N subfields. Write one of binary voltages to each pixel based on the gradation data 2 ^N The gradation is displayed. In order to perform such a gradation display, one frame has a period of the shortest subfield of 2 frames. ^N One time, one of the binary voltages (signal) is written. For example, by using 3-bit gradation data, 2 ³ In the case of performing gray scale display (8 gray scales), the period of three sub-feeds has a length corresponding to each bit, that is, 1 (2 ⁰ ): 2 (2 ¹ ): 4 (2 ² ). In the cycle of the shortest subfield of the three subfields set in this way, seven times (2 ³ One time) One of the binary voltages is written.
[0016]
Thus, the holding period for holding the voltage of the signal (pixel voltage) written to each pixel in one frame until the next writing is 1 / (2 ^N -1), and the amount of voltage drop of the pixel voltage during the holding period can be reduced. Therefore, it is not necessary to increase the storage capacitance (Cst in the above formula 1) of the capacitor provided in each pixel in order to reduce the leakage current of the switching element and reduce the amount of voltage drop of the pixel voltage. As a result, a high-definition display with a small pixel pitch and a bright display can be obtained while suppressing problems such as a decrease in contrast and a decrease in aperture ratio. In this manner, disclination can be suppressed and the amount of decrease in the pixel voltage during the holding period can be reduced, so that a bright display with low power consumption and high definition can be realized.
[0017]
The electro-optical device according to the aspect of the invention includes a plurality of switching elements arranged in a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines. An electro-optical device configured to write a signal to each pixel, comprising: a correction capacitance element connected in parallel to a pixel electrode of each pixel; and a wiring connected to the correction capacitance element of each pixel. 2 frames with the same duration ^N -1 is divided into one subfield, and one of binary voltages is written to each pixel based on the gradation data for each subfield. ^N By performing gradation display and changing the potential of the wiring after writing one of the binary voltages, the pixel electrode potential of each pixel is corrected by a feed-through voltage. That is the gist.
[0018]
According to this, the potential of the wiring to which the correction capacitance element of each pixel is connected is changed after writing one of the binary voltages, so that the pixel electrode potential of each pixel is corrected by the feedthrough voltage. be able to. Accordingly, the potential difference between the scanning line and the pixel electrode becomes relatively small, so that disclination is suppressed, the contrast and the aperture ratio are improved, and a bright display is obtained. Also, one frame having a period of the same length ^N -1 divided into subfields, and for each subfield, one of binary voltages (signal) is written to each pixel based on the gradation data. ^N The gradation is displayed. In order to perform such a gradation display, two frames are required for each subfield in one frame. ^N One write of one of the binary voltages is performed once. Thus, the holding period for holding the voltage of the signal (pixel voltage) written to each pixel in one frame until the next writing is 1 / (2 ^N -1), and the amount of voltage drop of the pixel voltage during the holding period can be reduced. Therefore, it is not necessary to increase the storage capacitance (Cst in the above formula 1) of the capacitor provided in each pixel in order to reduce the leakage current of the switching element and reduce the amount of voltage drop of the pixel voltage. As a result, a high-definition display with a small pixel pitch and a bright display can be obtained while suppressing the occurrence of problems such as a decrease in contrast and a decrease in aperture ratio. In this manner, disclination can be suppressed and the amount of decrease in the pixel voltage during the holding period can be reduced, so that a bright display with low power consumption and high definition can be realized.
[0019]
In this electro-optical device, when an N-channel transistor is used as each of the switching elements, the pixel electrode potential of each of the pixels is corrected to a plus side by a feed-through voltage.
[0020]
According to this, when an N-channel transistor is used as each switching element, the pixel electrode potential of each pixel can be corrected by the feedthrough voltage.
[0021]
In the electro-optical device, when a P-channel transistor is used as each of the switching elements, the pixel electrode potential of each of the pixels is corrected to a minus side by a feed-through voltage.
[0022]
According to this, when a P-channel transistor is used as each switching element, the pixel electrode potential of each pixel can be corrected by the feedthrough voltage.
[0023]
In this electro-optical device, a value that changes the potential of the wiring is set to a plus field and a positive field in which one of the binary voltages is written to each of the pixels as a positive signal for each of predetermined periods. A negative field in which one of the binary voltages is written as a negative polarity signal is set individually.
[0024]
According to this, the feedthrough voltage in each field is individually corrected by individually setting the value for changing the potential of the wiring to which the correction capacitance element of each pixel is connected in the plus field and the minus field. can do. Thereby, the polarity difference of the voltage applied to each pixel between the plus field and the minus field is reduced, and it is possible to further suppress the occurrence of flicker and burn-in.
[0025]
In the electro-optical device, the wiring connected to the correction capacitance element of each of the pixels may be a gate line or the correction capacitance element connected to a preceding scanning line selected immediately before the plurality of scanning lines. Are a plurality of correction capacitance wirings respectively connected to the plurality of correction capacitance wirings.
[0026]
According to this, when the wiring connected to the correction capacitance element of each pixel is a gate line connected to the preceding scanning line selected one before the plurality of scanning lines, each scanning line has It may be configured to supply a signal having a voltage waveform that corrects the pixel electrode potential of the pixel by the feedthrough voltage. Therefore, it is not necessary to provide any special wiring for correcting the feedthrough voltage, and the change is small. When the wiring is a plurality of correction capacitance lines individually connected to the correction capacitance element of each pixel, it is possible to individually correct the pixel electrode potential of each pixel by the feedthrough voltage.
[0027]
In this electro-optical device, the pixel electrode of each pixel constitutes a liquid crystal capacitor of each pixel together with a liquid crystal as an electro-optical material and a counter electrode provided between a pair of substrates, and a non-memory liquid crystal is used as the liquid crystal. .
[0028]
According to this, the liquid crystal of the memory type is not affected by the leakage current with respect to the retention, but the liquid crystal of the non-memory type is affected by the leakage current, which is particularly effective when a non-memory type liquid crystal is used. It becomes.
[0029]
A driving method of an electro-optical device according to the present invention includes a plurality of switching elements arranged in a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines, and the switching elements of each pixel are driven in a matrix. A driving method of an electro-optical device configured to write a signal to a pixel electrode of each pixel, wherein writing of a signal to the pixel electrode of each pixel is performed at a frame frequency of 120 Hz or more, The potential of the wiring connected to the correction capacitor connected in parallel to the pixel electrode of the pixel is changed after writing a signal to the pixel electrode, thereby correcting the pixel electrode potential of each pixel by a feedthrough voltage. That is the gist.
[0030]
According to this, the disclination can be suppressed, and the amount of decrease in the pixel voltage during the holding period can be reduced, so that even with high definition, low power consumption and bright display can be realized.
[0031]
A driving method of an electro-optical device according to the present invention includes a plurality of switching elements arranged in a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines, and the switching elements of each pixel are driven in a matrix. A method of driving an electro-optical device configured to write a signal to each pixel, wherein one frame is divided into N sub-fields having a period corresponding to each bit of N-bit gradation data. And one of two binary voltages is written into each pixel based on the grayscale data in the cycle of the shortest subfield of the N subfields in one frame. ^N By performing gradation display and changing the potential of the wiring to which the correction capacitance element connected in parallel to the pixel electrode of each pixel is connected after writing one of the binary voltages, The gist of the present invention is to correct the pixel electrode potential of a pixel by a feedthrough voltage.
[0032]
According to this, the disclination can be suppressed, and the amount of decrease in the pixel voltage during the holding period can be reduced, so that even with high definition, low power consumption and bright display can be realized.
[0033]
A driving method of an electro-optical device according to the present invention includes a plurality of switching elements arranged in a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines, and the switching elements of each pixel are driven in a matrix. A method of driving an electro-optical device configured to write a signal to each pixel, wherein one frame has a period of the same length. ^N Divided into sub-fields, and for each of the sub-fields, one of binary voltages is written to each of the pixels based on the gradation data. ^N By performing gradation display and changing the potential of the wiring to which the correction capacitance element connected in parallel to the pixel electrode of each pixel is connected after writing one of the binary voltages, The gist of the present invention is to correct the pixel electrode potential of a pixel by a feedthrough voltage.
[0034]
According to this, the disclination can be suppressed, and the amount of decrease in the pixel voltage during the holding period can be reduced, so that even with high definition, low power consumption and bright display can be realized.
[0035]
In this method of driving an electro-optical device, a value for changing the potential of the wiring is a plus field in which one of the binary voltages is written to each of the pixels as a signal of a positive polarity every predetermined period. A negative field in which one of the binary voltages is written as a negative signal to each pixel is set individually.
[0036]
According to this, the polarity difference of the voltage applied to each pixel between the plus field and the minus field is reduced, and it is possible to further suppress the occurrence of flicker and burn-in.
[0037]
An electronic apparatus according to the present invention includes the electro-optical device according to any one of claims 1 to 8.
According to this, the display quality of the electronic device can be improved. Therefore, an electronic device with good visibility can be realized.
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment in which the present invention is applied to a liquid crystal display device will be described below with reference to the drawings.
[0039]
[First Embodiment]
FIG. 1 shows a liquid crystal display panel of the liquid crystal display device according to the first embodiment of the present invention, from which an external circuit is removed, FIG. 2 shows a cross section of the panel, and FIG. FIG. 4 schematically shows an electric configuration of a driving circuit of the liquid crystal display device, and FIG. 4 shows a part of an electric equivalent circuit of the liquid crystal display panel.
[0040]
The liquid crystal display device of the present embodiment is an active matrix type liquid crystal display device having a liquid crystal display panel in which liquid crystal as an electro-optical material is sealed between two substrates and a switching element is provided for each pixel arranged in a matrix. . In addition, this liquid crystal display device alternately writes a positive data signal and a negative data signal to the pixel electrode of each pixel at predetermined intervals, for example, for each frame, and drives the liquid crystal by AC driving (inversion). Drive).
[0041]
The liquid crystal display panel 21 includes an element substrate 22 made of a quartz substrate and a counter substrate 23 as shown in FIGS. 1 and 2, and a TN (Twisted Nematic) type liquid crystal 24 is sealed between the two substrates. I have. In addition, as shown in FIGS. 3 and 4, the liquid crystal display panel 21 has a matrix arrangement corresponding to intersections (intersections) between the m rows of scanning lines Y1 to Ym and the n columns of signal lines X1 to Xn. And a TFT 26 serving as a switching element provided in each pixel 25.
[0042]
As shown in FIGS. 1 and 2, the element substrate 22 and the opposing substrate 23 are adhered to each other so that their electrode forming surfaces face each other at a fixed interval by a sealing material 27 including a spacer (not shown). A liquid crystal 24 is sealed between them. The sealant 27 is formed along the periphery of the counter substrate 23 and has an opening 27a for enclosing the liquid crystal 24. The opening 27a is sealed with the sealing material 28 after the liquid crystal 24 is sealed.
[0043]
Also, as shown in FIGS. 2 to 4, m rows of scanning lines Y1 to Ym arranged in the Y direction and n columns of signal lines X1 to Xn arranged in the X direction are formed on the element substrate 22. Is formed. Further, m × n pixels 25 and a TFT (thin film transistor) 26 provided for each pixel 25 are formed on the element substrate 22. The gate of each TFT 26 is connected to one of the scanning lines Y1 to Ym, its source is connected to one of the signal lines X1 to Xn, and its drain is connected to the pixel electrode 29 of one corresponding pixel 25.
[0044]
As shown in FIGS. 2 to 4, the pixel electrode 29 of each pixel 25 is opposed to one common electrode 30 provided as a counter electrode provided on the counter substrate 23 side via the liquid crystal 24. Further, each pixel 25 is connected in parallel with a liquid crystal capacitor 31 composed of a liquid crystal 24 between a rectangular pixel electrode 29 and a common electrode 30 to reduce leakage of the liquid crystal capacitor. And a correction capacitance element 32 which is a capacitance element. Note that an alignment film provided on the surface of the pixel electrode 29 and the common electrode 30 is not shown.
[0045]
Further, as shown in FIGS. 1 and 3, the liquid crystal display device includes two scanning line driving circuits 33, 33 for driving the scanning lines Y1 to Ym, and driving circuits for driving the signal lines X1 to Xn. A signal line driving circuit 34 and a control circuit 35 for controlling the scanning line driving circuit 33 and the signal line driving circuit 34 are provided. The control circuit 35 receives a data signal, a synchronization signal, and a clock signal from an external circuit. Further, a vertical synchronization signal, a clock signal, and the like are supplied from the control circuit 35 to the two left and right scanning line driving circuits 33, 33 via the signal line 36. Then, a data signal, a horizontal synchronizing signal, and the like are supplied from the control circuit 35 to the signal line driving circuit 34 via the signal line 37. Further, on the element substrate 22, a silver dot 38 which is a connection terminal with the counter substrate 23 side, an input terminal 39 to which various signals are input from an external circuit, and the like are formed.
[0046]
Next, a description will be given of gradation control by sub-field driving (time-division driving) and correction control of a feedthrough voltage, which are characteristic configurations of the liquid crystal display device of the present embodiment.
<Gradation control by subfield drive>
In the liquid crystal display device of this example, a positive data signal and a negative data signal are alternately written to the pixel electrode 29 of each pixel 25 for each frame, and the liquid crystal 24 is AC-driven (inverted). For this purpose, for example, the potential of the common electrode 30 is inverted between a low potential and a high potential for each frame. In the following description, one frame in which a positive data signal is written to the pixel electrode 29 of each pixel 25 is called a plus field, and one frame in which a negative data signal is written to the pixel electrode 29 of each pixel 25 is called a minus field. (See FIG. 5). In addition, the “one frame” referred to here means that one scanning line Y1 to Ym is sequentially selected and a data signal is written to the capacitances of all the pixels 25 (the storage capacitances of the liquid crystal capacitance 31 and the correction capacitance element 32). A period that constitutes a display.
[0047]
The control circuit 35 controls the 2 ^N The scanning line driving circuit 33 and the signal line driving circuit 34 are controlled so as to perform gradation display. In the “sub-field driving”, one frame (each of the plus field and the minus field) is divided into N sub-fields having a period corresponding to each bit of the N-bit gradation data. The period of the N sub-feeds has a length corresponding to each bit, that is, 1 (2 ⁰ ): 2 (2 ¹ ): 4 (2 ² ) ・ ・ ・ 2 ^N It is set to a ratio of -1. In the cycle of the shortest subfield among the N subfields set in this way, one of the binary voltages is written to each pixel based on the gradation data shown in FIG. ^N The gradation is displayed.
[0048]
Specifically, the control circuit 35 of the present example ³ Gradation (2 ^N N = 3, 8 gradations), that is, gradation display of gradation levels 0 to 7, as shown in FIG. 5, one frame includes three subfields SF1, SF2 and SF3. Respectively. Each period (time length) of the three subfields SF1, SF2, and SF3 is set to a length corresponding to each bit of the 3-bit grayscale data (in accordance with the binary system), that is, 1 (2 ⁰ ): 2 (2 ¹ ): 4 (2 ² ). Accordingly, each period of the subfields SF2 and SF3 is twice or four times as long as the subfield SF1. In this case, the subfield having the shortest period among the three subfields SF1, SF2, and SF3 is SF1, and a binary voltage is applied to each pixel 25 as a data signal in the cycle T of the subfield SF1 (see FIG. 6). Write either one of The “binary voltage” referred to here is an L-level voltage 0 (V) and an H-level voltage V1 (V). The voltage V1 is + V1 (V) in the plus field and -V1 (V) in the minus field (see FIGS. 5 and 7).
[0049]
As described above, in the gradation control by the subfield driving of the present example, the writing of the data signal to the pixel electrode 29 of each pixel 25 is performed at the frame frequency of 60 Hz (the frame cycle is 1/60 sec), One of the binary voltages is written to the pixel electrode 29 at each period T in one frame. In other words, the data signal is written to the pixel electrode 29 of each pixel 25 seven times per cycle T (2 times in one frame of 1/60 second (sec)). ³ 1). For this purpose, the control circuit 35 outputs a vertical scanning start signal DY (not shown) to the scanning line driving circuit 33 seven times at intervals of a period T in one frame based on the synchronization signal and the clock signal. .
[0050]
The left and right scanning line driving circuits 33 generate and output the scanning signals G1 to Gm, respectively, every time a vertical scanning start signal DY (hereinafter simply referred to as a start signal DY) is input from the control circuit 35. Thus, the scanning lines Y1 to Ym are sequentially selected. That is, when the first start signal DY is input at the beginning of one frame, the scanning line driving circuit 33 sequentially outputs the first scanning signals G11 to Gm1 as shown in FIG. Select in order. This selection period is the first selection period in one frame. When the second to seventh start signals DY are input each time the period T elapses from the input of the first start signal DY, the scan line driving circuit 33 outputs the second scan signals G12 to Gm2. ... The seventh scanning signals G17 to Gm7 are sequentially output, and the scanning lines Y1 to Ym are sequentially selected. These selection periods are the second to seventh selection periods in one frame. The operation of sequentially selecting the scanning lines Y1 to Ym is repeated seven times in one frame.
[0051]
Further, in addition to the synchronization signal and the clock signal, 3-bit grayscale data as a binary data signal which is an image signal is input to the control circuit 35 in order to perform field driving. The gradation data are eight types of binary data signals from (000) to (111) as shown in Table 1 below and FIGS. 5 (a) to 5 (h).
[0052]
[Table 1]

In the case of the normally white mode, the gradation data (000) is data for displaying one pixel 25 with a gradation of 0 (white display), and the gradation data (111) is stored in one pixel 25 with the gradation. 7 (black display). Further, the gradation data (001) to (110) are data for displaying an intermediate gradation level of 1 to 6 on one pixel 25, respectively.
[0053]
The signal line driving circuit 34 outputs L to each pixel connected to the selected scanning line as a data signal as shown in Table 1 below and FIG. 5 in each selection period in which the scanning lines Y1 to Ym are sequentially selected. Either (voltage 0) or H (voltage V1) is sequentially output. As a result, one of L and H is turned on (conducting state) by the liquid crystal capacitance 31 and the correction capacitance element 32 of each pixel 25 connected to the selected scanning line in each of the seven selection periods. The data is written via the changed TFT 26. When the TFT 26 is turned off (non-conducting state) after the L (voltage 0) or H (voltage V1) data signal is written, the voltage 0 or the voltage V1 is applied to the liquid crystal capacitance 31 and the correction capacitance element 32 of each pixel 25. Is held.
Table 2 below shows gradation data corresponding to the above-described eight types of gradations, and subfields SF1 (first selection period), SF2 (second and third selection periods), and SF3 (one frame) in one frame. The relationship with the data signal applied to one pixel 25 in the fourth to seventh selection periods is shown.
[0054]
[Table 2]

For example, when the gradation data (000) of FIG. 5A is used to display each pixel 25 with a gradation of 0, as shown in Table 2, the subfields SF1 (first selection period) and SF2 (second selection period) In each of the seven selection periods of SF3 (the fourth to seventh selection periods), only the L data signal is written to each pixel 25. Further, in the case of displaying each pixel 25 at the gradation level 1 with the gradation data (001) in FIG. 5B, as shown in Table 2, the H data signal is written only in the first selection period, An L data signal is written in each of the second to seventh selection periods. Similarly, when gradation levels 2 to 7 are displayed on each pixel 25 using the gradation data (010) to (111) in FIGS. 5C to 5H, as shown in Table 2, seven times An L or H data signal is written in each selection period.
[0055]
<Description of operation of gradation control by subfield driving>
Here, as an example, a case will be described in which all pixels 25 in one frame are displayed with a gradation of 1 based on the gradation data (001) in FIG. 5B.
[0056]
When the first start signal DY is input at the beginning of one frame, the scanning line driving circuit 33 sequentially outputs the scanning signals G11 to Gm1 shown in FIGS. 6A, 6B, and 6C to perform scanning. Lines Y1 to Ym are sequentially selected (first selection period). As a result, the TFT 26 of each pixel 25 connected to one of the scanning lines Y1 to Ym is turned on.
[0057]
In the first selection period (during the subfield SF1), the signal line driving circuit 34 outputs data of H (voltage V1) to each pixel 25 connected to one selected scanning line as shown in Table 2. Outputs signals in order. Thus, the voltage V1 is written as a data signal to the liquid crystal capacitance 31 and the correction capacitance element 32 of each pixel 25 connected to the scanning line via the TFT 26.
[0058]
When the first selection period is completed and each TFT 26 is turned off, the data signal (voltage V1) written to each pixel 25 is held for a holding period until the next selection period (second selection period) (described above). It is held during the period T-selection period h).
[0059]
When the period T elapses from the input of the first start signal DY and the second start signal DY is input, the scanning line driving circuit 33 sequentially outputs the scanning signals G12 to Gm2 and outputs the scanning lines Y1 to Ym. Select in order. In the second selection period, that is, in the first cycle T in the subfield SF2 shown in FIG. 6, the signal line driving circuit 34 applies L (L) to each pixel 25 connected to one of the selected scanning lines Y1 to Ym. The data signals of voltage 0) are sequentially output. Thus, a voltage 0 is written to the pixel electrode 29 of each pixel 25 as a data signal via the TFT 26. When the TFT 26 is turned off after the end of the second selection period, the data signal (voltage 0) written to the pixel electrode 29 of each pixel 25 changes until the next selection period (third selection period). Retained during the retention period.
[0060]
When the third start signal DY is input after the period T has elapsed from the input of the second start signal DY, the scanning line driving circuit 33 sequentially outputs the scanning signals G13 to Gm3 and outputs the scanning lines Y1 to Ym. Select in order. In the third selection period, that is, in the first cycle T in the subfield SF2 shown in FIG. 6, the signal line driving circuit 34 applies L (voltage 0) to each pixel 25 connected to one of the selected scanning lines. Are sequentially output. Thus, the voltage 0 is written to each pixel. When the TFT 26 is turned off after the third selection period ends, the electric charge (voltage 0) written to each pixel 25 is held for the holding period until the next selection period (fourth selection period). Is done.
[0061]
Thereafter, similarly to the above, every time the fourth to seventh start signals DY are input at intervals of the period T, the scanning line driving circuit 33 sequentially transmits the scanning signals G14 to Gm4 to the scanning signals G17 to Gm7. The output period is the fourth to seventh selection periods. In the fourth to seventh selection periods, that is, in each of the first to fourth cycles T in the subfield SF3, an L (voltage 0) data signal is applied to each pixel connected to one of the selected scanning lines. Are written respectively.
[0062]
In this way, in the seventh selection period, the L data signal is written to each pixel connected to the scanning line Ym selected last, so that all the pixels constituting one screen are displayed with the gradation of 1. Thus, the operation of composing one screen (one frame cycle) ends.
<Feedthrough voltage correction control>
Further, in the liquid crystal display device of this example, the feed-through voltage for correcting the feed-through voltage at which the pixel electrode potential of the pixel electrode 29 (hereinafter, referred to as a pixel potential) decreases at the moment when the TFT 26 of each pixel 25 is turned off. Correction control "is performed. In order to perform this correction control, the correction capacitance element 32 of each pixel 25 connected to any one of the scanning lines Y1 to Ym is connected via a gate line (wiring) 40 as shown in FIG. The scanning line is connected to a preceding scanning line (one line before) selected one before the m scanning lines Y1 to Ym. For example, the correction capacitance element 32 of each pixel 25 at each intersection of the scanning line Yk + 1 and the signal lines X1 to Xn is connected via the gate line 40 to the scanning line Yk which is the preceding scanning line selected immediately before. It is connected to the.
[0063]
Then, the control circuit 35 writes a data signal to each pixel 25 by the above-described “grayscale control by sub-field driving”, and then controls the scanning signals G1 to Gm to be applied to one of the selected scanning lines Y1 to Ym. By changing the voltage, the pixel potential of each pixel is corrected by the feedthrough voltage. For this purpose, as shown in FIGS. 7A and 7B, the control circuit 35 converts the voltages of the scanning signals Gk and Gk + 1 applied to one selected scanning line, for example, the scanning line Yk or Yk + 1, to the data signal. After writing, the voltage is reduced from the voltage V0 at the time of selection to a voltage value lower than the reference value (eg, 0 V) by the voltage V2. Then, the control circuit 35 controls the scanning line driving circuit 33 so as to maintain the low voltage value for a certain period of time and thereafter return to the reference value. The certain time is a total time of the selection period h and the period τ.
[0064]
The control circuit 35 configured as described above changes the potential of the gate line 40 to which the correction capacitance element 32 of each pixel 25 is connected after writing the L (voltage 0) or H (voltage V1) data signal. The pixel voltage correcting means corresponds to the control circuit 35 and corrects the pixel potential of each pixel by the feedthrough voltage ΔV.
[0065]
In addition, as for the correction capacitance element 32 of each pixel 25 in which the gate of the TFT 26 is connected to the scanning line Y1 of the first row, there is no preceding scanning line with respect to the scanning line Y1 of the first row. A line Y0 (not shown) is provided. The correction capacitance element 32 of each pixel 25 at each intersection of the scanning line Y1 and the signal lines X1 to Xn is connected to the dummy scanning line Y0 via the gate line 40. Then, a scanning signal having the same voltage waveform as that of the other scanning lines Y1 to Ym is applied to the scanning line Y0. Alternatively, the voltage is changed to a voltage waveform for changing the potential of the gate line 40 after each writing of the data signal, that is, a voltage value lower than the reference value (for example, 0 V) by the voltage V2, and the low voltage value is maintained for a certain period of time. Only a voltage waveform that returns to the reference value may be applied.
[0066]
By performing such a feed-through voltage correction control, the pixel potential of each pixel 25 connected to one selected scanning line, for example, the scanning line Yk + 1, is increased in the plus field and the minus field, respectively, as shown in FIG. Changes as shown in FIG.
[0067]
In the plus field, for example, the pixel potential of the scanning line Yk + 1 becomes + V1 when the data signal of the voltage V1 (H) is written in the seven selection periods. At the moment when the writing is completed and the TFT 26 is turned off (time t1), the pixel potential decreases from the voltage V1 (+ V1) by the feedthrough voltage ΔVd. Thereafter, when the period τ elapses from the time point t1 (time point t2), the scanning signal applied to the scanning line Yk connected to the correction capacitance element 32 of each pixel connected to the scanning line Yk + 1 via the gate line 40. The potential of Gk rises from the low voltage value by the voltage V2 and returns to the reference value. As a result, the pixel potential of each pixel 25 connected to the scanning line Yk + 1 rises by ΔVu1 from the potential lowered by the feedthrough voltage ΔVd from the voltage V1 (time t2). When the selection period h elapses from this point (time t3), the voltage of the scanning signal Gk + 1 applied to the scanning line Yk + 1 increases by the voltage V2. Accordingly, the pixel potential of each pixel 25 connected to the scanning line Yk + 1 further increases by ΔVu2.
[0068]
On the other hand, in the minus field, for example, the pixel potential of the scanning line Yk + 1 becomes −V1 when the H data signal is written during the seven selection periods, and the potential is changed from −V1 at the moment when the writing is completed and the TFT 26 is turned off. It decreases by the through voltage ΔVd. Thereafter, the lowered pixel potential rises by ΔVu1 when the potential of the scanning signal Gk rises from the low voltage value by the voltage V2 and returns to the reference value, and further, the voltage of the scanning signal Gk + 1 rises by the voltage V2. I do. As a result, the pixel potential further increases by ΔVu2.
[0069]
As described above, the pixel potential of each pixel is changed. The amounts of change ΔVd, ΔVu1 and ΔVu2 of each voltage are expressed by the following equations (2), (3) and (4), respectively.
[0070]
ΔVd = {Ctft / (Ctft + Ch + Clc)} × (V1 + V2) ·· 2
ΔVu1 = {Ch / (Ctft + Ch + Clc)} × V2...
ΔVu2 = {Ctft / (Ctft + Ch + Clc)} × V2...
Here, Ch is the capacitance of the correction capacitance element 32. The capacitance of the correction capacitance element 32 is not only a storage capacitance for reducing the leakage of the liquid crystal capacitance, but also a correction capacitance for correcting the feedthrough voltage ΔVd. Therefore, in the following description, the capacitance Ch of the correction capacitance element 32 is called a correction capacitance. In each of the above equations 2 to 4, for simplification, it is assumed that Ctft does not depend on the gate voltage and the drain voltage.
[0071]
To set the feedthrough voltage ΔVd to 0,
ΔVd−ΔVu1−ΔVu2 = 0, that is,
It is necessary to set the voltage V2 and the correction capacitance Ch so as to satisfy Ctft × V1−Ch × V2 = 0 or V1 / V2 = Ch / Ctft.
[0072]
For example, assuming that V1 = 11 to 15V and Ctft = 1fF, the feedthrough voltage ΔVd is set by setting the voltage V2 to V2 = 1.1 to 1.5V and setting the correction capacitance Ch to about Ch = 10fF. Can be set to 0.
[0073]
As shown in FIG. 6, seven vertical scans are performed in one frame, but a vertical blanking period from the end of each vertical scan to the start of the next vertical scan is omitted. Further, in each selection period for sequentially selecting the scanning lines Y1 to Ym, from the end of the horizontal scanning period for sequentially writing a data signal to each pixel connected to the selected scanning line to the start of the next horizontal scanning, A horizontal retrace period is provided as needed.
[0074]
The period τ shown in FIG. 7 is provided to prevent the correction of the feed-through voltage from becoming insufficient due to the dullness of the gate line 40 or insufficient current supply capability. It does not need to be a value. The period τ may have the same length as the selection period h. In this case, the voltage of the scanning signal may be increased by the voltage V2 at the timing when a period τ (τ = h) having the same length as the selection period h has elapsed from the end of each writing of the data signal, and the circuit configuration is simplified. . If there is no problem even in the period τ = 0, setting τ = 0 further simplifies the circuit configuration.
[0075]
According to the first embodiment configured as described above, the following operation and effect can be obtained.
(A) By sub-field driving, 2 ³ It is possible to perform gradation display of gradation (8 gradations), that is, gradation display of gradation levels 0 to 7.
[0076]
(B) In the subfield driving, one frame is divided into three subfields SF1, SF2, and SF3 having a period corresponding to each bit of the 3-bit grayscale data. The three subfields SF1, SF2 and SF3 are set in a period (time length) of a ratio of 1: 2: 4. In one frame, L (voltage 0) or H (voltage V1) data is applied to each pixel 25 based on the gradation data shown in FIG. 5 in the cycle T of the subfield SF1 having the shortest period among the three subfields. The signals are written as shown in Table 2 above and a display of 23 gradations is performed.
[0077]
In such gradation control, assuming that the frame frequency is 60 Hz, the writing of a data signal to each pixel 25 is performed seven times in each frame T in one frame whose frame cycle is 1/60 second (sec) (23- Once). As a result, the holding period for holding the voltage (pixel voltage) of the data signal written to each pixel 25 in one frame until the next writing is shortened by 1/7 compared with the normal driving method, and the pixel during the holding period is reduced. The amount of voltage drop can be reduced. For example, as described above, when the pixel pitch is 200 ppi and 1000 ppi, the liquid crystal capacitance Clc is 1/4 and 1/100, and the amount of voltage drop during the holding period is 4 times and 100 times, ^N By appropriately setting N to a large value, the amount of voltage drop can be suppressed. Therefore, in order to reduce the leakage current of the switching element and reduce the amount of voltage drop of the pixel voltage, the storage capacitance (Cst in the above formula 1) of the correction capacitance element 32 (storage capacitance) provided in each pixel 25 is increased. No need. As a result, a high-definition display with a small pixel pitch and a bright display can be obtained while suppressing the occurrence of problems such as a decrease in contrast and a decrease in aperture ratio.
[0078]
(C) By performing the above-described feed-through voltage correction control, the feed-through voltage at which the pixel potential decreases at the moment when the TFT 26 of each pixel 25 is turned off can be corrected. Accordingly, the potential difference between each of the scanning lines Y1 to Ym and each of the pixel electrodes 29 becomes relatively small, so that disclination is suppressed, the contrast and the aperture ratio are improved, and a bright display is obtained. In this way, disclination can be suppressed, and the amount of decrease in the pixel voltage during the holding period can be reduced as described in (b) above, thereby realizing bright display with low power consumption even at high definition. can do.
[0079]
(D) In the correction control of the feed-through voltage, as shown in FIGS. 7A and 7B, the control circuit 35 controls the scanning signal Gk to be applied to one selected scanning line, for example, the scanning line Yk or Yk + 1. After writing the L or H data signal, the voltage of Gk + 1 is lowered from the voltage V0 at the time of selection by a voltage V2 from a reference value (for example, 0 V). Then, the control circuit 35 controls the scanning line driving circuit 33 so as to maintain the low voltage value for a certain period of time and thereafter return to the reference value. Therefore, a configuration may be adopted in which a signal having a voltage waveform that corrects the pixel potential of each pixel 25 by the feedthrough voltage is supplied to each of the scanning lines Y1 to Ym, and a special wiring is provided to correct the feedthrough voltage. There is no need to provide it, and only a slight change in the electrical configuration is required.
[0080]
(E) An N-channel TFT 26 is used as a switching element provided in each pixel 25. In this case, the control circuit 35 as the pixel voltage correcting means corrects the pixel potential of each pixel 25 to the plus side by the feedthrough voltage ΔVd as shown in FIG. 7C. Thus, when an N-channel TFT 26 is used as each switching element, the pixel potential of each pixel 25 can be corrected by the feedthrough voltage.
[0081]
[Second embodiment]
Next, a liquid crystal display device according to a second embodiment of the present invention will be described with reference to FIGS. In the description of this embodiment, the same members and signals as those in the first embodiment are denoted by the same reference numerals, and a duplicate description will be omitted.
[0082]
The second embodiment is the same as the first embodiment in that the gradation control by the sub-field driving is performed. However, in order to perform the feed-through voltage correction control, each of the scanning lines Y1 to Ym is individually controlled. Corresponding correction capacitance wirings 4 ₁₁ ~ 4 _1m (Refer to FIG. 9 and FIG. 10) is different from the first embodiment in that they are individually connected.
[0083]
In FIG. ₁₁ ~ 4 _1m Among them, the correction capacitance wiring 4 _1k And 4 _{1k + 1} Only shows. These correction capacitance lines 4 ₁₁ ~ 4 _1m 9 (a) to 9 (c) and FIG. 10 () show a correction capacitance wiring corresponding to one selected scanning line among driving circuits (not shown) for the correction capacitance wiring controlled by the control circuit 35. The voltage signal S shown in FIGS. 3A and 3B is output. The control circuit 35 and the drive circuit (not shown) for the correction capacitance wiring configured as described above correspond to the pixel voltage correction unit.
[0084]
The voltage signal S decreases to a voltage value lower than the reference value (for example, 0 V) by the voltage V2 before or almost simultaneously with the selection of each of the scanning lines Y1 to Ym in order, and the low voltage value is maintained for a predetermined time. (Period τ1 + period τ2) is maintained, and thereafter changes to return to the reference value. The period τ2 is a period from the end of each selection period to the return to the reference value.
[0085]
According to the feed-through voltage correction control of this embodiment, the pixel potential of each pixel 25 connected to one selected scanning line, for example, the scanning line Yk + 1, is shown in FIG. 10C in the plus field and the minus field, respectively. To change.
[0086]
In the plus field, for example, the pixel potential of the scanning line Yk + 1 drops from + V1 by the feedthrough voltage ΔVd at the moment when the data signal writing in the seven selection periods is completed and the TFT 26 is turned off. Thereafter, when the period τ2 elapses, the potential supplied to the correction capacitance element 32 ′ of each pixel connected to the scanning line Yk + 1 via the correction capacitance wiring 41k + 1 rises from the low voltage value by the voltage V2 and becomes the reference voltage. Return to value. As a result, the pixel potential of each pixel 25 connected to the scanning line Yk + 1 rises by ΔVu from the potential that has dropped from + V1 by the feedthrough voltage ΔVd.
[0087]
Similarly, in the minus field, after the writing of the data signal is completed, when the period τ2 elapses, the pixel potential of each pixel 25 connected to the scanning line Yk + 1 increases by ΔVu from the potential lowered by −V1 by the feedthrough voltage ΔVd. I do.
[0088]
As described above, the pixel potential of each pixel is changed. The change amounts ΔVd and ΔVu of the respective voltages are expressed by the following equations 5 and 6, respectively.
ΔVd = {Ctft / (Ctft + Ch + Clc)} × V1 · 5
ΔVu = {Ch / (Ctft + Ch + Clc)} × V2...
Here, Ch is a correction capacitance of the correction capacitance element 32 '. In each of the above equations 5 and 6, for simplicity, it is assumed that Ctft does not depend on the gate voltage and the drain voltage.
[0089]
To set the feedthrough voltage ΔVd to 0,
ΔVd−ΔVu = 0, that is,
Ctft × V1-Ch × V2 = 0 or
It is necessary to set the voltage V2 and the correction capacitance Ch so as to satisfy V1 / V2 = Ch / Ctft.
[0090]
For example, assuming that V1 = 11 to 15V and Ctft = 1fF, the feedthrough voltage ΔVd is set by setting the voltage V2 to V2 = 1.1 to 1.5V and setting the correction capacitance Ch to about Ch = 10fF. Can be set to 0. Therefore, the correction capacitance Ch can be reduced.
[0091]
According to the second embodiment configured as described above, the following operation and effect can be obtained.
(F) To perform the feed-through voltage correction control, a plurality of correction capacitance lines 4 corresponding to the scanning lines Y1 to Ym, respectively. ₁₁ ~ 4 _1m (See FIGS. 9 and 10) are individually connected. Thereby, the pixel potential of each pixel 25 can be individually corrected by the feedthrough voltage.
[0092]
[Third embodiment]
Next, a liquid crystal display device according to a third embodiment of the present invention will be described with reference to FIG.
[0093]
The third embodiment is the same as the first embodiment in that the correction control of the feedthrough voltage is performed using the gate line (wiring) 40, but the point that the gradation control by the subfield driving is not performed. This is different from the first embodiment.
[0094]
In the third embodiment, the control circuit 35 performs analog gradation control for writing a data signal of a voltage corresponding to the gradation to the pixel electrode 29 of each pixel 25. Further, the control circuit 35 controls the scanning line driving circuit 33 so that the writing of the data signal to the pixel electrode 29 of each pixel 25 is performed at a frame frequency of 120 Hz or more, for example, a frame frequency of 480 Hz which is eight times the normal 60 Hz. And the signal line drive circuit 34 is controlled.
[0095]
According to the third embodiment configured as described above, the following operation and effect can be obtained.
(G) Since the writing of the data signal to the pixel electrode 29 of each pixel 25 is performed at the frame frequency of 480 Hz, the frame period is shortened. That is, the frame period can be set to 1/8 (1/480 sec) of the normal frame period (1/60 sec). Since the frame period is shortened in this way, the holding period for holding the data signal (pixel voltage) written to the pixel electrode 29 of each pixel 25 until the next writing is shortened, and the amount of decrease in the pixel voltage during the holding period is reduced. Can be smaller. Therefore, it is not necessary to increase the storage capacitance of the correction capacitance element 32 provided in each pixel 25 in order to reduce the amount of voltage drop, and problems such as flicker, burn-in, reduced contrast, and reduced aperture ratio occur. A high-definition display with a small pixel pitch can be obtained while suppressing the pixel pitch. Therefore, a bright display with low power consumption and high definition can be realized.
[0096]
[Fourth embodiment]
Next, a liquid crystal display device according to a fourth embodiment of the present invention will be described with reference to FIG.
[0097]
In the fourth embodiment, the correction control of the feedthrough voltage is performed by a plurality of correction capacitance lines 4 corresponding to the respective scanning lines Y1 to Ym. ₁₁ ~ 4 _1m (Refer to FIG. 9 and FIG. 10) is the same as the second embodiment, but differs from the second embodiment in that the gradation control by the subfield drive is not performed.
[0098]
In the fourth embodiment, the control circuit 35 performs analog gradation control for writing a data signal of a voltage corresponding to the gradation to each pixel 25. Further, the control circuit 35 controls the scanning line driving circuit 33 and the signal line driving so that the writing of the data signal to each pixel 25 is performed at a frame frequency of 120 Hz or more, for example, a frame frequency of 480 Hz which is eight times the normal 60 Hz. The circuit 34 is controlled. Therefore, the same operation and effect (g) as in the third embodiment are obtained.
[0099]
[Electronics]
Next, electronic devices using the liquid crystal display panel 21 of the liquid crystal display device described in each of the above embodiments will be described. The liquid crystal display panel 21 can be applied to a mobile personal computer as shown in FIG. A personal computer 70 shown in FIG. 13 includes a main body 72 having a keyboard 71 and a display unit 73 using the liquid crystal display panel 21. The liquid crystal display panel 21 used in the display unit 73 can realize bright display with low power consumption even with high definition.
[0100]
[Modification]
The present invention can be embodied with the following modifications.
In the first embodiment, the present invention is also applicable to a configuration in which gradation control by sub-field driving is performed as follows, instead of gradation control by sub-field driving described above. The control circuit 35 converts one frame into two frames having a period (cycle T) of the same length. ^N -1 is divided into sub-fields, and one of binary voltages is written to each pixel based on the gradation data for each sub-field. ^N The scanning line driving circuit 33 and the signal line driving circuit 34 are controlled so as to perform gradation display. Table 3 below shows 2 as an example. ³ Eight kinds of gradation data when displaying gradations, 2 ³ The relationship with the data signal applied to one pixel 25 in each of the first to seventh selection periods performed for each of −1 (= 7) subfields SF1 to SF7 is shown.
[0101]
[Table 3]

For example, in the case of displaying a gradation of 0 on each pixel 25 with gradation data (000), as shown in Table 3, each of subfields SF1 (first selection period) to SF7 (seventh selection period) Only the L data signal is written to each pixel 25 in the selection period. Further, when the display of the gradation level 1 is performed on each pixel 25 by the gradation data (001), as shown in Table 3, the H data signal is written only in the subfield SF1, and each of the subfields SF2 to SF7 is selected. In the period, an L data signal is written. Similarly, when the gradation data (010) to (111) are used to display each pixel 25 with gradation levels 2 to 7, as shown in Table 3, an L or H data signal is written. I have. By the gradation control by such sub-field driving, the above-described operation and effect (b) can be obtained as in the first embodiment.
[0102]
-In the first embodiment, 2 ³ Gradation (2 ^N N = 3, 8 gradations), that is, gradation display of gradation 0 to gradation 7 is performed. ^N Display of gradation, that is, gradation 0 to gradation 2 ^N The present invention is also applied to a configuration for performing -1 gradation display.
[0103]
In the first embodiment, the frame frequency is set to 60 Hz. However, the present invention is also applied to a configuration in which the gradation control is performed by the subfield drive in a liquid crystal display device in which the frame frequency is twice (120 Hz) or more. It is possible. In this case, the holding period for holding the voltage (pixel voltage) of the data signal written to each pixel 25 until the next writing is shorter than in the first embodiment, so that a higher definition and brighter display can be realized. Can be.
[0104]
In the third and fourth embodiments, the frame frequency is set to 480 Hz. However, the frame frequency is not limited to this, and may be set to 120 Hz.
In the first embodiment, the potential of the common electrode 30 is inverted every frame. However, the present invention can be applied to a case where the potential is inverted every horizontal scanning period. is there.
[0105]
In the first embodiment, in order to invert the liquid crystal, the potential of the common electrode 30 is inverted every frame between a low potential and a high potential. However, the liquid crystal is inverted by another method. The present invention is applicable to driving.
[0106]
In the first embodiment, the left and right two scanning line driving circuits (Y drivers) 33, 33 for driving the scanning lines Y1 to Ym are provided. The present invention is also applicable.
[0107]
In the above embodiments, the scanning line driving circuit 33, the signal line driving circuit 34, and the control circuit 35 are described as being incorporated on the element substrate 22 in FIG. 1, for example. Absent. For example, the IC may be mounted on the circuits 33 to 35 in FIG. 1 by COG, or the IC may be connected by TAB or the like without incorporating the IC. Further, the control circuit 35 may be provided on an external circuit board.
[0108]
In the above embodiments, a TN (Twisted Nematic) type liquid crystal 24 is used. However, as the liquid crystal 24, a bistable type having a memory property such as an STN (Super Twisted Nematic) type, a BTN (Bi-stable Twisted Nematic) type, or a ferroelectric type having a twisted orientation of 180 ° or more, a polymer dispersion type, and a guest Well-known things including a host type can be widely used.
[0109]
In the above embodiments, it is preferable to use a non-memory type (monostable type) as the liquid crystal 24. The memory-type liquid crystal is not affected by the leakage current, but the non-memory-type liquid crystal is affected by the leakage current. This is particularly effective when a non-memory type liquid crystal 24 is used.
[0110]
The TFT 26 used in each of the above embodiments is an a-Si (amorphous silicon: amorphous silicon) type thin film transistor, a p-Si (polysilicon) type thin film transistor, or single crystal silicon or strained silicon using SiGe. Alternatively, another semiconductor material may be used.
[0111]
In each of the above embodiments, a TFT which is a three-terminal switching element is used as a switching element of each pixel. However, instead of this, an active matrix liquid crystal using a two-terminal switching element such as a TFD (Thin Film Diode) is used. The present invention can be applied to a display panel. When a two-terminal switching element is used, a counter electrode is provided on the counter substrate side via a liquid crystal and a pixel electrode of each pixel on the element substrate, and the counter electrode is divided for each scanning line. Then, a two-terminal switching element such as a TFD is arranged on the element substrate side at a position where a signal line on the element substrate and a counter electrode (scanning line) on the counter substrate spatially intersect.
[0112]
In each of the above embodiments, the electro-optical device is described as a liquid crystal display device, but the present invention is not limited to this, and an electro-optical device using an electro-optical material other than liquid crystal and an electronic device including the electro-optical device It is also applicable to devices. For example, when the present invention is applied to an electro-optical device using a light emitting element such as an organic EL element, a “data signal” written to each pixel is applied to a gate of a driving transistor that drives the light emitting element of each pixel. Refers to voltage.
[0113]
The liquid crystal display panel 21 of the liquid crystal display device is not limited to a personal computer as shown in FIG. 13, but can be applied to various electronic devices such as a mobile phone and a digital camera.
[0114]
In the above embodiments, the scanning line driving circuit 33 performs the vertical scanning for sequentially selecting the scanning lines Y1 to Ym in order from the top when a Hi (H level) scanning direction switching signal is input at the start of the vertical scanning. At the same time, when a Low (L level) scanning direction switching signal is input, the scanning is performed sequentially from the bottom. Such a configuration is effective when the present invention is applied to an L / V (light valve) for a projector to project on a screen.
[Brief description of the drawings]
FIG. 1 is a plan view showing a liquid crystal display panel of a liquid crystal display device according to a first embodiment.
FIG. 2 is a cross-sectional view showing a part of a cross section of the liquid crystal display panel of FIG. 1;
FIG. 3 is a schematic configuration diagram illustrating an electrical configuration of a driving circuit of the liquid crystal display device.
FIG. 4 is a circuit diagram showing a part of an electric equivalent circuit of the liquid crystal display panel.
FIGS. 5A to 5H are waveform diagrams showing the relationship between grayscale data and data signals applied to pixels.
FIGS. 6A to 6C are waveform diagrams of a scanning signal.
7 (a) and 7 (b) are enlarged waveform diagrams showing a part of the same waveforms as in FIG. 6, and FIG. 7 (c) is a waveform diagram of a pixel voltage.
FIG. 8 is a circuit diagram showing an equivalent circuit of a part of the drive circuit according to the second embodiment.
FIGS. 9A to 9C are waveform diagrams showing a scanning signal and a signal of a correction capacitance line.
10 (a) and 10 (b) are enlarged waveform diagrams showing a part of the same waveforms as in FIG. 9, and FIG. 10 (c) is a waveform diagram of a pixel voltage.
FIGS. 11A to 11C are waveform diagrams illustrating a part of a scanning signal in a third embodiment in an enlarged manner.
FIGS. 12A to 12C are waveform diagrams illustrating a part of a scanning signal according to a fourth embodiment in an enlarged manner.
FIG. 13 is a perspective view showing a personal computer using a liquid crystal display device.
FIG. 14 is an explanatory view of a conventional example.
[Explanation of symbols]
τ, τ2 period, V0, V1, V2 voltage, T period, Y0, Y1 to Ym scanning line, Clc, 31 liquid crystal capacitance, SF1 to SF7 subfield, X1 to Xn, 36, 37 signal Line, 24: liquid crystal as electro-optical material, 25: pixel, 26: thin film transistor (TFT) as switching element, 29: pixel electrode, 30: common electrode as counter electrode, 32: correction capacitance element as capacitance element, 40: gate line (wiring), 411 to 41m: correction capacitance wiring.

Claims (13)

A plurality of switching elements disposed at a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines, and driving the switching elements of each pixel in a matrix to apply a signal to a pixel electrode of each pixel; In an electro-optical device configured to write,
A correction capacitance element provided corresponding to the switching element, and a wiring to which the correction capacitance element is connected,
Writing a signal to the pixel electrode of each pixel at a frame frequency of 120 HZ or more,
An electro-optical device, wherein the potential of the wiring is changed after a signal is written to the pixel electrode, thereby correcting the pixel electrode potential of each pixel by a feed-through voltage. A plurality of switching elements disposed at a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines, and a matrix driving of the switching elements of each pixel to write a signal to each pixel. In the configured electro-optical device,
A correction capacitance element connected in parallel to the pixel electrode of each pixel, and a wiring to which the correction capacitance element of each pixel is connected,
One frame is divided into N sub-fields having a period corresponding to each bit of the N-bit grayscale data, and the frame is divided into one frame at a cycle of the shortest sub-field of the N sub-fields. Based on the grayscale data, one of the binary voltages is written to each of the pixels to perform ^2N grayscale display,
An electro-optical device wherein the potential of the wiring is changed after writing one of the binary voltages so that the pixel electrode potential of each pixel is corrected by a feed-through voltage. . A plurality of switching elements disposed at a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines, and a matrix driving of the switching elements of each pixel to write a signal to each pixel. In the configured electro-optical device,
A correction capacitance element connected in parallel to the pixel electrode of each pixel, and a wiring to which the correction capacitance element of each pixel is connected,
One frame is divided into 2 ^N -1 sub-fields having a period of the same length, and for each of the sub-fields, one of binary voltages is written to each of the pixels based on gradation data, and the 2 ^{N -th} order Display the key,
An electro-optical device wherein the potential of the wiring is changed after writing one of the binary voltages so that the pixel electrode potential of each pixel is corrected by a feed-through voltage. . 4. The device according to claim 1, wherein when an N-channel transistor is used as each of the switching elements, the pixel electrode potential of each of the pixels is corrected to a plus side by a feedthrough voltage. 5. An electro-optical device according to any one of the preceding claims. 4. The device according to claim 1, wherein when a P-channel transistor is used as each of the switching elements, a pixel electrode potential of each of the pixels is corrected to a minus side by a feedthrough voltage. 5. An electro-optical device according to any one of the preceding claims. A value that changes the potential of the wiring is a plus field in which one of the binary voltages is written as a positive signal to each of the pixels every predetermined period, and a negative signal is applied to each of the pixels. 6. The electro-optical device according to claim 1, wherein each of the two voltages is set individually in a minus field in which one of the two voltages is written. The wiring connected to the correction capacitance element of each pixel is individually connected to a gate line or the correction capacitance element connected to a preceding scanning line selected immediately before the plurality of scanning lines. 7. The electro-optical device according to claim 1, wherein the plurality of correction capacitance lines are provided. The pixel electrode of each pixel constitutes a liquid crystal capacity of each pixel together with a liquid crystal as an electro-optical material and a counter electrode provided between a pair of substrates, and a non-memory type liquid crystal is used as the liquid crystal. Item 8. The electro-optical device according to any one of Items 1 to 7. A plurality of switching elements disposed at a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines, and driving the switching elements of each pixel in a matrix to apply a signal to a pixel electrode of each pixel; A method of driving an electro-optical device configured to write,
Writing a signal to the pixel electrode of each pixel at a frame frequency of 120 HZ or more,
By changing the potential of the wiring connected to the correction capacitance element connected in parallel to the pixel electrode of each pixel after writing a signal to the pixel electrode, the potential of the pixel electrode of each pixel is reduced by the feedthrough voltage. A method for driving an electro-optical device, comprising: correcting. A plurality of switching elements disposed at a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines, and a matrix driving of the switching elements of each pixel to write a signal to each pixel. A driving method of the configured electro-optical device,
One frame is divided into N sub-fields having a period corresponding to each bit of the N-bit grayscale data, and the frame is divided into one frame at a cycle of the shortest sub-field of the N sub-fields. Based on the grayscale data, one of the binary voltages is written to each of the pixels to perform ^2N grayscale display,
The potential of a wiring connected to a correction capacitor connected in parallel to the pixel electrode of each pixel is changed after writing one of the binary voltages, so that the pixel electrode potential of each pixel is fed through. A method for driving an electro-optical device, wherein correction is performed by a voltage. A plurality of switching elements disposed at a plurality of pixels corresponding to intersections of a plurality of scanning lines and a plurality of signal lines, and a matrix driving of the switching elements of each pixel to write a signal to each pixel. A driving method of the configured electro-optical device,
One frame is divided into ^2N subfields having the same length of time, and for each of the subfields, one of binary voltages is written to each of the pixels based on the grayscale data and ^2N grayscales are written. Display,
The potential of a wiring connected to a correction capacitor connected in parallel to the pixel electrode of each pixel is changed after writing one of the binary voltages, so that the pixel electrode potential of each pixel is fed through. A method for driving an electro-optical device, wherein correction is performed by a voltage. A value that changes the potential of the wiring is a plus field in which one of the binary voltages is written as a positive signal to each of the pixels every predetermined period, and a negative signal is applied to each of the pixels. The method of driving an electro-optical device according to claim 11, wherein each of the two voltages is set individually in a minus field in which one of the two voltages is written. An electronic apparatus comprising the electro-optical device according to claim 1.

Images