CN101159301A - A semiconductor light emitting device and its manufacturing method - Google Patents
A semiconductor light emitting device and its manufacturing method Download PDFInfo
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Abstract
本发明公开了一种半导体发光器件,其包括衬底及层叠于衬底上的半导体外延叠层,该半导体外延叠层由下往上依次包含N型层、发光层和P型层。在衬底的下表面设置有一电极。在P型层的上表面设置有P型电极,其中,部分P型层被刻蚀到N型层,并设置有N型电极,同时在该区域N型层内设有一导电体,其一端与N型电极相连接,另一端与衬底电接触;该导电体由一柱状通孔及填充于通孔内的导电物质构成;该导电体还可延伸至衬底底部,并与衬底下表面的电极相连接。本发明能有效降低半导体发光器件的工作电压,及提高半导体发光器件的输出功率。另外,本发明还公开了一种半导体发光器件的制造方法。
The invention discloses a semiconductor light-emitting device, which comprises a substrate and a semiconductor epitaxial stack laminated on the substrate. The semiconductor epitaxial stack includes an N-type layer, a light-emitting layer and a P-type layer in sequence from bottom to top. An electrode is provided on the lower surface of the substrate. A P-type electrode is provided on the upper surface of the P-type layer, wherein a part of the P-type layer is etched to the N-type layer, and an N-type electrode is provided. The N-type electrode is connected, and the other end is in electrical contact with the substrate; the conductor is composed of a columnar through hole and a conductive substance filled in the through hole; the conductor can also extend to the bottom of the substrate and connect with the bottom surface of the substrate The electrodes are connected. The invention can effectively reduce the operating voltage of the semiconductor light emitting device and increase the output power of the semiconductor light emitting device. In addition, the invention also discloses a manufacturing method of the semiconductor light emitting device.
Description
技术领域technical field
本发明涉及一种半导体发光器件及其制造方法。The invention relates to a semiconductor light emitting device and a manufacturing method thereof.
背景技术Background technique
III-V族氮化物半导体材料广泛用于紫、蓝、绿和白光发光二极管,高密度光学存储用的紫光激光器,紫外光探测器,以及高功率高频电子器件。然而由于缺乏合适的衬底,目前高质量的GaN基材料膜通常都生长在蓝宝石或SiC衬底上,但是这两种衬底都比较昂贵,尤其是SiC,而且尺寸都比较小。此外,蓝宝石还有硬度极高、不导电、导热差等缺点。III-V nitride semiconductor materials are widely used in violet, blue, green and white light-emitting diodes, violet lasers for high-density optical storage, ultraviolet light detectors, and high-power high-frequency electronic devices. However, due to the lack of suitable substrates, current high-quality GaN-based material films are usually grown on sapphire or SiC substrates, but both substrates are relatively expensive, especially SiC, and are relatively small in size. In addition, sapphire has the disadvantages of extremely high hardness, non-conductivity, and poor thermal conductivity.
为克服上述缺点,人们在用Si作衬底生长GaN方面一直不断地进行探索,预期在Si衬底上异质外延生长III族氮化物发光器件在降低成本方面具有明显的技术优势。用Si作GaN基发光二极管(LED)衬底的优点主要在于LED的制造成本将大大降低,这不仅是因为Si衬底本身的价格比目前使用的蓝宝石和SiC衬底便宜很多,而且可以使用比蓝宝石和SiC衬底的尺寸更大的Si衬底以提高金属有机化学气相沉积(MOCVD)设备的利用率,从而提高芯片的产率。Si和SiC衬底一样,也是导电衬底,电极可以从芯片的上下引出形成垂直导电结构,有别于绝缘的蓝宝石衬底那样电极必须都从同一侧引出的侧向结构,这样不但可以有效利用芯片面积,还可以简化封装过程。同时可以使用Si集成电路加工中成熟的工艺制作LED芯片,节省了芯片生产成本。In order to overcome the above shortcomings, people have been continuously exploring the growth of GaN using Si as a substrate. It is expected that the heteroepitaxial growth of III-nitride light-emitting devices on Si substrates has obvious technical advantages in terms of cost reduction. The advantage of using Si as a GaN-based light-emitting diode (LED) substrate is that the manufacturing cost of the LED will be greatly reduced, not only because the price of the Si substrate itself is much cheaper than the currently used sapphire and SiC substrates, but also can be used Sapphire and SiC substrates have larger Si substrates to increase the utilization of metal-organic chemical vapor deposition (MOCVD) equipment, thereby increasing the yield of chips. Si and SiC substrates are also conductive substrates. The electrodes can be drawn out from the top and bottom of the chip to form a vertical conductive structure, which is different from the lateral structure of the insulating sapphire substrate where the electrodes must be drawn out from the same side. This can not only effectively utilize The chip area can also simplify the packaging process. At the same time, LED chips can be manufactured using the mature technology in Si integrated circuit processing, which saves the cost of chip production.
然而与蓝宝石和SiC相比,在Si衬底上生长GaN更为困难,这是因为Si与GaN材料之间的热失配和晶格失配更大。Si与GaN的热膨胀系数差别将导致GaN膜出现龟裂,大的晶格失配会在GaN外延层中造成高的位错密度。尽管Si衬底GaN基LED的制造技术已经取得了不少令人兴奋的结果,但是仍存在工作电压较高及输出功率较低的缺陷,一方面是由于Si与GaN的热膨胀系数存在较大失配导致GaN膜出现龟裂,晶格常数差会在GaN外延层中造成高的位错密度,Si衬底还存在严重的吸光问题,人们为了解决龟裂、晶格不匹配以及吸光问题,通常引入各种缓冲层(如AlN/GaN)及插入层(如解决吸光问题引入的DBR反射层),但是这些外来层的引入会额外增加器件的工作电压;另一方面,在GaN基LED结构中Si与GaN之间有较大的能带不连续性而使开启电压升高,以及晶体完整性差造成P型GaN掺杂效率低,导致串联电阻增大。解决Si衬底GaN基LED芯片工作电压高的问题,是Si衬底GaN基LED走向实用化的关键。However, compared to sapphire and SiC, it is more difficult to grow GaN on Si substrates because of the larger thermal and lattice mismatch between Si and GaN materials. The difference in thermal expansion coefficient between Si and GaN will cause cracks in the GaN film, and the large lattice mismatch will cause high dislocation density in the GaN epitaxial layer. Although the manufacturing technology of GaN-based LEDs on Si substrates has achieved many exciting results, there are still defects of high operating voltage and low output power. On the one hand, there is a large gap between the thermal expansion coefficients of Si and GaN. The GaN film is cracked due to the combination, and the difference in lattice constant will cause high dislocation density in the GaN epitaxial layer. The Si substrate also has serious light absorption problems. In order to solve the problems of cracking, lattice mismatch and light absorption, people usually Introduce various buffer layers (such as AlN/GaN) and insertion layers (such as the DBR reflective layer introduced to solve the light absorption problem), but the introduction of these foreign layers will increase the operating voltage of the device; on the other hand, in the GaN-based LED structure There is a large energy band discontinuity between Si and GaN, which increases the turn-on voltage, and poor crystal integrity results in low doping efficiency of P-type GaN, resulting in increased series resistance. Solving the problem of high operating voltage of GaN-based LED chips on Si substrates is the key to the practical application of GaN-based LEDs on Si substrates.
发明内容Contents of the invention
本发明的目的是提供一种能有效降低工作电压的半导体发光器件及其制造方法。The object of the present invention is to provide a semiconductor light-emitting device capable of effectively reducing the operating voltage and a manufacturing method thereof.
为了实现上述目的,本发明采用如下技术方案:In order to achieve the above object, the present invention adopts the following technical solutions:
一种半导体发光器件,其包括衬底及层叠于衬底上的半导体外延叠层,该半导体外延叠层由下往上依次包含N型层、发光层和P型层。在衬底的下表面设置有一电极。在P型层的上表面设置有P型电极,其中,部分P型层被刻蚀到N型层,并设置有N型电极,同时在该区域N型层内设有一导电体,其一端与N型电极相连接,另一端与衬底电接触。A semiconductor light-emitting device, which includes a substrate and a semiconductor epitaxial stack stacked on the substrate. The semiconductor epitaxial stack includes an N-type layer, a light-emitting layer and a P-type layer in sequence from bottom to top. An electrode is provided on the lower surface of the substrate. A P-type electrode is provided on the upper surface of the P-type layer, wherein a part of the P-type layer is etched to the N-type layer, and an N-type electrode is provided. The N-type electrodes are connected, and the other end is in electrical contact with the substrate.
该导电体由一柱状通孔及填充于通孔内的导电物质构成。The conductor is composed of a columnar through hole and a conductive material filled in the through hole.
该通孔为横截面呈圆形或方形等柱状通孔。The through hole is a columnar through hole with a circular or square cross section.
该导电体还可延伸至衬底底部,并与衬底下表面的电极相连接。The conductor can also extend to the bottom of the substrate and be connected to the electrodes on the lower surface of the substrate.
所述的半导体外延叠层或通孔的大小以及深度可以依据实际操作情况来具体设定。The size and depth of the semiconductor epitaxial stack or the through hole can be specifically set according to actual operating conditions.
为了解决半导体外延叠层龟裂、或与衬底晶格不匹配的问题,半导体外延叠层与衬底之间还设置有缓冲层。In order to solve the problem of cracks in the semiconductor epitaxial stack or lattice mismatch with the substrate, a buffer layer is also provided between the semiconductor epitaxial stack and the substrate.
为了解决衬底的吸光问题,该缓冲层与半导体外延叠层之间还设置有DBR反射层。In order to solve the light absorption problem of the substrate, a DBR reflective layer is also arranged between the buffer layer and the semiconductor epitaxial stack.
上述衬底由Si基材料形成,半导体外延叠层及DBR反射层均由铝镓铟氮(InxGayAl1-x-yN,0<=x<=1,0<=y<=1)材料形成。The above substrate is formed of Si-based material, and the semiconductor epitaxial stack and the DBR reflective layer are all made of aluminum gallium indium nitrogen (In x Ga y Al 1-xy N, 0<=x<=1, 0<=y<=1) material formed.
为了使得填充的导电物质与N型层侧壁以及Si衬底的完全接触,柱状通孔的填充物质可为各种金属或合金或导电树脂等任何导电材料,同时也可以是上述材料的任意组合。In order to make the filled conductive substance fully contact with the N-type layer sidewall and Si substrate, the filling substance of the columnar through hole can be any conductive material such as various metals or alloys or conductive resins, and can also be any combination of the above materials .
另外,本发明还提供了一种半导体发光器件的制造方法,其步骤包括:在Si衬底上沉积半导体外延叠层,该半导体外延叠层由下往上依次包括N型层、发光层和P型层;通过干法刻蚀将部分P型层刻蚀到N型层,在露出的N型层内刻蚀一区域,在该区域内形成一导电体,导电体一端露出N型层表面,另一端与Si衬底电接触;利用光刻工艺,在导电体顶端上定义N型电极区域,并在该区域蒸镀上N型电极;在P型层的上表面定义P型电极区域,并在该区域形成P型电极,在Si衬底的下表面蒸镀金属层,形成电极。In addition, the present invention also provides a method for manufacturing a semiconductor light-emitting device, the steps of which include: depositing a semiconductor epitaxial stack on a Si substrate, and the semiconductor epitaxial stack includes an N-type layer, a light-emitting layer, and a P layer from bottom to top. Type layer; Part of the P-type layer is etched to the N-type layer by dry etching, and a region is etched in the exposed N-type layer, and a conductor is formed in the region, and one end of the conductor is exposed on the surface of the N-type layer. The other end is in electrical contact with the Si substrate; using a photolithography process, define an N-type electrode region on the top of the conductor, and evaporate an N-type electrode on this region; define a P-type electrode region on the upper surface of the P-type layer, and A P-type electrode is formed in this region, and a metal layer is vapor-deposited on the lower surface of the Si substrate to form an electrode.
该导电体可由在N型层内刻蚀形成通孔及填充于通孔内的导电物质形成。The conductor can be formed by etching a through hole in the N-type layer and filling the conductive substance in the through hole.
上述通孔还可刻蚀至Si衬底内部或至Si衬底底部,并与衬底的下表面所形成电极接触。The through hole can also be etched to the inside of the Si substrate or to the bottom of the Si substrate, and be in contact with the electrode formed on the lower surface of the substrate.
本发明的半导体发光器件及其制造方法所提供的柱状通孔贯穿于整个半导体外延叠层,并部分或全部刻蚀穿衬底,该柱状通孔填充导电物质后,N型层通过导电物质与Si衬底或Si衬底下端的电极接触。工作时,流经P型电极的电流经过N型层后,大部分会通过低阻的导电物质向Si衬底流动,少部分经N型层直接流向Si衬底。一方面,N型层和Si衬底的电互联降低了传统的Si衬底半导体发光器件芯片由于额外层以及Si和半导体外延叠层势垒所引入的过高工作电压;另一方面,相对于蓝宝石衬底的半导体发光器件芯片而言,由于一部分电流会通过N型层直接流向Si衬底,这样,部分消除了绝缘的蓝宝石衬底芯片中的电流阻塞效应。The columnar through hole provided by the semiconductor light-emitting device and its manufacturing method of the present invention runs through the entire semiconductor epitaxial stack, and is partially or completely etched through the substrate. After the columnar through hole is filled with a conductive substance, the N-type layer passes through the conductive substance and The Si substrate or the electrode contact at the lower end of the Si substrate. When working, most of the current flowing through the P-type electrode will flow to the Si substrate through the low-resistance conductive material after passing through the N-type layer, and a small part will flow directly to the Si substrate through the N-type layer. On the one hand, the electrical interconnection between the N-type layer and the Si substrate reduces the excessive operating voltage introduced by the traditional Si substrate semiconductor light-emitting device chip due to the additional layer and the Si and semiconductor epitaxial stack barrier; on the other hand, compared to For semiconductor light-emitting device chips with sapphire substrates, since part of the current flows directly to the Si substrate through the N-type layer, the current blocking effect in the insulating sapphire substrate chips is partially eliminated.
因此,本发明可以显著降低半导体发光器件的工作电压,又能改善电流扩展效果,而Si衬底良好的导热性又能提高器件的热性能。同时,该工艺简单易行,不会增加过多的芯片制作成本。Therefore, the invention can significantly reduce the operating voltage of the semiconductor light-emitting device and improve the current spreading effect, while the good thermal conductivity of the Si substrate can improve the thermal performance of the device. At the same time, the process is simple and easy, and will not increase excessive chip manufacturing costs.
附图说明Description of drawings
图1是本发明实施例1的半导体发光器件的结构示意图。FIG. 1 is a schematic structural view of a semiconductor light emitting device according to
图2是本发明实施例2的半导体发光器件的结构示意图。Fig. 2 is a schematic structural view of a semiconductor light emitting device according to Embodiment 2 of the present invention.
图3是本发明实施例3的半导体发光器件的结构示意图。Fig. 3 is a schematic structural view of a semiconductor light emitting device according to Embodiment 3 of the present invention.
上述图中,1为衬底,3为导电物质,4为P型层,5为发光层,6为N型层,7为缓冲层,8为透明导电薄膜,9为P型电极,10为衬底下表面的电极,11为通孔顶部的N型电极,12为DBR反射层,13为柱状通孔。In the above figure, 1 is the substrate, 3 is the conductive material, 4 is the P-type layer, 5 is the light-emitting layer, 6 is the N-type layer, 7 is the buffer layer, 8 is the transparent conductive film, 9 is the P-type electrode, 10 is the The electrode on the lower surface of the substrate, 11 is the N-type electrode on the top of the through hole, 12 is the DBR reflective layer, and 13 is the columnar through hole.
具体实施方式Detailed ways
实施例1Example 1
参照图1,一种半导体发光器件,其包括衬底1及层叠于衬底1上的半导体外延叠层,该半导体外延叠层由下往上依次包含N型层6、发光层5和P型层4,该P型层4的上表面形成有一层透明导电薄膜8,在透明导电薄膜8上设置有P型电极9,该衬底1的下表面设置有电极10,其中,N型层6内设有一导电体,其一端露出N型层6,并设有一N型电极11,其另一端与衬底1电接触。With reference to Fig. 1, a kind of semiconductor light-emitting device, it comprises
该导电体由一柱状通孔13及填充于通孔13内的导电物质3构成。该通孔13为横截面呈圆形或方形的柱状通孔。The conductor is composed of a columnar through
为了使得填充的导电物质3与N型层6侧壁以及衬底1的完全接触,柱状通孔13填充的导电物质3可为各种金属或合金,如Au、Ag、Al、Ti、Ni、Cu、ITO、Pt、AuSb等,也可以为导电树脂等任何导电材料,同时也可以为上述材料的任意组合。为了防止器件发生短路,导电物质3与P型层4之间须留有一定间隔空间。In order to make the filled conductive substance 3 fully contact with the side wall of the N-
上述衬底1由Si基材料形成,半导体外延叠层由铝镓铟氮(InxGayAl1-x-yN,0<=x<=1,0<=y<=1)材料形成。The
为了解决半导体外延叠层龟裂、或与衬底1晶格不匹配的问题,半导体外延叠层与衬底1之间还设置有一缓冲层7。In order to solve the problem of cracks in the semiconductor epitaxial stack or lattice mismatch with the
该半导体发光器件制造方法包括以下步骤:The manufacturing method of the semiconductor light emitting device comprises the following steps:
先把Si衬底1清洗干净,放入金属有机化学气相沉积设备中,在Si衬底1上依次沉积缓冲层7及半导体外延叠层结构,该半导体外延叠层包括N型层6,多量子阱发光层5和P型层4。Clean the
半导体外延叠层沉积完成后,通过干法刻蚀,把图1中所示的区域刻除以形成一区域,并于该区域内形成一导电体,导电体的一端露出N型层6表面,另一端与Si衬底1电接触。After the deposition of the semiconductor epitaxial stack is completed, the region shown in FIG. 1 is etched by dry etching to form a region, and a conductor is formed in the region, and one end of the conductor exposes the surface of the N-
上述导电体由在N型层6内刻蚀形成的柱状通孔13及填充于通孔13内的导电物质3形成。该柱状通孔13穿过半导体外延叠层,直到接触Si衬底1,然后将通孔13外围区域刻蚀到N型层6以露出N型层6的表面,并使用磁控溅射或电镀工艺在通孔13中沉积导电物质3,以填充通孔13。The conductor is formed by the columnar through
采用光刻工艺,在通孔13顶端所在的N型层台面上定义N型电极区域,蒸镀N型电极11,退火形成欧姆接触,使得N型层6与Si衬底1通过导电物质3互联。Using a photolithography process, define an N-type electrode area on the N-type layer mesa where the top of the through
采用光刻工艺,在P型层4的上表面定义P型区域,在P型区域表面形成透明导电薄膜8;在透明导电薄膜8上定义P型电极区域,并在P型电极区域上蒸镀形成P型电极9;在Si衬底下表面蒸镀金属层,形成电极10。Using a photolithography process, define a P-type region on the upper surface of the P-type layer 4, and form a transparent conductive film 8 on the surface of the P-type region; define a P-type electrode region on the transparent conductive film 8, and vapor-deposit on the P-type electrode region A P-
将半导体外延叠层切割,形成独立的半导体发光器件芯片。The semiconductor epitaxial stack is cut to form independent semiconductor light emitting device chips.
本实施例中,透明导电薄膜8可以采用镍金合金氧化物(Oxidzed-Ni/Au)、氧化铟锡(ITO)、氧化锌铝(AZO)、氧化锌,以及它们的组合物(如Ni/AZO,NiO/AZO,Ni/ZnO,NiO/ZnO等)。In the present embodiment, the transparent conductive film 8 can adopt nickel-gold alloy oxide (Oxidzed-Ni/Au), indium tin oxide (ITO), zinc aluminum oxide (AZO), zinc oxide, and their compositions (such as Ni/ AZO, NiO/AZO, Ni/ZnO, NiO/ZnO, etc.).
其中,Ni/Au是利用电子束蒸镀(E-gun Evaporator)进行蒸镀,蒸镀的厚度为50/100;金属蒸镀之后,再将Ni/Au放在高温炉中,在氧气环境下进行550℃、5分钟的热处理,以形成Ni/Au的氧化物。Among them, Ni/Au is evaporated by electron beam evaporation (E-gun Evaporator), and the thickness of the evaporation is 50/100 Ȧ; Heat treatment at 550° C. for 5 minutes to form Ni/Au oxides.
ITO是利用电子束蒸镀机(E-gun Evaporator)进行沉积,沉积的厚度为2000-10000;ITO沉积后,再于RTA系统中、氮气环境下,进行600℃、5分钟的热处理以形成欧姆接触。ITO is deposited using an electron beam evaporation machine (E-gun Evaporator), and the thickness of the deposition is 2000-10000 Ȧ; after ITO is deposited, it is then heat-treated at 600 ° C for 5 minutes in an RTA system in a nitrogen environment to form ohmic contact.
AZO是利用离子溅射机(Sputter)进行沉积,沉积厚度为2500,为了改善AZO与P型层4间的欧姆接触特性,在沉积AZO前先在P型层4上分别蒸镀50的Ni、NiOx,之后再进行AZO的沉积。沉积完后,在氮气环境下以RTA系统进行800℃、1分钟的热处理。AZO is deposited using an ion sputtering machine (Sputter), and the deposition thickness is 2500 Ȧ. In order to improve the ohmic contact characteristics between AZO and the P-type layer 4, 50 Ȧ of 50 Ȧ were vapor-deposited on the P-type layer 4 before depositing AZO. Ni, NiOx, and then AZO deposition. After deposition, heat treatment is performed at 800° C. for 1 minute with an RTA system under a nitrogen atmosphere.
实施例2Example 2
如图2所示,本实施例与实施例1相似,其区别在于:本实施例为了降低衬底1的内阻,在刻蚀通孔13时可以全部贯穿整个衬底1,形成全通孔,并在通孔13中的填充入导电物质3,N型层6直接与衬底1下端的电极10通过导电物质3实现电接触。As shown in Figure 2, this embodiment is similar to
当然,根据实际应用中对半导体发光器件内阻的要求不同,通孔13也可部分贯穿衬底1。Of course, according to different requirements on the internal resistance of the semiconductor light emitting device in practical applications, the through
实施例3Example 3
如图3所示,本实施例与实施例1相似,其区别在于:本实施例为了提高半导体发光器件的出光效率,在衬底1与缓冲层7之间引入铝镓铟氮(InxGayAl1-x-yN,0<=x<=1,0<=y<=1)材料的DBR反射层12(典型结构为AlGaN/AlN等),这时的通孔13结构在干法刻蚀时,需刻蚀穿过DBR反射层12及缓冲层7到达衬底1。As shown in Figure 3, this embodiment is similar to
当然,根据实际应用中对半导体发光器件内阻的要求不同,采用与实施例2相似的方法,通孔13也可部分或全部贯穿衬底1。Of course, according to different requirements on the internal resistance of the semiconductor light emitting device in practical applications, the through
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CN102339913A (en) * | 2011-09-30 | 2012-02-01 | 映瑞光电科技(上海)有限公司 | High-voltage LED (Light Emitting Diode) device and manufacturing method thereof |
CN102593291A (en) * | 2011-01-07 | 2012-07-18 | 山东华光光电子有限公司 | Nitride distributed Bragg reflector (DBR) and manufacturing method and application thereof |
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CN102593291A (en) * | 2011-01-07 | 2012-07-18 | 山东华光光电子有限公司 | Nitride distributed Bragg reflector (DBR) and manufacturing method and application thereof |
CN102339913A (en) * | 2011-09-30 | 2012-02-01 | 映瑞光电科技(上海)有限公司 | High-voltage LED (Light Emitting Diode) device and manufacturing method thereof |
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JP2017084919A (en) * | 2015-10-27 | 2017-05-18 | 株式会社ディスコ | Led substrate forming method |
CN112289821A (en) * | 2016-04-14 | 2021-01-29 | 群创光电股份有限公司 | Display device |
CN114583026A (en) * | 2022-05-05 | 2022-06-03 | 徐州立羽高科技有限责任公司 | Novel semiconductor deep ultraviolet light source structure |
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