CN101157569A - Non-damage carborundum eroding method - Google Patents
Non-damage carborundum eroding method Download PDFInfo
- Publication number
- CN101157569A CN101157569A CNA2007101393351A CN200710139335A CN101157569A CN 101157569 A CN101157569 A CN 101157569A CN A2007101393351 A CNA2007101393351 A CN A2007101393351A CN 200710139335 A CN200710139335 A CN 200710139335A CN 101157569 A CN101157569 A CN 101157569A
- Authority
- CN
- China
- Prior art keywords
- sic
- high temperature
- masking layer
- etching
- damage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 36
- 230000003628 erosive effect Effects 0.000 title claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 39
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 22
- 230000006378 damage Effects 0.000 claims abstract description 11
- 230000007797 corrosion Effects 0.000 claims abstract description 10
- 238000005260 corrosion Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims description 20
- 230000000873 masking effect Effects 0.000 claims description 17
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000007792 gaseous phase Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 12
- 238000001312 dry etching Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000001039 wet etching Methods 0.000 abstract description 2
- 239000007795 chemical reaction product Substances 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 230000014509 gene expression Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 6
- 239000008367 deionised water Substances 0.000 description 5
- 229910021641 deionized water Inorganic materials 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000004506 ultrasonic cleaning Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000003467 diminishing effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Images
Landscapes
- Weting (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a lossless corrosion silicon carbide method which is applied in the field of SiC parts production. Different from the dry etching and the wet etching in the production of SiC parts, the method selectively oxidizes the SiC wafer to form the appearance required by the parts. Because of not introducing the affected layer of the dry etching method, the invention is the lossless corrosion silicon carbide in real sense. The main technique process consists of the deposition of a high-temperature shielding layer on the SiC wafer, the etching, the selection of a corrosive high temperature-resistant layer, the oxidization of the SiC wafer under high temperature, the removal of the reaction product, etc. The temperature for the oxidization of the invention ranges from 800DEG to 1,450DEG. The invention, when being used, does not injure the material, thereby avoiding the injuries of crystal lattice and reducing the density of the surface state.
Description
Technical field
The present invention relates to a kind of making method of silicon carbide device, especially relate to a kind of harmless making method of silicon carbide device.
Background technology
Silicon carbide (SiC) material physical properties and chemical property are stable, do not react with common corrosion reagent at normal temperatures, do not have suitable wet corrosion technique, and therefore, dry etch process becomes technology commonly used in the silicon carbide device preparation.But, because etching process ionic medium body must have certain energy and can guarantee etching speed, certain damage that this will certainly cause carbofrax material.Semiconducter device, as SiC MESFET (metal-semiconductor field effect transistor) is gated device, raceway groove is shorter, the device active region etching is required very harsh, the surfaces of active regions of crossing through plasma bombardment will form lattice damage, and gather a large amount of static electric charges, and and active area produced exhaust, can cause that the device saturation currnet diminishes, Schottky gate n value is bigger than normal, the direct current mutual conductance reduces, microwave power gains and efficient reduces etc. greatly.Shown in Figure 1 is is rich in static electric charge and SiC MESFET device active region is produced the synoptic diagram that exhausts with the channel surface of the SiC device of prior art etching.Wherein, the 1st, the source electrode of device, the 2nd, the drain electrode of device, the 3rd, the gate electrode of device, the 4th, the zone that channel surface exhausts behind the plasma bombardment, 5 the expression be that channel surface is rich in static electric charge, the 6th, the channel layer of device, the 7th, the buffer layer of device, the 8th, device substrate, the 9th, the contact layer of device.
Silicon (Si) device can be oxidized, and oxidation can generate high-quality SiO
2Layer, its SiO
2/ Si interface state density is very low, and repeatability and homogeneity are all very high, makes that oxidizing process has obtained using widely in large-scale integrated circuit.Similar to the Si material, the SiC material also can be oxidized under hot conditions.The method of existing oxidation SiC generally is applied in removes the material surface affected layer that dry etch process is brought, promptly remove the material surface affected layer that dry etch process causes by the way of oxidation sacrifice SiC material, simultaneously material is carried out high temperature annealing, damage in the dummy.The SiO that oxidizing reaction generates
2Layer also can be used for making passivation layer.
Summary of the invention
The technical issues that need to address of the present invention provide a kind of method of making silicon carbide device by oxidizing process.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is to adopt following manufacture craft process:
High temperature resistant masking layer is fallen in step 4 selective corrosion;
The used material of the present invention specifically can be: extension or single-chip are SiC matrix wherein a kind of of 4H or 6H.
High temperature resistant masking layer in the step 2 of the present invention is the Si by adopting chemical gaseous phase depositing process to obtain
3N
4
Because the technical progress of having adopted technique scheme, the present invention to obtain is:
The present invention utilizes the characteristics that SiC can be oxidized, adopt the method for oxidation, form mesa structure, its whole process of preparation is not introduced the processing step that increases material damage, the lattice damage of directly avoiding dry etching to bring to device active region, and reduce surface density of states.The big problem of material surface damage when so not only having solved dry etching, the while can reduce the surface state of corrosion surface.Method of the present invention is the method for a kind of undamaged corrosion SiC, it can be good at overcoming in the existing technology owing to plasma bombardment forms lattice damage, avoid gathering a large amount of static electric charges, many defectives such as prevent that device generation saturation currnet from diminishing, Schottky gate n value is bigger than normal, the direct current mutual conductance reduces, microwave power gain and efficient reduce greatly.Si
3N
4As high temperature resistant masking layer, obtain Si by adopting chemical gaseous phase depositing process
3N
4The corrosion of energy high temperature oxidation resisting atmosphere well prevents the silicon carbide layer generation oxidation of its covering.
Description of drawings
Fig. 1 is that the channel surface of the SiC device of prior art etching is rich in static electric charge and SiC MESFET device channel is produced the synoptic diagram exhaust.
Wherein, 1, the source electrode of device, 2, the drain electrode of device, 3, the gate electrode of device, 4, the zone that channel surface exhausts behind the plasma bombardment, 5, channel surface is rich in static electric charge, 6, the channel layer of device, 7, the buffer layer of device, 8, device substrate, 9, the contact layer of device.
Fig. 2 is the synoptic diagram of the basic craft course of method of the present invention to Fig. 5.
Wherein, 11, Si
3N
4, 12, SiC extension or single-chip, 13, the SiO that forms of oxidation
2
Embodiment
Below in conjunction with accompanying drawing the present invention is described in further details:
Step 1: the cleaning of extension (or single-chip)
At first adopted the acetone soln ultrasonic cleaning 5 minutes, with the ammoniacal liquor-H that puts into 50 ℃ behind the deionized water rinsing
2O
2-H
2The ratio of O is a ultrasonic cleaning 5 minutes in 1: 1: 6 the solution, washes down with deionized water once more, puts into HCl solution-H then
2O
2-H
2The ratio of O is to clean 5 minutes in 70 ℃ of hydrochloric acid solns of 1: 1: 5, puts into HF solution-H after deionized water washes down once more
2The ratio of O is to clean after 3 minutes in 1: 5 the solution to take out, and uses airing behind the deionized water cleaning down at last.
In technological process, can adopt the method for multiple cleaning epitaxial wafer, as long as can guarantee the cleaning on epitaxial wafer surface, purging method can be versatile and flexible.
Step 2: the high temperature resistant masking layer of deposit
The Si that the LPCVD method that adopts chemical vapour deposition is 2500 at 800 ℃ of following deposition thicknesses
3N
4Si
3N
4Here promptly as high temperature resistant masking layer.
The Si of deposit
3N
4Should be fine and close, otherwise can in oxidation, take place along Si
3N
4The phenomenon of hole undercutting SiC.
Step 3: photoetching
Can select suitable equipment as required, with high temperature resistant masking layer Si
3N
4Etch away, expose the SiC figure of thinking etching; High temperature resistant masking layer Si
3N
4Can adopt wet method or dry etching.
After Fig. 2 represents the cleaning of extension (or single-chip), deposit Si
3N
4, and further photoetching, corrosion Si
3N
4The surface topography that the back forms.Wherein 11 represent Si
3N
4, 12 expression SiC epitaxial wafer or single-chips.
The oxidation of step 4:SiC
Use wet oxygen under 1200 ℃, SiC to be carried out oxidation.
Fig. 3 represents the pattern that forms after the oxidation.Wherein 11 represent Si
3N
4, 12 expression SiC extension or single-chips, the SiO that 13 expression oxidations form
2
Step 5:SiO
2Removal with high temperature resistant masking layer
SiO
2With high temperature resistant masking layer Si
3N
4Can adopt wet method or dry etching, but preferentially use the HF wet etching to remove SiO
2
Fig. 4 represents to remove SiO
2The pattern that the back forms, wherein 11 expression Si
3N
4, SiO is removed in 12 expressions
2Remaining SiC extension in back or single-chip.
Fig. 5 represents to remove Si
3N
4The mesa structure pattern that the back forms, the mesa structure that extension that promptly obtains at last or single-chip form.
Step 6: clean
With deionized water the said products is cleaned again.
The difference of present embodiment and embodiment 1 is: in the step 2 be adopt PECVD 300 ℃ of following deposits the Si of 2000
3N
4Be to use wet oxygen that SiC is carried out oxidation in the step 4, the temperature of oxidation is 1000 ℃.
The difference of present embodiment and embodiment 1 is: adopt Ni (nickel) to make masking layer in the step 2; Use ICP equipment that the Ni masking layer is carried out dry etching in rapid 3.
The difference of present embodiment and embodiment 1 is: the oxidation in the step 4 is to carry out in dry oxygen ambient.
The oxidation of step 4 can also be done in addition, carry out in the wet oxygen blended atmosphere.
Claims (2)
1. the method for a non-damage carborundum eroding is used the wherein a kind of as substrate of the epitaxial wafer of silicon carbide or single-chip, it is characterized in that this method comprises following processing step:
The cleaning of step 1 substrate,
Step 2 deposits the high temperature resistant masking layer greater than 1000 ,
Step 3 photoetching exposes the SiC part of thinking etching,
High temperature resistant masking layer is fallen in step 4 selective corrosion,
Step 5 is carried out oxidation to exposing the SiC figure under 800 ℃～1450 ℃,
Step 6 erodes the SiO that oxidation generates
2And masking layer.
2. the method for a kind of non-damage carborundum eroding according to claim 1 is characterized in that the high temperature resistant masking layer in the described step 2 is the Si that obtains by the employing chemical gaseous phase depositing process
3N
4
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101393351A CN101157569B (en) | 2007-09-03 | 2007-09-03 | Non-damage silicon carbide eroding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101393351A CN101157569B (en) | 2007-09-03 | 2007-09-03 | Non-damage silicon carbide eroding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101157569A true CN101157569A (en) | 2008-04-09 |
| CN101157569B CN101157569B (en) | 2010-06-02 |
Family
ID=39305819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101393351A Expired - Fee Related CN101157569B (en) | 2007-09-03 | 2007-09-03 | Non-damage silicon carbide eroding method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101157569B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556919B (en) * | 2009-05-21 | 2014-03-05 | 中国电子科技集团公司第十三研究所 | Method for controlling step appearance of SiC matrix etching |
| CN105405749A (en) * | 2015-11-02 | 2016-03-16 | 株洲南车时代电气股份有限公司 | Method for etching silicon carbide |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1094653C (en) * | 1999-12-10 | 2002-11-20 | 中国科学院上海冶金研究所 | Technology for manufacturing chip of high-temp pressure sensor |
| JP2003124189A (en) * | 2001-10-10 | 2003-04-25 | Fujitsu Ltd | Method of manufacturing semiconductor device |
| CN1209793C (en) * | 2002-10-16 | 2005-07-06 | 中国科学院半导体研究所 | Horizontal epitaxial growth of gallium nitride and its compound semiconductor |
-
2007
- 2007-09-03 CN CN2007101393351A patent/CN101157569B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556919B (en) * | 2009-05-21 | 2014-03-05 | 中国电子科技集团公司第十三研究所 | Method for controlling step appearance of SiC matrix etching |
| CN105405749A (en) * | 2015-11-02 | 2016-03-16 | 株洲南车时代电气股份有限公司 | Method for etching silicon carbide |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101157569B (en) | 2010-06-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101024882B (en) | Cleaning solution for silicon surface and methods of fabricating semiconductor device using the same | |
| WO2017101535A1 (en) | Wet corrosion method of group iii nitride | |
| CN106298904A (en) | Nitridation gallio enhancement device with gallium nitride interposed layer and preparation method thereof | |
| CN107240605A (en) | A kind of GaN MIS raceway grooves HEMT device and preparation method | |
| CN103109372A (en) | Method for manufacturing semiconductor device and method for growing graphene | |
| CN111640797A (en) | Method for manufacturing semiconductor device | |
| US20070087573A1 (en) | Pre-treatment method for physical vapor deposition of metal layer and method of forming metal silicide layer | |
| CN101157569B (en) | Non-damage silicon carbide eroding method | |
| CN110504299A (en) | GaN groove anode Schottky diode preparation method based on graphical regrowth | |
| CN105826181B (en) | The method for preventing ONO structure scaling defects | |
| CN107230625A (en) | Gallium nitride transistor and its manufacture method | |
| CN100539083C (en) | The manufacture method of flush memory device | |
| CN102381718B (en) | Passivant and method for adopting passivant to realize surface pretreatment for germanium-base devices | |
| CN107045975A (en) | The preparation method for Ohmic contact of being slotted based on the gallium nitride-based material that self-stopping technology is etched | |
| CN104319237B (en) | Method for preparing graphene top gate field effect transistor device through self-alignment process | |
| CN110911485A (en) | Enhanced bidirectional blocking power GaN-based device based on P-type layer and manufacturing method | |
| CN103840003A (en) | Double-gate graphene transistor with aluminum oxide as gate dielectric and manufacturing method thereof | |
| CN209418507U (en) | A kind of normally-off SiC base DMOSFET device | |
| CN106653566A (en) | SiGe nanowire making method | |
| CN112542384A (en) | Manufacturing method of gallium nitride enhanced device | |
| CN110137075A (en) | The manufacturing method of autoregistration grapheme transistor is realized in a kind of ion implanting oxidation | |
| CN102054696A (en) | Method for forming source electrode and drain electrode | |
| CN103811556A (en) | Double-gate graphene transistor with silicon substrate and aluminium oxide gate dielectric, and preparation method | |
| CN109243973A (en) | A kind of method of etching silicon carbide | |
| CN109326522A (en) | A kind of preparation method of diamond heterojunction diode component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: HE BEI SINOPACK ELECTRONIC TECH Co.,Ltd. Assignor: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY Group Corp. Contract record no.: 2010130000045 Denomination of invention: Non-damage carborundum eroding method Granted publication date: 20100602 License type: Exclusive License Open date: 20080409 Record date: 20100810 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100602 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |