CN101154206A - 耦合设备、处理器装置、数据处理装置、传输数据的方法 - Google Patents
耦合设备、处理器装置、数据处理装置、传输数据的方法 Download PDFInfo
- Publication number
- CN101154206A CN101154206A CNA2007101676276A CN200710167627A CN101154206A CN 101154206 A CN101154206 A CN 101154206A CN A2007101676276 A CNA2007101676276 A CN A2007101676276A CN 200710167627 A CN200710167627 A CN 200710167627A CN 101154206 A CN101154206 A CN 101154206A
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- cache memory
- parallel
- serial
- Prior art date
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- 230000008878 coupling Effects 0.000 title claims abstract description 75
- 238000010168 coupling process Methods 0.000 title claims abstract description 75
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000005540 biological transmission Effects 0.000 title description 6
- 238000004891 communication Methods 0.000 claims description 3
- 238000013500 data storage Methods 0.000 claims description 2
- 238000007689 inspection Methods 0.000 claims description 2
- 230000014509 gene expression Effects 0.000 description 7
- 230000005055 memory storage Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
- G06F2212/2022—Flash memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (24)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110453608.6A CN102637153B (zh) | 2006-09-28 | 2007-09-28 | 耦合设备、处理器装置、数据处理装置、传输数据的方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US84786906P | 2006-09-28 | 2006-09-28 | |
US60/847869 | 2006-09-28 | ||
DE102006045903.2A DE102006045903B4 (de) | 2006-09-28 | 2006-09-28 | Prozessoranordnung mit einer Kopplungsvorrichtung zum Koppeln eines Speichers mit einem Prozessor, Datenverarbeitungsanordnung und Verfahren zum Übertragen von Daten |
DE102006045903.2 | 2006-09-28 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110453608.6A Division CN102637153B (zh) | 2006-09-28 | 2007-09-28 | 耦合设备、处理器装置、数据处理装置、传输数据的方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101154206A true CN101154206A (zh) | 2008-04-02 |
CN101154206B CN101154206B (zh) | 2012-03-14 |
Family
ID=39255871
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101676276A Expired - Fee Related CN101154206B (zh) | 2006-09-28 | 2007-09-28 | 耦合设备、处理器装置、数据处理装置、传输数据的方法 |
CN201110453608.6A Expired - Fee Related CN102637153B (zh) | 2006-09-28 | 2007-09-28 | 耦合设备、处理器装置、数据处理装置、传输数据的方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110453608.6A Expired - Fee Related CN102637153B (zh) | 2006-09-28 | 2007-09-28 | 耦合设备、处理器装置、数据处理装置、传输数据的方法 |
Country Status (2)
Country | Link |
---|---|
CN (2) | CN101154206B (zh) |
DE (1) | DE102006045903B4 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105653478A (zh) * | 2015-12-29 | 2016-06-08 | 致象尔微电子科技(上海)有限公司 | 串行闪存控制器、串行闪存控制方法及串行闪存控制系统 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5257359A (en) * | 1989-02-08 | 1993-10-26 | Hitachi Microsystems, Inc. | Instruction cache buffer with program-flow control |
US5404484A (en) * | 1992-09-16 | 1995-04-04 | Hewlett-Packard Company | Cache system for reducing memory latency times |
DE10040267A1 (de) * | 2000-08-17 | 2002-02-28 | Philips Corp Intellectual Pty | Prozessor-Speicher-System |
EP1320035A1 (en) * | 2001-12-11 | 2003-06-18 | Thomson Licensing S.A. | Storage device cache management |
US7010638B2 (en) * | 2003-08-29 | 2006-03-07 | Texas Intruments Incorporated | High speed bridge controller adaptable to non-standard device configuration |
KR101149816B1 (ko) * | 2004-05-28 | 2012-05-25 | 삼성전자주식회사 | 캐쉬 메모리의 캐쉬 히트 로직 |
KR100621631B1 (ko) * | 2005-01-11 | 2006-09-13 | 삼성전자주식회사 | 반도체 디스크 제어 장치 |
-
2006
- 2006-09-28 DE DE102006045903.2A patent/DE102006045903B4/de not_active Expired - Fee Related
-
2007
- 2007-09-28 CN CN2007101676276A patent/CN101154206B/zh not_active Expired - Fee Related
- 2007-09-28 CN CN201110453608.6A patent/CN102637153B/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105653478A (zh) * | 2015-12-29 | 2016-06-08 | 致象尔微电子科技(上海)有限公司 | 串行闪存控制器、串行闪存控制方法及串行闪存控制系统 |
CN105653478B (zh) * | 2015-12-29 | 2019-07-26 | 致象尔微电子科技(上海)有限公司 | 串行闪存控制器、串行闪存控制方法及串行闪存控制系统 |
Also Published As
Publication number | Publication date |
---|---|
DE102006045903A1 (de) | 2008-05-15 |
CN101154206B (zh) | 2012-03-14 |
CN102637153B (zh) | 2017-04-12 |
CN102637153A (zh) | 2012-08-15 |
DE102006045903B4 (de) | 2016-06-02 |
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Owner name: INTEL MOBILE COMMUNICATIONS TECHNOLOGY LTD. Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG Effective date: 20120522 Owner name: INTEL MOBILE COMMUNICATIONS LTD. Free format text: FORMER OWNER: INTEL MOBILE COMMUNICATIONS TECHNOLOGY LTD. Effective date: 20120522 |
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Effective date of registration: 20120522 Address after: Neubiberg, Germany Patentee after: Intel Mobile Communications GmbH Address before: German Neubiberg Patentee before: Infineon Technologies AG Effective date of registration: 20120522 Address after: Neubiberg, Germany Patentee after: Intel Mobile Communications GmbH Address before: Neubiberg, Germany Patentee before: Intel Mobile Communications GmbH |
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Address after: Neubiberg, Germany Patentee after: Intel Mobile Communications GmbH Address before: Neubiberg, Germany Patentee before: Intel Mobile Communications GmbH |
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CF01 | Termination of patent right due to non-payment of annual fee |
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